Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.

Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.

Abstract: An integrated circuit is formed by identifying process parameters of a plurality of process steps for the first partial lot containing the integrated circuit; confirming the number of wafers in the first partial lot is less than the wafer carrier capacity; examining lots upstream of the partial lot and identifying a second partial lot which can be combined with the first partial lot into a single wafer carrier and which can be processed with the first partial lot; combining the wafers of the partial lots into a single wafer carrier; processing the partial lots through the plurality of process steps; and performing a multi-lot verification process. The multi-lot verification process determines if all wafers in the partial lots have completed the process step; determines if any wafers in the partial lots are on hold; and determining if all wafers in the partial lots are in a same material carrier.

Abstract: A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.

Abstract: A method of optical proximity correction (OPC) includes the following steps. A layout pattern is provided to a computer system, and the layout pattern is classified into at least a first sub-layout pattern and at least a second sub-layout pattern. Then, at least an OPC calculation is performed respectively on the first sub-layout pattern and the second sub-layout pattern to form a corrected first sub-layout pattern and a corrected second sub-layout pattern. The corrected first sub-layout pattern/the corrected second sub-layout pattern and the layout pattern are compared to select a part of the corrected first sub-layout pattern/the corrected second sub-layout pattern as a first selected pattern/the second selected pattern, and the first selected pattern/the second selected pattern is further altered to modify the corrected first sub-layout pattern/the corrected second sub-layout pattern as a third sub-layout pattern/a fourth sub-layout pattern.

Abstract: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.

Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

Abstract: In an embodiment, a confidence interval of a yield is calculated with a set specification of an evaluation item and confidence level and values of the evaluation item obtained in Monte Carlo simulations to determine whether or not a target yield is within the confidence interval of the yield. In a case where the target yield is within the confidence interval of the yield, a Monte Carlo simulation executing unit is instructed to execute a subsequent Monte Carlo simulation. In a case where the target yield is not within the confidence interval of the yield, it is determined that the target yield will be achieved when a minimum value of the confidence interval of the yield is the target yield or larger while it is determined that the target yield will not be achieved when a maximum value of the confidence interval of the yield is below the target yield.

Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: Roughly described, a system enables quick and accurate depiction to a user of multi-patterning layout violations so that they may be corrected manually and in real time, and without interfering with normal manual editing process. In one embodiment, the system involves iteratively building tree structures with nodes identifying islands and arcs identifying multi-patterning spacing violations between the connected islands. The system detects coloring violations during the building of these tree structures, using the relationships previously inserted. The coloring violations preferably are reported to a user in the form of visual indications of the cycles among the candidate spacing violations, with the candidate spacing violations also themselves indicated visually and individually. The user can see intuitively how to move the islands around, and in which directions and by what distance, in order to remove a multi-patterning spacing violation and thereby break the cycle.

Abstract: A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

Abstract: A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A first shape is identified in a layout of the IC corresponding to the design as being apart by a first distance from a second shape. The first distance is a forbidden distance and at least equal to a minimum distance requirement of a lithography system. A determination is made that the first shape and the second shape are colored using a first color. The first shape is changed to a second color, such that even though the first distance is at least equal to the minimum distance requirement of the lithography system, the first and the second shapes are placed on different masks to print the design, thereby improving the printability of the design.

Abstract: The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape. As an illustrative embodiment to achieve the object, there are proposed a method of selecting a pattern by referring to a library, a method of creating a library by use of pattern cross-sectional shapes calculated through an exposure process simulation in advance, and a method for selecting a pattern shape stored in the library.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Among other things, one or more techniques for balancing mask loading are provided herein. In some embodiments, a dummy mask assignment is assigned to a dummy within a mask layout based on an area of a polygon within the mask layout. In some embodiments, the dummy mask comprising the dummy mask assignment is inserted in the mask layout. In some embodiments, a window is created such that dummies within the window receive dummy mask assignments. In some embodiments, a halo is created such that the area of the polygon is determined based on the halo. Additionally, in some examples, the window and halo are shifted around the mask layout. In this manner, balanced mask loading is provided, thus enhancing a yield associated with the mask layout, for example.

Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.

Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Abstract: The present invention provides an OPC method. First, a mask pattern is provided. A first region and a second region are detected in the mask pattern. The mask pattern comprises at least a first pattern in the first region and a second pattern in the second pattern, and the first pattern with a first width, a first gap with a first space, the second pattern with a second width and a second gap with a second space are disposed in sequence, wherein the second space value is substantially 2.5 to 3.5 times the value of the first width. Then, a modification process is performed by changing the arrangement of the mask pattern thereby making the mask pattern become a revised pattern, so the first pattern is not influenced by light passing through the second gap during an exposure process. Finally, the revised pattern is outputted onto a mask.

Abstract: A method for displaying layout-fixing hints for resolving color-seeding violations in an IC design layout. The method receives a set of error paths within a disjoint set of shapes. For each error path, the method performs an analysis on the error path to identify a set of layout-fixing hints that eliminates the color-seeding violation on the error path and does not introduce any new color-seeding violation. The method displays the set of identified hints for each error path in order to aid a user to resolve the color-seeding violations. The method displays each identified layout-fixing hint as a set of moving instructions. The set of moving instructions provides a set of indications of a distance by which a shape or an edge of the shape needs to be moved in order to resolve a color-seeding violation.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.

Abstract: A method and system for measuring layer overlay and for inspecting a mask for defects unrelated to overlay utilizing a singe comprehensive tool is disclosed. An exemplary method includes receiving a mask design database that corresponds to a mask and has a die area with a mask database feature. A mask image of the mask is received, and a comprehensive inspection system compares the mask image to the mask design database in order to detect mask defects that are not related to layer alignment. The system produces mask defect information corresponding to the mask defects. The comprehensive inspection system also compares the mask image to the mask design database to determine a database-to-mask offset. From the database-to-mask offset, a mask overlay characteristic is determined.

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. Outer markers are generated in the computing apparatus for at least a subset of the features based on the proximity of the features to one another and spacing requirements. Features are identified in the computing apparatus where the associated outer marker has at least one dimension greater than the dimensions specified for the feature.

Abstract: The process for designed based assessment includes the following steps. First, the process defines multiple patterns of interest (POIs) utilizing design data of a device and then generates a design based classification database. Further, the process receives one or more inspection results. Then, the process compares the inspection results to each of the plurality of POIs in order to identify occurrences of the POIs in the inspection results. In turn, the process determines yield impact of each POI utilizing process yield data and monitors a frequency of occurrence of each of the POIs and the criticality of the POIs in order to identify process excursions of the device. Finally, the process determines a device risk level by calculating a normalized polygon frequency for the device utilizing a frequency of occurrence for each of the critical polygons and a criticality for each of the critical polygons.

Abstract: In one embodiment, a method for aligning an image of a semiconductor device with a bitmap representation thereof includes receiving diffusion layer information of at least a portion of the semiconductor device, receiving implant layer information of the at least a portion of the semiconductor device, deriving distinct p- and n-doped region information from the received diffusion and implant layer information, generating the bitmap representation, including a differentiation between the distinct p- and n-doped regions, and performing an alignment operation of the image of the semiconductor device with generated bitmap representation.

Abstract: A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.

Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: A method of optical proximity correction (OPC) includes the following steps. At first, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into at least a first region and at least a second region. Then, several iterations of OPC calculations are performed to the layout pattern, and a total number of OPC calculations performed in the first region is substantially larger than a total number of OPC calculations performed in the second region. Afterwards, a corrected layout pattern is outputted through the computer system onto a mask.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated.

Abstract: A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks.

Abstract: There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

Abstract: A method and system for an IC design house to transfer design and layout information to a fabrication or failure analysis facility on a need-to-know basis to enable effective failure analysis while not providing unnecessary or extraneous information.

Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: Separation directives for integrated circuit layout design data are formed based upon one or more printing feasibility analyses performed on the layout design data. At least one printing feasibility analysis is performed on layout design data to identify portions of the design that may not be correctly formed or “printed” during a photolithographic process. The geometric element edges involved in a potential printing defect are then identified as edges to be formed using separate masks. Further, separation directives may be created to specifically designate the identified edges as edges to be formed using separate masks in a photolithographic manufacturing process.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

Abstract: A target pattern and a mask pattern are provided. The target pattern is segmented into a plurality of segments. Each segment includes at least one evaluation point. A first contour of a structure based on the mask pattern is simulated. A distortion between the first contour and the target pattern is evaluated at the evaluation point. At least one of the plurality of segments having a distortion exceeding a threshold value is identified. The identified segment is dissected into at least two sub-segments.

Abstract: A mask blank is provided by forming a plurality of films, including at least a thin film to be a transfer pattern, on a board. At the time of patterning a resist film of the mask blank according to pattern data, film information to check with a pattern is obtained for each of a plurality of the films.