Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: The present invention provides a computer-readable recording medium recording a program for causing a computer to execute a method of determining a pattern of a mask and an effective light source distribution with which the mask is illuminated, both of which are used for an exposure apparatus including an illumination optical system which illuminates a mask with light from a light source and a projection optical system which projects a pattern of the mask onto a substrate.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: Improved convergence in the volume-integral method (VIM) of calculating electromagnetic scattering properties of a structure is achieved by numerically solving a volume integral equation for a vector field, F, rather than the electric field, E. The electric field, E, is determined from the vector field, F, after solving of the volume integral equation. The vector field, F, may be related to the electric field, E, by a change of basis, and may be continuous at material boundaries where the electric field, E, has discontinuities. Convolutions of the vector field, F, are performed using convolution operators according to the finite Laurent rule, which allows for efficient matrix-vector products using Fast Fourier Transforms. An invertible convolution-and-change-of-basis operator, C, is configured to transform the vector field, F, to the electric field, E, by performing a change of basis according to material and geometric properties of the periodic structure.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: Some embodiments of the invention provide a method for automatically, accurately, and efficiently identifying double patterning (DP) loop violations in an IC design layout. The method of some embodiments identifies DP loop violations in a manner that eliminates false identification of DP loop violations without missing DP loop violations that should be identified. The method of some embodiments also generates a marker for each identified DP loop violation to indicate that a set of shapes associated with the marker forms the DP loop and displays the marker in the design layout.

Abstract: A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Abstract: A method for correcting topography proximity effects (TPE) for an integrated circuit (IC) design is described. This method includes dividing the IC design into a plurality of levels (z-direction). Each level can be decomposed into one or more elementary geometries. These elementary geometries can be top view geometries, cross-sectional geometries, half-plane geometries, geometries with single slope sides, and/or geometries with multiple slope sides. The one or more elementary geometries can be compared to primitives in a library. A transfer matrix can be generated using the matching primitives and the elementary geometries. A disturbance matrix can be calculated based on the transfer matrix. This disturbance matrix can advantageously capture a spectrum of a reflective electric field from a spectrum of an incident electric field. Wave propagation through a photoresist layer can be performed using the disturbance matrix for the plurality of levels.

Abstract: A method of constructing a mask for use in semiconductor device manufacturing is disclosed. A first shape that is related to mask construction is selected from a set of shapes. A second shape related to the mask construction is selected from the set of shapes. The first shape and the second shape are represented using a first shape vector and a second shape vector, respectively. A cluster is formed that includes the first shape and the second shape when the first shape vector and the second shape vector are within a selected criterion.

Abstract: A method of performing initial optical proximity correction (OPC) with a calibrated lithography simulation model. The method includes providing a photomask having an integrated circuit (IC) pattern formed thereon, acquiring an aerial image of the IC pattern formed on the photomask using an optical microscope, and calibrating an optical component of the lithography simulation model based on the aerial image. The method also includes exposing and developing a photoresist layer on a semiconductor wafer using the photomask to form a post-development pattern on the photoresist layer, acquiring a post-development image of the post-development pattern on the photoresist layer, and calibrating the photoresist component of the lithography simulation model based on the post-development image.

Abstract: A method of electron-beam lithography is provided, notably for technologies of critical dimension of the order of 22 nm. In such methods applied notably to networks of lines, the methods of the prior art do not offer precise and efficient correction of the shortenings of line ends. The method provided solves this problem by carrying out the insertion of contrast intensification structures of types which are optimized for the structure of the lines to be corrected. The method allows the semi-automatic or automatic calculation of the dimensions and locations of said structures. Advantageously, these calculations may be modeled to produce a target design, derived from libraries of components. They may be supplemented with a joint optimization of the size of the etchings and of the radiated doses, as a function of the process energy latitude.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: After layout design data has been modified using a resolution enhancement process, a repair flow is initiated. This repair flow includes checking a layout design altered by a resolution enhancement process for errors. A repair process is performed to correct detected sub-resolution assist feature errors. The repair process may employ a rule-based sub-resolution assist feature technique, a model-based sub-resolution assist feature technique, an inverse lithography-based sub-resolution assist feature technique, or any combination thereof.

Abstract: Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture an IC based on the IC layout. The process defines a set of design rules based on the specified manufacturing configuration. The process uses the set of design rules to design the IC layout. Some embodiments of the invention provide a design aware process for manufacturing an integrated circuit (“IC”). The process receives an IC design with an associated set of design properties. The process specifies a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manufacture the IC, where the specified set of manufacturing settings are based on the set of design properties. The process manufactures the IC based on the manufacturing settings.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, context and visible portions. An inverse lithography process is then performed on the core portion of the re-correction region while taking into account effects from the context portion of the re-correction region to generate a first modified re-correction region. A traditional OPC process is then performed on the core and context portions of the first modified re-correction region while taking into account effects from the visible portion of the first modified re-correction region to generate a second modified re-correction region.

Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.

Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.

Abstract: A method of optical proximity correction (OPC) includes the following steps. A layout pattern is provided to a computer system, and the layout pattern is classified into at least a first sub-layout pattern and at least a second sub-layout pattern. Then, at least an OPC calculation is performed respectively on the first sub-layout pattern and the second sub-layout pattern to form a corrected first sub-layout pattern and a corrected second sub-layout pattern. The corrected first sub-layout pattern/the corrected second sub-layout pattern and the layout pattern are compared to select a part of the corrected first sub-layout pattern/the corrected second sub-layout pattern as a first selected pattern/the second selected pattern, and the first selected pattern/the second selected pattern is further altered to modify the corrected first sub-layout pattern/the corrected second sub-layout pattern as a third sub-layout pattern/a fourth sub-layout pattern.

Abstract: The present invention provides a decision method which decides a mask pattern used in an exposure apparatus comprising a projection optical system that projects a mask pattern including a main pattern and an auxiliary pattern onto a substrate, and an exposure condition in the exposure apparatus, the method including a step of calculating an image of a mask pattern formed on the substrate by the projection optical system while changing settings of the mask pattern and the exposure condition, and deciding the mask pattern and the exposure condition based on the image of the mask pattern, wherein the step includes determining whether or not to generate a new auxiliary pattern after the settings are changed.

Abstract: The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour.

Abstract: The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Abstract: A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation.

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Abstract: Aspects of the invention relate to techniques for improving speed and consistency of OPC processes based on pattern matching. Pattern matching may be performed on a layout design to determine one or more arrays in the layout design that comprise arrays of identical layout patterns of which each matches a reference pattern. The one or more arrays may then be partitioned into core portions and boundary portions. The OPC process information for the reference pattern may be applied to the core portions, while a conventional OPC process may be performed on the boundary portions and layout regions outside of the one or more arrays.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.

Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.

Abstract: One embodiment relates to a computer method of evaluating proposed edits to a target layer of an integrated circuit. In the method, a number of editable regions is determined for metal layers overlying the target layer, where an editable region for a metal layer is laterally arranged between segments of the metal layer. The method identifies a number of possible vertical milling paths that extend from an exterior surface of the integrated surface to the target layer. Each possible vertical milling path passes through at least one editable region. The method generates a number of possible edit plans that are based on both the proposed edits and the number of possible vertical milling paths, where each edit plan places edits in a different combination of possible vertical milling paths.

Abstract: A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

Abstract: A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is disposed around the first main feature. A model-based feature is generated around the first main feature. An overlap Boolean feature is extracted from the rule-based features, wherein the overlap Boolean feature overlaps with the model-based feature in an overlap ratio up to a target value. The overlap Boolean feature serves as an assistant feature, and the assistant feature and the first main feature constitute a transfer feature.

Abstract: A block management method for OPC model calibration includes calculating differences in several different optical functions between first patterns of a first mask and patterns of a second mask corresponding to the first patterns but differing therefrom by a predetermined bias, selecting one or more of the optical functions based on the calculated differences, clustering data of variations in the values of the calculated differences in the selected ones of the optical functions, selecting respective ones of the first patterns in consideration of how the data clusters, and designating the selected first patterns as test patterns.

Abstract: A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A charged particle beam writing apparatus and a charged particle beam writing method capable of shortening the time necessary to generate shot data and improving writing throughput. A graphic pattern defined in write data is divided into graphics represented in shot units. The divided graphics are temporarily stored in a memory and are distributed to their corresponding subfield areas while developing position information defined in a state of being compressed to write data. When each pattern is written by multi-pass writing, graphics divided at a first pass are used for distribution to subfield areas after a second pass.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.

Abstract: A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8 W1 to 1.3 W1. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is ?2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.

Abstract: The present invention provides an OPC method. First, a mask pattern is provided. A first region and a second region are detected in the mask pattern. The mask pattern comprises at least a first pattern in the first region and a second pattern in the second pattern, and the first pattern with a first width, a first gap with a first space, the second pattern with a second width and a second gap with a second space are disposed in sequence, wherein the second space value is substantially 2.5 to 3.5 times the value of the first width. Then, a modification process is performed by changing the arrangement of the mask pattern thereby making the mask pattern become a revised pattern, so the first pattern is not influenced by light passing through the second gap during an exposure process. Finally, the revised pattern is outputted onto a mask.

Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.

Abstract: A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.

Abstract: Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a process window is defined. Aberrations induced by a lens manipulator are characterized in a manipulator model and the process window is optimized using the manipulator model. Aberrations are characterized by identifying variations in critical dimensions caused by lens manipulation for a plurality of manipulator settings and by modeling behavior of the manipulator as a relationship between manipulator settings and aberrations. The process window may be optimized by minimizing a cost function for a set of critical locations.

Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.

Abstract: A complex two-dimensional layout of a photomask or other three-dimensional object is systematically decomposed into a finite number of elementary two-dimensional objects with the ability to cause one-dimensional changes in light transmission properties. An algorithmic implementation of this can take the form of creation of a look-up table that stores all the scattering information of all two-dimensional objects needed for the synthesis of the electromagnetic scattered field from the original three-dimensional object. The domain is decomposed into edges, where pre-calculated electromagnetic field from the diffraction of isolated edges is recycled in the synthesis of the near diffracted field from arbitrary two-dimensional diffracting geometries. The invention has particular applicability in die-to-database inspection where an actual image of a mask is compared with a synthesized image that takes imaging artifacts of comers, edges and proximity into account.