Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Abstract: A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.

Abstract: A hotspot correction method is provided. The layout patterns in the hotspot regions are accurately corrected by using an ILT method. Then the layout patterns in the extension regions are corrected by using an OPC method. As a result, the layout patterns in the hotspot regions can be accurately corrected while pattern distortion of the extension regions generated due to the regional ILT correction can be prevented. Moreover, high demanding of calculation capability and long calculation time of global ILT correction can be avoided.

Abstract: A dimension measuring apparatus for measuring a dimension between a first data contour which is an evaluation reference of a pattern to be evaluated and a second data contour which is the pattern to be evaluated generates first correspondence information between a point on the first data contour and a point on the second data contour, determines consistency of a correspondence included in the first correspondence information, corrects an inconsistent correspondence, and generates second correspondence information, when associating a point on the first contour data and a point on the second contour data with each other.

Abstract: According to certain aspects, the present embodiments relate to an inverse lithography technology (ILT) solution that provides masks with perfect symmetry and minimal complexity. A methodology according to the embodiments includes several steps and strictly maintains symmetry in each of these steps. In one step, lithographic model kernels are processed to enforce symmetry corresponding to an illumination source. In another step, an ideal grayscale mask for a target pattern is computed using the symmetrical model kernels and computation domain centered on each target polygon. In another step optimized polygons are computed using the computed grayscale mask. The final mask perfectly maintains the symmetry properties of the illumination source. An ILT solution according to the embodiments can be used on an original design hierarchy and on a full chip scale.

Abstract: An efficient OPC method of increasing imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and optimizing target gray level for each evaluation point in each OPC iteration based on this function. In one given embodiment, the function is approximated as a polynomial function of focus and exposure, R(?,ƒ)=P0+ƒ2·Pb with a threshold of T+V? for contours, where PO represents image intensity at nominal focus, ƒ represents the defocus value relative to the nominal focus, ? represents the exposure change, V represents the scaling of exposure change, and parameter “Pb” represents second order derivative images. In another given embodiment, the analytical optimal gray level is given for best focus with the assumption that the probability distribution of focus and exposure variation is Gaussian.

Abstract: Aspects of the disclosed technology relate to techniques of pattern matching. Matching rectangles in a layout design that match rectangle members of a search pattern are identified based on edge operations. The rectangle members comprise an origin rectangle member and one or more reference rectangle members. Grid element identification values are attached to the matching rectangles. The matching rectangles that match the one or more reference rectangle members in neighborhoods of the matching rectangles that match the origin rectangle member are then analyzed. The neighborhoods are determined based on the grid element identification values. Based on the analysis, matching patterns in the layout design that match the search pattern are determined.

Abstract: An IC manufacturing model is disclosed, wherein input variables and an output variable are measured using a calibration set of patterns. The model can or cannot include a PSF. The output variable may be a dimensional bias between printed patterns and target patterns or simulated patterns. It can also be a Threshold To Meet Experiments. The input variables may be defined by a metric which uses kernel functions, preferably with a deformation function which includes a shift angle and a convolution procedure. A functional or associative relationship between the input variables and the output variable is defined. Preferably this definition includes normalization steps and interpolation steps. Advantageously, the interpolation step is of the kriging type. The invention achieves a much more accurate modeling of IC manufacturing, simulation or inspection processes.

Abstract: There are provided system and method of performing metrology operations related to a specimen. The method comprises: generating an examination recipe in accordance with a metrology application, the examination recipe specifying one or more metrology objects and one or more metrology operations related to the metrology application; obtaining an image-based representation of the specimen and a design-based representation of the specimen; mapping between the design-based representation of at least first metrology object and the image-based representation of at least first metrology object; and performing at least first metrology operation of the one or more metrology operations according to the examination recipe using the mapping, the at least first metrology operation specified as related to the at least first metrology object and to be performed on at least the image-based representation of the specimen.

Abstract: The invention relates to a method and device for characterizing at least one optical aberration of an optical system of an image acquisition device, the optical system having an associated optical transfer function that is dependent on the aberrations, the image acquisition device being capable of acquiring at least two images in a field of image capture in a manner so as to introduce a differential aberration between the two images, each image being defined by a digital image signal. The method includes the obtaining (50) of a first image and a second image of a same given zone of the field of image capture, the second image being acquired with a differential aberration (?aberr) relative to the first image, each image acquisition having an associated optical transfer function.

Abstract: A non-transitory computer readable storage medium according to an embodiment stores a mask evaluation program evaluating a mask used to manufacture an integrated circuit device. The program causes a computer to realize a convolutional neural network. The convolutional neural network output a calculated value of second data when first data is input. The first data corresponds to a circuit pattern of the mask. The second data corresponds to a pattern formed by the mask. The convolutional neural network has a filter and a weighting coefficient learned to reduce an error of the calculated value and an actual measured value of the second data by using the first data and the actual measured value of the second data.

Abstract: In an assist pattern arrangement method according to an embodiment, a plurality of patterns, in which an assist pattern is to be arranged, are extracted from a design pattern that is prepared in advance. Then, a resolution map of the extracted pattern is calculated. The resolution map includes a first pattern that increases a resolution of the pattern and a second pattern that decreases the resolution of the pattern. After the resolution map is calculated, a plurality of calculated resolution maps are added. Then, the assist pattern is arranged on the design pattern on the basis of the addition result.

Abstract: Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Abstract: A method for designing a semiconductor device includes establishing boundary conditions for a layout of each cell of a plurality of cells, wherein each cell has a plurality of features, and boundary conditions are established based on a proximity of each feature to a cell boundary of a corresponding cell. The method includes determining whether the layout of each cell is colorable based on a number of masks used to manufacture a layer of the semiconductor device, a minimum spacing requirement for the plurality of features, and the established boundary conditions. The method includes forming a layout of the layer of the semiconductor device by abutting a first cell of the plurality of cells with a second cell of the plurality of cells. The method includes reporting the layout of the layer of the semiconductor device as colorable without analyzing the layout of the layer of the semiconductor device.

Abstract: According to one embodiment, a layout region of a mask pattern is divided into N (N is an integer of 2 or larger) units, a main pattern resolved by exposure light is arranged and sub patterns not resolved by the exposure light are arranged outside the main pattern such that distributions of attenuation amount of the exposure light in the divided layout regions are different.

Abstract: A method, system, and non-transitory computer readable medium for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern include inserting an internal dummy between a first portion of the guiding pattern and a second portion of the guiding pattern if a vertical spacing is equal to or greater than a first predetermined distance, inserting a first external dummy along an external edge of the guiding pattern in a vertical direction if the vertical spacing is greater than a second predetermined distance, and inserting an anti-taper structure on the first external dummy if a second distance from the external edge of the guiding pattern to an edge of the first external dummy is greater than a first distance.

Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: The disclosure relates to a method for verifying a printed pattern. In an example embodiment, the method includes defining sectors of at least a portion of the features in the reference pattern, determining a contour of the printed pattern, and superimposing the contour of the printed pattern on the reference pattern. The method also includes determining surface areas of sectors of the printed pattern that correspond to the sectors of the reference pattern and calculating one or more parameters as a function of at least one of the surface areas, the parameters being related to a single sector or to multiple sectors. The method additionally includes evaluating the parameters with respect to a reference value.

Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.

Abstract: A system and method that includes receiving a layout of an integrated circuit (IC) device. A template library is provided having a plurality of parameterized shape elements. A curvilinear feature of layout is classified by selecting at least one of the parameterized shape elements that defines the curvilinear feature. A template index is associated with the layout is formed that includes the selected parameterized shape element. The template index and the layout can be delivered to a mask writer, which uses the template index and the layout to fabricate a pattern on a photomask.

Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.

Abstract: Systems and methods may provide for projection of a plurality of structured light patterns. In one example, the method may include generating a low-resolution pattern image utilizing a returned image, wherein the low-resolution pattern image is an approximation of an image that would have been generated utilizing a low-resolution pattern and generating a high-resolution pattern image utilizing a preprocessed returned image and a preprocessed low-resolution pattern image, wherein high-resolution pattern image is an approximation of an image that would have been generated utilizing a high-resolution pattern.

Abstract: Aspects of the invention relate to techniques for determining pattern optical similarity in lithography. Optical kernel strength values for a first set of layout features and a second set of layout features are computed first. Based on the optical kernel strength values, optical similarity values between the first set of layout features and the second set of layout features are then determined. Subsequently, calibration weight values for the first set of layout features may be determined based on the optical similarity values, which, along with the first set of layout features, may be employed to calibrate lithography process model parameters.

Abstract: According to an embodiment, a method for generating a 3-D stereo structure comprises registering and rectifying a first image frame and a second image frame by local correction matching, extracting a first scan line from the first image frame, extracting a second scan line from the second image frame corresponding to the first scan line, calculating a pixel distance between the first scan line and the second scan line for each pixel for a plurality of pixel shifts, calculating a smoothed pixel distance for each pixel for the pixel shifts by filtering the pixel distance for each pixel over the pixel shifts, and determining a scaled height for each pixel of the first scan line, the scaled height comprising a pixel shift from among the pixel shifts corresponding to a minimal distance of the smoothed pixel distance for the pixel.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level.

Abstract: Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output.

Abstract: Mask data is analyzed for the presence of a notch. A notch candidate on a polygon boundary of mask data is defined as a plurality of line segments that includes an initial line segment, a final line segment and at least two line segments therebetween. The initial and final line segments define adjacent edges of the notch candidate. A direction of each line segment is a direction of travel from the initial line segment to the final line segment.

Abstract: A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level.

Abstract: A photomask includes a focus metrology mark region that includes a plurality of focus monitor patterns. To measure a focal variation of a feature pattern formed on a substrate, a substrate target for lithography metrology including a focus metrology mark formed on the same level as the feature pattern is used. A lithography metrology apparatus includes a projection device including a polarizer; a detection device detecting the powers of ±n-order diffracted light beams from among output beams diffracted by the focus metrology mark of a to-be-measured substrate; and a determination device which determines, from a power deviation between the ±n-order diffracted light beams, defocus experienced by the feature pattern.

Abstract: A method for configuring a via in a semiconductor device includes determining time dependent dielectric breakdown failure rate as a function of distance between the via and a metal line, generating candidate via configurations with different sizes, rotation, and offset values for the via, determining TDDB failure rate for the candidate via configurations, and selecting one of the candidate via configurations with an optimal TDDB failure rate for the via.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout.

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract: A charged particle beam writing apparatus includes a correction term calculation processing circuitry to calculate a correction term which corrects an error of a proximity effect density of a figure pattern to be written, compared against the figure pattern at design stage, a proximity effect correction dose coefficient calculation processing circuitry to calculate a proximity effect correction dose coefficient for correcting a proximity effect, by using the correction term, a dose calculation processing circuitry to calculate a dose of a charged particle beam by using the proximity effect correction dose coefficient, and a writing mechanism to write the figure pattern on a target object by using the charged particle beam whose dose is the dose calculated.

Abstract: Among other things, one or more systems and techniques for tier based layer modification, such as promotion or demotion, for a design layout are provided herein. A metal scheme describes one or more metal layers of the design layout, which are grouped into a set of tiers based upon resistivity similarity between the metal layers. Wire segments of the design layout are evaluated for promotion to tiers providing improved performance, for demotion to tiers providing decreased performance so that relatively faster routing resources are freed up for other wire segments, or for modification such as widening of wire segments. Via count penalties corresponding to timing delays of additional vias used to reassign wire segments are taken into account during promotion. Routing resource gains associated with reassigning wire segments are taken into account during demotion. In this way, wire segments of the design layout are promoted, demoted, or modified.

Abstract: A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium.

Abstract: Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer.

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract: Systems and methods for detecting defects on a wafer are provided. One method includes determining locations of all instances of a weak geometry in a design for a wafer. The locations include random, aperiodic locations. The weak geometry includes one or more features that are more prone to defects than other features in the design. The method also includes scanning the wafer with a wafer inspection system to thereby generate output for the wafer with one or more detectors of the wafer inspection system. In addition, the method includes detecting defects in at least one instance of the weak geometry based on the output generated at two or more instances of the weak geometry in a single die on the wafer.

Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: Systems and methods for classifying defects on a wafer are provided. One method includes dilating an extended bounding box (EBB) surrounding a defect position on a wafer in two dimensions in proportion to a width and height of a pattern of interest (POI) for a hot spot closest to the defect position. The method also includes determining if polygons in the POI match polygons in the dilated bounding box. If the polygons in the POI do not match the polygons in the dilated bounding box, the defect is classified as a non-hot spot defect. If the polygons in the POI match the polygons in the dilated bounding box, the defect is classified as a hot spot defect if the area of the EBB intersects the area of interest associated with the hot spot and a non-hot spot defect if the EBB area does not intersect the area of interest.

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract: The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a patterning sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed.

Abstract: Optical simulation can be performed employing a calibrated printing model, in which a unique phase transmission value is assigned to each type of sub-resolution assist features (SRAFs). The printing model can be calibrated employing a mask including multiple test patterns. Each test pattern is defined by a combination of a main feature, at least one SRAF applied to the main feature, and the geometrical relationship between the main feature and the at least one SRAF. Generation of the phase transmission values for each SRAF can be performed by fitting a printing model employing phase shift values and/or transmission values for SRAFs with measured printed feature dimensions as a function of defocus and/or with measured SRAF printing behavior on a printed photoresist layer. A properly calibrated printing model can predict the printed feature dimensions, shift in the best focus, and presence or absence of printed SRAFs.

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.