Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes generating a photomask for forming a DSA directing pattern on a semiconductor substrate. The DSA directing pattern is configured to guide a self-assembly material deposited thereon that undergoes directed self-assembly (DSA) to form a DSA pattern. Generating the photomask includes using a computing system, inputting a DSA target pattern and an initial pattern. An output mask writer pattern is produced from the initial pattern using the computing system, the DSA target pattern, a DSA model, an OPC model, and a MPC model. The output mask writer pattern is for a mask writer to write on the photomask.

Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: A method of reducing current leakage in product variants of a semiconductor device, during the fabrication of the semiconductor device. The method involves using a semiconductor process technique for reducing current leakage in semiconductor product variants having unused circuits. A semiconductor device or integrated circuit fabricated by this method has reduced current leakage upon powering as well as during operation. The method involves semiconductor process technique that substantially increases the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors.

Abstract: Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: According to one embodiment, a method for generating mask data is configured to form a circuit pattern on a substrate using a directed self-assembly material. The method includes extracting a first region, setting a second region and setting a third region. The first region does not existing in the circuit pattern and existing in an initial pattern. The initial pattern includes a plurality of interconnect patterns extending in a first direction. The second region is formed by elongating the first region in a second direction intersecting the first direction. The second region straddles the first region in the second direction. The third region includes at least one of the second regions. The directed self-assembly material is disposed in the third region.

Abstract: Mask data is analyzed for the presence of a notch. A notch candidate on a polygon boundary of mask data is defined as a plurality of line segments that includes an initial line segment, a final line segment and at least two line segments therebetween. The initial and final line segments define adjacent edges of the notch candidate and have an angle therebetween within a defined range. A direction of each line segment is a direction of travel from the initial line segment to the final line segment. A plurality of conditions is applied to the plurality of line segments and the direction of travel, and the notch candidate is a notch when all conditions are satisfied. The notch may be removed from the data before mask writing.

Abstract: A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

Abstract: Provided is an integrated circuit (IC) testline layout. The layout has a device boundary and a main pattern boundary inside the device boundary. The layout includes at least one main pattern inside the main pattern boundary. The layout further includes a plurality of dummy patterns in a region that is between the main pattern boundary and the device boundary. The plurality of dummy patterns is printable in a photolithography process and is arranged in a ring with a uniform spacing between two adjacent dummy patterns.

Abstract: A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour.

Abstract: A method of optical proximity correction executed by a computer system for modifying line patterns includes the following steps. First, providing an integrated circuit layout with parallel line patterns and interconnect patterns disposed corresponding to the parallel line patterns. Then, using the computer to modify the integrated circuit layout based on a position of the interconnect patterns so as to generate a convex portion and a concave portion respectively on two sides of each of the parallel line patterns. Portions of the line pattern in front of and behind the convex portion and the concave portion are straight lines and have an identical critical dimension.

Abstract: A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Abstract: A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image.

Abstract: A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract: Computer-implemented method, system and computer program product for double patterning technology (DPT) odd loops visualization within an integrated circuit design layout are disclosed. The method, system and computer program product comprise mapping all violations of the integrated circuit design layout to a graph. The method, system and computer programming product also includes partitioning the graph into a plurality of sub-graphs. Each of the plurality of sub-graphs includes multiple edges and multiple nodes. The method, system and computer product further include detecting all possible odd loops in each of the plurality of sub-graphs; and visualizing all of the odd loops in at least one of the plurality of sub-graphs.

Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.

Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.

Abstract: An enhanced optical proximity correction method is provided. The method includes providing a mask substrate and a substrate and obtaining a customer target pattern. The method also includes obtaining a production layout by performing an optical proximity correction process onto the customer target pattern using the pattern and a pattern formed on the substrate. Further, the method includes obtaining the light intensity information instead of dimension of the production layout. Further, the method includes storing the light intensity information of the production layout, the production layout and surrounding coherence radius in an optical proximity correction model database if the light intensity information of the production layout does not coincide with light intensity information of original modeling patterns already stored in the optical proximity correction model database.

Abstract: A hybrid OPC process and a resulting reticle are disclosed. Embodiments include generating a finfet fin reticle including a first portion having regular pitches and a second portion having irregular pitches, performing rule based OPC on at least the first portion, and performing OPC repair locally at the second portion.

Abstract: A method and system for fracturing or mask data preparation or proximity effect correction is disclosed in which a series of charged particle beam shots is determined, where the series of shots is capable of forming a continuous non-manhattan track on a surface, such that the non-manhattan track has a line width roughness (LWR) which nearly equals a target LWR. A method and system for fracturing or mask data preparation or proximity effect correction is also disclosed in which at least two series of shots are determined, where each series of shots is capable of forming a continuous non-manhattan track on a surface, and where the space between tracks has space width roughness (SWR) which nearly equals a target SWR.

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract: Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.

Abstract: Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation.

Abstract: A method of performing optical proximity correction for preparing a mask projected onto a wafer by photolithography includes the following steps. An integrated circuit layout design including a first feature and a second feature is obtained, wherein the first feature overlaps a first boundary of two structures in the wafer. An edge of the first feature close to the second feature pertaining to a specific trend section of an experimental chart having trend sections is recognized. An optical proximity correction value is evaluated for the edge through a computer system according to a rule corresponding to the specific trend section. The layout design is compensated with the optical proximity correction value.

Abstract: A computer-implemented method for obtaining values of one or more design variables of one or more design rules for a pattern transfer process comprising a lithographic projection apparatus, the method comprising. simultaneously optimizing one or more design variables of the pattern transfer process and the one or more design variables of the one or more design rules. The optimizing comprises evaluating a cost function that measures a metric characteristic of the pattern transfer process, the cost function being a function of one or more design variables of the pattern transfer process and one or more design variables of the one or more design rules.

Abstract: Systems, methods, and other embodiments associated with dynamically generating jog patches are described. In one embodiment, a method includes determining a virtual edge within metal of a design at a jog rule violation. The design is a design of an integrated circuit and the virtual edge is an edge of a rectangle associated with one or more edges of the jog rule violation. The example method may also include dynamically generating a jog patch by expanding the metal from the virtual edge.

Abstract: Methods and systems for designing a binary spatial filter based on data indicative of a desired exposure condition to be emulated by an inspection system, and for implementing the binary spatial filter in an optical path of the inspection system, thereby enabling emulation of the desired exposure condition by interacting a light beam of the inspection system with the binary spatial filter. The present method and systems enable on-the-fly and on-demand design and implementation/generation of spatial filters for use in inspection systems.

Abstract: The invention discloses a computer implemented method of fracturing a surface into elementary features wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it will be advantageous to perform a second fracturing step using eRIFs. These eRIFs will be positioned either on the edges or on the medial axis or skeleton of the desired pattern. The invention further discloses method steps to define the position and shape of the elementary features used for the first and second fracturing steps.

Abstract: A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.

Abstract: A method of making a photomask layout is provided. A graphic data of a photomask is provided. The graphic data includes at least one rectangular pattern. A correction step is performed to the graphic data by using a computer. The correction step includes adding a substantially ring-shaped pattern inside the rectangular pattern. A method of forming a photomask by using the photomask layout obtained by the said method is also provided. In an embodiment, the photomask is suitable for defining micro-lenses of a solid-state image sensor.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A method of manufacturing an optical lithography mask includes providing a patterned layout design comprising a plurality of polygons, correcting the patterned layout design using optical proximity correction (OPC) by adjusting widths and lengths of one or more of the plurality of polygons, to generate a corrected patterned layout design, converting the corrected patterned layout design into a mask writer-compatible format, to generate a mask writer-compatible layout design comprising the plurality of polygons, and biasing each polygon in the plurality of polygons with a bias that accounts for large-scale density values of the patterned layout design, to generate a biased, mask writer-compatible layout design.

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract: An advanced correction method is provided. A target layout pattern is provided, and is corrected by a correction model to obtain a corrected pattern. A simulation is performed on the corrected pattern to obtain a simulation contour. A plurality of off-target evaluation points are established on the simulation contour, the simulation contour is compared with a target layout pattern, and a plurality of risk weighting values of each of the off-target evaluation points are obtained. A risk sum value obtained by summing up the risk weighting values of each of the off-target evaluation points is sorted into a processing sequence in descending manner. The target layout pattern is identified, classified and grouped into a plurality of pattern blocks. The corrected pattern is modified according to the processing sequence, so as to converge the simulation contour of the corrected pattern being modified to be close to the target layout pattern.

Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.

Abstract: A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare.

Abstract: A method may be implemented for obtaining calibration data for use in calibrating an optical proximity correction model. The method may include capturing an image for each portion of a plurality of portions of a wafer to obtain captured images. The method may further include assembling at least portions of the captured images to form an assembled image. The method may further include mapping layout data of the wafer with the assembled image. The method may further include selecting portions of the assembled image based on the layout data of the wafer. The method may further include obtaining data associated with the portions of the assembled image as the calibration data.

Abstract: A method of forming a mask includes creating a difference map between a desired intra-field pattern that is to be formed on substrates and an intra-field signature pattern. The intra-field signature pattern represents a pattern formed on an example substrate by an exposure field using an example E-beam-written mask. Modifications are determined to formation of mask features to be made using an E-beam mask writer if forming a modified E-beam-written mask having mask features modified from that of the example E-beam-written mask that will improve substrate feature variation identified in the difference map. The E-beam mask writer is programmed using the determined modifications to improve the substrate feature variation identified in the difference map. It is used to form the modified E-beam-written mask having the modified mask features. One or more substrates are photolithographically processed using the modified E-beam-written mask.

Abstract: A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns.

Abstract: A method for mask process correction or forming a pattern on a resist-coated reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle, and where the pattern exposure information is modified to lower the calculated sensitivity. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a resist-coated reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where the sensitivity of the wafer pattern is calculated with respect to changes in resist exposure of the reticle.

Abstract: Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.