Abstract: A charged particle beam writing apparatus includes a storage unit configured to store writing data in which there are defined a plurality of figures and resizing information indicating, with respect to each of the plurality of figures, a resizing status whether or not to perform resizing and a resizing direction used when performing resizing, a judgment determination unit configured to input the writing data and judge, with respect to each of the plurality of figures, the resizing status whether or not to perform resizing and the resizing direction used when performing resizing, a resize processing unit configured to resize, with respect to each of the plurality of figures, a dimension of a figure concerned in a judged resizing direction when it is judged to perform resizing, and a writing unit configured to write a pattern onto a target workpiece with using a resized figure and a charged particle beam.

Abstract: A method of SRAF printing using etch-aware SRAF print avoidance engines and the resulting device are provided. Embodiments include performing mask to resist simulations for a mask having both a plurality of features to be formed on a substrate and a plurality of sub resolution assist features (SRAFs); detecting SRAFs of the plurality that will print through to a resist; checking dimensions of the detected SRAFs to determine whether one or more of the SRAFs will etch through to the substrate; modifying the one or more of the SRAFs; and forming the mask after the one or more of the SRAFs have been modified.

Abstract: Aspects of the invention relate to techniques for applying edge fragment correlation information to optical proximity correction. Conventional edge adjustment values for the edge fragments are first derived from edge placement error values. Neighbor-aware edge adjustment values for the edge fragments are then computed based on the edge placement error values, the conventional edge adjustment values and edge fragment correlation information. The computation comprises: calculating pseudo edge placement error values by subtracting neighboring edge movement contribution values from the edge placement error values and calculating the neighbor-aware edge adjustment values based on the pseudo edge placement error values. The computed neighbor-aware edge adjustment values are combined with conventional edge adjustment values and the edge fragments are adjusted accordingly. The process may be repeated for a number of times.

Abstract: A photolithography mask design is simplified. In one example, a target mask design is optimized for a photolithography mask. Medial axes of the design and assist features on the optimized mask are identified. These are simplified to lines. Lines that are distant from a respective design feature are pruned. The remaining lines are simplified and then thickened to form assist features.

Abstract: An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar set of shapes). A set of points will be identified along the edges of the first set of shapes (e.g., at corners of the edges and at positions along the edges that are in alignment with corners of adjacent shapes) to yield an initial mask output. This initial mask output will be copied to the second set of shapes to yield a final mask output which may then be outputted using such an optimized fragmentation scheme.

Abstract: The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

Abstract: A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Abstract: Approaches for generating test cases for design rule checking are provided. A method includes extracting coordinates of an error marker in an integrated circuit design. The method also includes creating an error polygon using the coordinates. The method additionally includes selecting polygons in the design that touch the error polygon. The method further includes identifying a rectangle that encloses the selected polygons. The method also includes generating a test case based on data of the design contained within the rectangle. The extracting, the creating, the selecting, the identifying, and the generating are performed using a computer device.

Abstract: Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area element.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design.

Abstract: Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature.

Abstract: A method and system for fracturing or mask data preparation is disclosed in which the central core portion of a diagonal pattern is fractured using overlapping variable shaped beam (VSB) shots, and an outer portion of the diagonal pattern is fractured using non-overlapping VSB shots. A transition region is interposed between the central core and outer pattern portions, and transition region shots are generated so as to produce in the transferred pattern a smooth transition in pattern characteristics such as line edge roughness or period of waviness, from the central core portion of the pattern to the outer portion of the pattern. Methods for forming a semiconductor device layout pattern on a reticle or substrate are also disclosed.

Abstract: Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps.

Abstract: Candidate layout patterns can be assessed using a sparse pattern dictionary of known design layout patterns by determining sparse coefficients for each candidate pattern, reconstructing the respective candidate pattern, and determining reconstruction error. Any pattern with reconstruction error over a threshold value can be flagged. Compressive sampling can be employed, such as by projecting each candidate pattern onto a random line or a random matrix. The dictionary can be built by determining sparse coefficients of known patterns and respective basis function sets using matching pursuit, variants of SVD, and/or other techniques.

Abstract: An optical proximity correction (OPC) method is disclosed, in which original design patterns are first grouped into a first group and a second group, wherein each pattern of the first group has a size greater than a size of any pattern of the second group. Next, a simple OPC model and a complex OPC model are individually established for the two groups using different numbers of convolution kernels. After that, the simple OPC model and the complex OPC model are combined together to generate a hybrid OPC model which is thereafter used to perform an OPC treatment on the original design patterns. This method is capable of shortening the OPC processing time and increasing the flexibility in utilizing OPC software and hardware resources.

Abstract: An inspection data generator generates inspection data used to inspect a pattern transferred onto the same material layer using exposure processes. An input part of the generator receives first layout data for a mask used in a first exposure process and second layout data for a mask used in a second exposure process, and receives a measured value of a misalignment between a first transfer pattern actually transferred onto the material layer in the first exposure process and a second transfer pattern actually transferred onto the material layer in the second exposure process. A processor unit generates the inspection data by shifting the first layout data and the second layout data from each other by an amount corresponding to the measured value and then combining the first layout data with the second layout data. An output part outputs the inspection data to inspect the pattern transferred onto the material layer.

Abstract: A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern.

Abstract: A new approach is proposed that contemplates systems and methods to support block-based compression of a compound image by skipping “don't care” blocks in the layers of the image while neither introducing significant overhead nor requiring changes to the compression method used. The block-based compression approach first segments a compound image into multiple layers and then recomposes a new set of image layers, possibly with new dimensions, from only the non-“don't care” blocks in the layers of the original image. The approach may later decompress the compressed image layers and restore the image by copying the decompressed blocks to their respective positions in the original image.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: A process and apparatus are provided for generating and evaluating one or more metrics for analyzing the design and manufacture of semiconductor devices. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Abstract: Graph analysis for double pattern lithography is described. Layout shapes are decomposed into rectangles and a vertex is provided for each rectangle. Double pattern spacing conflicts are determined and shown as edges for the graph analysis. Odd cycles are used to identify double pattern lithography violations. Cycles can be completed with the addition of edges between vertices where stitches have been included in the layout. Edges between touching shapes do not count toward the odd count in the cycles. Fixes are included by increasing space or by rerouting. A portion of the layout can be incrementally changed and a local update of the graph analysis performed. Correct by construction layout is implemented by avoiding certain odd cycle prone layout routings.

Abstract: A method and a computer system for designing an optical photomask for forming a prepattern opening in a photoresist layer on a substrate wherein the photoresist layer and the prepattern opening are coated with a self-assembly material that undergoes directed self-assembly to form a directed self-assembly pattern. The methods includes: generating a mask design shape from a target design shape; generating a sub-resolution assist feature design shape based on the mask design shape; using a computer to generate a prepattern shape based on the sub-resolution assist feature design shape; and using a computer to evaluate if a directed self-assembly pattern of the self-assembly material based on the prepattern shape is within specified ranges of dimensional and positional targets of the target design shape on the substrate.

Abstract: An electron beam lithography method and apparatus for improving throughput is disclosed. An exemplary lithography method includes receiving a pattern layout having a pattern layout dimension; shrinking the pattern layout dimension; and overexposing a material layer to the shrunk pattern layout dimension, thereby forming the pattern layout having the pattern layout dimension on the material layer.

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Abstract: The invention provides for the acceleration of a source mask optimization process. In some implementations, a layout design is analyzed by a pattern matching process, wherein sections of the layout design having similar patterns are identified and consolidated into pattern groups. Subsequently, sections of the layout design corresponding to the pattern groups may be analyzed to determine their compatibility with the optical lithographic process, and the compatibility of these sections may be classified based upon a “cost function.” With further implementations, the analyzed sections may be classified as printable or difficult to print, depending upon the particular lithographic system. The compatibility of various sections of a layout design may then be utilized to optimize the layout design during a lithographic friendly design process. For example, during the design phase, sections categorized as difficult to print may be flagged for further optimization, processing, or redesign.

Abstract: A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer.

Abstract: The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method.

Abstract: Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area element.

Abstract: A hybrid OPC process and a resulting reticle are disclosed. Embodiments include generating a finfet fin reticle including a first portion having regular pitches and a second portion having irregular pitches, performing rule based OPC on at least the first portion, and performing OPC repair locally at the second portion.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask.

Abstract: Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography.

Abstract: A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.

Abstract: A target pattern is provided including a first pattern in a first region. A sensor pattern is inserted in the target pattern in the first region. A flare intensity of the sensor pattern in the first region is determined. A pattern bias is determined based on the flare intensity.

Abstract: A method for optical proximity correction (OPC) is disclosed, in which a set of VSB shots is determined, where the set of shots can approximately form a target reticle pattern that is an OPC-compensated version of an input pattern. The set of shots is simulated to create a simulated reticle pattern. A substrate image is calculated, based on using the simulated reticle pattern in an optical lithographic process to form the substrate image. A system for OPC is also disclosed.

Abstract: Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: One embodiment of a method for process window optimized optical proximity correction includes applying optical proximity corrections to a design layout, simulating a lithography process using the post-OPC layout and models of the lithography process at a plurality of process conditions to produce a plurality of simulated resist images. A weighted average error in the critical dimension or other contour metric for each edge segment of each feature in the design layout is determined, wherein the weighted average error is an offset between the contour metric at each process condition and the contour metric at nominal condition averaged over the plurality of process conditions. A retarget value for the contour metric for each edge segment is determined using the weighted average error and applied to the design layout prior to applying further optical proximity corrections.

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: The invention discloses a computer implemented method of fracturing a surface into elementary features wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it will be advantageous to perform a second fracturing step using eRIFs. These eRIFs will be positioned either on the edges or on the medial axis or skeleton of the desired pattern. The invention further discloses method steps to define the position and shape of the elementary features used for the first and second fracturing steps.

Abstract: One embodiment of the present invention provides techniques and systems for modeling mask errors based on aerial image sensitivity. During operation, the system can receive an uncalibrated process model which includes a mask error modeling term which is based at least on an aerial image sensitivity to mask modifications which represent mask errors. Next, the system can fit the uncalibrated process model using measured CD data. Note that the mask error modeling term can also be dependent on the local and/or long-range pattern density. In some embodiments, the mask error modeling term can include an edge bias term and a corner rounding term. The edge bias term can be based on the sensitivity of the aerial image intensity to an edge bias, and the corner rounding term can be based on the sensitivity of the aerial image intensity to a corner rounding adjustment.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask.

Abstract: Aspects of the invention relate to techniques of optical simulation for topographically non-uniform substrates. A layout design is simulated to generate an aerial image based on optical models for different types of substrates and for transition regions, along with models for one or more categories of light signals. The one or more categories of light signals comprise trench side-wall reflection signals, trench radiation signals, and trench corner diffraction signals. The one or more categories of light signals may further comprise gate scattering signals and interconnect scattering signals. The models for the one or more categories of light signals may be calibrated with experimental data.

Abstract: A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.

Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.

Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.