Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.

Abstract: A pattern designing method, including the steps of carrying out transfer simulation calculation and step simulation calculation by using physical layout data produced from circuit design data, and comparing a result of the transfer simulation calculation and the step simulation calculation with a preset standard; and carrying out calculation for electrical characteristics by using parameters obtained from the physical layout when as a result of the comparison, the preset standard is fulfilled, and carrying out calculation for the electrical characteristics by reflecting the result of the transfer simulation calculation and the step simulation calculation in the parameters when as the result of the comparison, the preset standard is not fulfilled, thereby extracting the parameters.

Abstract: A method of determining a pattern of a mask to be used in an exposure apparatus. The mask is arranged on an object plane of a projection optical system. The method includes calculating a value of a first evaluation function used to evaluate a cost of drawing a provisional pattern on a mask blank to manufacture the mask, calculating a value of a second evaluation function used to evaluate an image of the provisional pattern, which is formed on an image plane of the projection optical system when a mask having the provisional pattern is arranged on the object plane, and changing the provisional pattern. The calculations are repeated, and the provisional pattern is determined as the pattern of the mask, when the value of the first evaluation function meets a first predetermined standard and the value of the second evaluation function meets a second predetermined standard.

Abstract: Improved masks for double patterning lithography are described. In one example, conflict spaces between features of a target design are identified. The conflict spaces are represented as nodes of a graph. Connections are inserted between nodes based on a local search. The connections are cut to determine double patterning mask assignment. The connections are extended to form a checkerboard that is then overlayed on the target mask design to split the features of the target mask design for double patterning.

Abstract: A mask set for double exposure process and method of using said mask set. The mask set is provided with a first mask pattern having a first base and a plurality of first teeth and protruding portions, and a second mask pattern having a second base and a plurality of second teeth, wherein the second base may at least partially overlap the first base such that each of the protruding portions at least partially overlaps one of the second teeth.

Abstract: According to one embodiment, a method for producing a mask layout of an exposure mask for forming wiring of an integrated circuit device, includes estimating shape of the wiring formed based on an edge of a pattern included in an initial layout of the exposure mask. The method includes modifying shape of the edge if the estimated shape of the wiring does not satisfy a requirement.

Abstract: A three dimensional (3D) stacked integrated circuit (IC) design-for-Testing (DfT) die-level wrapper boundary register having a bypass mode and design-level DfT delay recovery techniques are provided. Die wrappers that contain boundary registers at the interface between dies can be inserted into 3D ICs where the boundary registers include a gated scan flop with a bypass line passing the functional input to a through-silicon-via (TSV) in a manner avoiding the clocked stages of the gated scan flop during functional operation. A retiming process can be applied during design layout using a simulation/routing tool or standalone program to recover the additional delay added to the TSV paths by the DfT insertion. Retiming can be performed at both die and stack level, and in further embodiments, logic redistribution across adjacent dies of the stack can be performed for further delay optimization.

Abstract: A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The features removed include features that have been determined to print correctly, duplicate features and features that are not sensitive to variations in process conditions. The revised target layout is analyzed to determine if the features that remain will print correctly on a wafer.

Abstract: Systems and methods for process aware metrology are provided. One method includes selecting nominal values and one or more different values of process parameters for one or more process steps used to form the structure on the wafer, simulating one or more characteristics of the structure that would be formed on the wafer using the nominal values, and determining parameterization of the optical model based on how the one or more characteristics of the structure vary between at least two of the nominal values and the one or more different values.

Abstract: A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described.

Abstract: According to one embodiment, a pattern data generating apparatus comprises a storage unit that stores a table defining direct self assembly information that combines a direct self assembly material, a film thickness of the direct self assembly material, and a process condition for the direct self assembly material according to a pattern dimension, a division unit that divides layout data of a device based on the pattern dimension to generate divided layouts, an extraction unit that extracts the direct self assembly information corresponding to the pattern dimension of the divided layout from the table, and a generation unit that generates pattern data by allocating the direct self assembly information extracted by the extraction unit to the divided layouts.

Abstract: Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such as optical proximity correction.

Abstract: Aspects of the invention relate to techniques for integrating optical proximity correction and mask data preparation. First mask writer instructions for a layout design are simulated to generate a mask contour. Based on the generated mask contour, first layout data for the layout design are adjusted for optical proximity correction to generate second layout data. Using the generated second layout data as mask target, the first mask writer instructions are adjusted to generate second mask writer instructions. The above process may be iterated until an end condition is met.

Abstract: Model-Based Sub-Resolution Assist Feature (SRAF) generation process and apparatus are disclosed, in which an SRAF guidance map (SGM) is iteratively optimized to finally output an optimized set of SRAFs as a result of enhanced signal strength obtained by iterations involving SRAF polygons and SGM image. SRAFs generated in a prior round of iteration are incorporated in a mask layout to generate a subsequent set of SRAFs. The iterative process is terminated when a set of SRAF accommodates a desired process window or when a predefined process window criterion is satisfied. Various cost functions, representing various lithographic responses, may be predefined for the optimization process.

Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

Abstract: The present invention provides a generation method of generating data of patterns of a plurality of masks used in an exposure apparatus for exposing a substrate, including a step of specifying, from a plurality of points on a grid having pattern elements to be formed on the substrate as intersections, an allowable point that allows a pattern to be transferred other than points of target pattern elements constituting a target pattern to be formed on the substrate, and a step of, for a pattern element group including a target pattern element whose distance to an adjacent target pattern element is shorter than a resolution limit of the exposure apparatus, grouping the adjacent target pattern elements on the grid a space between which is filled with the allowable point.

Abstract: The invention discloses a computer implemented method of fracturing a surface into elementary features wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it will be advantageous to perform a second fracturing step using eRIFs. These eRIFs will be positioned either on the edges or on the medial axis or skeleton of the desired pattern. The invention further discloses method steps to define the position and shape of the elementary features used for the first and second fracturing steps.

Abstract: Aspects of the invention relate to techniques of layout decomposition for triple patterning lithography. Data of a coloring graph are derived from layout data for a layout design. The coloring graph is simplified through graph reduction and graph partitioning processes. The graph partitioning process comprises separating biconnected components. The graph partitioning process may further comprise separating subgraphs connected by one or two edges. Based on the simplified coloring graph, the layout design is decomposed to generate decomposition information. The decomposition process may comprise applying a heuristic method for coloring if needed. The decomposition information may comprise information of one or more layout regions that cannot be decomposed.

Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.

Abstract: An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts 32 (structural features) are provided within the circuit design so as to force allocation of functional contacts (structural features) of the matched devices into the same pattern layer thereby reducing inter-device variation in contact position and/or size.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask.

Abstract: A circuit layout method comprises inputting layout data into a circuit layout system. The layout data represents a plurality of patterns in a plurality of cells. Each pattern of the plurality of patterns has a plurality of runs, ends, and corners. The method also comprises specifying a plurality of G1-rule criteria. The method further comprises reviewing a representation of G0-space and G0 rule violations for each cell of the plurality of cells. The method additionally comprises inputting an adjustment to the layout data. The method also comprises reviewing a representation of adjusted cell edge spacings, and selecting to output a final layout.

Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.

Abstract: A method of generating a layout for a device includes receiving a first layout including a plurality of active regions, each active region of the plurality of active regions having sides. The method further includes defining a plurality of elongate mandrels that each extend in a first direction and are spaced apart from one another in a second direction perpendicular to the first direction. The method further includes for each adjacent pair of partially-parallel active regions of the plurality of active regions having a minimum distance less than a specified minimum spacing, connecting at least a portion of nearest ends of pairs of elongate mandrels, each mandrel of a pair from a different active region. The method further includes generating a second layout including a plurality of elongate mandrels in the plurality of active regions, and connective elements between active regions of at least one adjacent pair of active regions.

Abstract: Described herein are methods for matching the characteristics of a lithographic projection apparatus to a reference lithographic projection apparatus, where the matching includes optimizing projection optics characteristics. The projection optics can be used to shape wavefront in the lithographic projection apparatus. According to the embodiments herein, the methods can be accelerated by using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).

Abstract: A design layout includes a conductive line level, at least one underlying conductive line level, and a via design level for vertically interconnecting structures in the conductive line level and the at least one underlying conductive line level. Stitch shapes are identified in the conductive line level. Test shapes are generated to determine whether vias formed in the area of the stitch shapes can extend to the at least one underlying conductive line level without contacting preexisting design shapes in the at least one underlying conductive line level structure and whether a new design shape can be inserted into the at least one underlying conductive line level with electrical isolation. As many new design shapes are inserted as possible to prevent extension of collateral via structures below the top surface of underlying metal line structures in a physical metal interconnect structure implementing the design layout.

Abstract: Disclosed is a method, system, and computer program product for performing predictions for an electronic design. Embodiments of the invention allow the ability to efficiently update the model predictions at a later time once previously incomplete blocks are completed. Predictions can be efficiently updated after block designs are updated (e.g. after correcting problems detected from model predictions).

Abstract: Methods and systems for generating a regularized integrated circuit layout are disclosed. Pattern replacement of various portions of wiring within an integrated circuit layout with a common pattern is performed in order to generate a regularized layout. The regularized layout is then subjected to additional mask data preparation processing, such as optical proximity correction.

Abstract: A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

Abstract: An initial layout of at least a portion of a given layer of an integrated circuit design is decomposed into multiple sub-layouts by splitting each of a plurality of shapes of the initial layout into multiple segments, constructing a constraint graph to represent relationships between the segments, reducing the constraint graph to a stitch graph, determining at least one cut line of the stitch graph, and generating a decomposed layout based on the determined cut line. The decomposed layout in an illustrative embodiment includes first and second sub-layouts comprising respective disjoint subsets of the segments, with each of the sub-layouts of the decomposed layout being associated with a different pattern mask of a double patterning lithography process. The layout decomposition process advantageously minimizes the number of stitches between the sub-layouts without introducing excessive computational complexity.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. The initial design layout comprises a first pattern, such as a mandrel pattern, and a second pattern, such as a passive fill pattern. An initial cut pattern is generated for the initial design layout. Responsive to identifying a design rule violation associated with the initial cut pattern, the initial design layout is modified to generate a modified initial design layout. An updated cut pattern, not resulting in the design rule violation, is generated based upon the modified initial design layout. The updated cut pattern is applied to the modified initial design layout to generate a final design layout. The final design layout can be verified as self-aligned multiple patterning (SAMP) compliant.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.

Abstract: A method of determining calibration test patterns to be utilized to calibrate a model for simulating the imaging performance of an optical imaging system. The method includes the steps of defining a model equation representing the imaging performance of the optical imaging system; transforming the model equation into a plurality of discrete functions; identifying a calibration pattern for each of the plurality of discrete functions, where each calibration pattern corresponding to one of the plurality of discrete functions being operative for manipulating the one of the plurality of discrete functions during a calibration process; and storing the calibration test patterns identified as corresponding to the plurality of discrete functions. The calibration test patterns are then utilized to calibrate the model for simulating the imaging performance of an optical imaging system.

Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract: An integrated circuit includes a gate array layer having a two-dimensional array of logic gates, each logic gate including multiple transistors. At least one upper template-based metal layer is coupled to the gate array layer and is configured to define at least one of a power distribution network, a clock network and a global signal network. A configuration of traces of the upper template-based metal layer is at least mainly predetermined prior to design of the integrated circuit.

Abstract: In a method and apparatus for quantitatively evaluating two-dimensional patterns, a reference coordinate system is set in order to convert pattern edge information (one-dimensional data) acquired by measurement using an existing critical dimension machine into coordinate data. Thus, a pattern is converted into coordinate information. Next, a function formula is determined from this coordinate information by approximate calculation and a pattern is represented by the mathematical expression y=f(x). Integrating y=f(x) in the reference coordinate used when calculating the coordinate data gives the area of the pattern, whereby it is possible to convert the coordinate data to two-dimensional data.

Abstract: Some embodiments relate to a system that pre-colors word lines and control lines within a memory cell to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The system has a memory element that stores a graphical IC layout with a memory circuit having layout features including a plurality of word lines and a plurality of Y-control lines. A pre-coloring element pre-colors one or more of the plurality of word lines and Y-control lines, to indicate that pre-colored word lines and Y-control lines are to be formed on a same mask of a multiple mask set used for a multiple patterning lithography process. A decomposition element assigns different colors to uncolored layout features of the memory circuit, to indicate that different colored memory features are to be formed on different masks of the multiple mask set.

Abstract: A method for describing an array of elements includes the steps of providing an array description system that includes a library of possible alternative designations; and describing the array of elements using at least one of the alternative designations. The library of possible alternative designations includes one or more of the following (i) a line designation, (ii) a column designation, (iii) a square designation, (iv) a rectangle designation, (v) a cross designation, (vi) a diagonal designation, (vii) a complex designation, (viii) a mosaic designation, (ix) an overlap designation, (x) a power designation, (xi) a border designation, (xii) a corner flip designation, (xiii) a mirror image designation, (xiv) a repeat designation, and (xv) a glide designation.

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract: An inspection method for a photo-mask in a semiconductor process is provided. First, a first photo-mask with a first wafer anchor point (1st wafer FAM) is provided. Then, Dmax and Dmin are calculated according to the 1st wafer FAM. A second photo-mask and a second mask anchor point (2nd mask FAM) of the second photo-mask are provided. A CD average, and a CD range of the second photo-mask are measured. Finally, the second photo-mask is inspected by using equation A and/or equation B: CD average?2nd mask FAM<Dmax?CD range/2??(equation A) 2nd mask FAM?CD average<Dmin?CD range/2??(equation B).

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: Disclosed are a method, apparatus, and program product for routing an electronic design using double patterning that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patterning, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning.

Abstract: A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function.

Abstract: A method of optical proximity correction (OPC) includes the following steps. First, a layout pattern is provided to a computer system. Subsequently, the layout pattern is classified into a first sub-layout pattern and a second sub-layout pattern. Then, an OPC calculation based on a first OPC model is performed on the first sub-layout pattern so as to form a corrected first sub-layout pattern and an OPC calculation based on a second OPC model is performed on the second sub-layout pattern so as to form a corrected second sub-layout pattern. Afterward, the corrected first sub-layout pattern and the corrected second sub-layout pattern are output from the computer system into a photomask.

Abstract: Defective artifact removal is described in photolithography masks corrected for optical proximity. In one example a method is described in which partitions are identified in a mask design for independent optimization. The partitions are grouped and ordering into stages. The first stage is processed. Geometries are extracted from the periphery of the first stage partitions. The extracted geometries are added to the peripheries of second stage partitions. Then the second stage partitions are processed.