Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: Systems for integrated electronic and photonic design include a graphical user interface (GUI) configured to lay out electronic and photonic design components in a design environment; a design rule checking (DRC) module configured to check design rules for electronic and photonic components according to manufacturing requirements; and a processor configured to adjust photonic components according to photonic design requirements and to reconcile conflicts between electronic and photonic components.

Abstract: Embodiments of the present disclosure disclose a method of forming a new integrated circuit design on a semiconductor wafer using a photolithography tool. The method includes selecting a previously processed wafer having a past integrated circuit design different than the new integrated circuit design, selecting a plurality of critical dimension (CD) data points extracted from the previously processed wafer after the previously processed wafer was etched, and creating a field layout and associated baseline exposure dose map for the new integrated circuit design. The method also includes refining each field in the baseline exposure dose map based on a difference between an average CD for the previously processed wafer and an average CD for each field in the field layout and controlling the exposure of the photolithography tool according to the refined baseline exposure dose map to form the new integrated circuit design on the semiconductor wafer.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing an integrated circuit layout plan, the integrated circuit layout plan containing a plurality of semiconductor features. The method includes selecting a subset of the features for decomposition as part of a double patterning process. The method includes designating a relationship between at least a first feature and a second feature of the subset of the features. The relationship dictates whether the first and second features are assigned to a same photomask or separate photomasks. The designating is carried out using a pseudo feature that is part of the layout plan but does not appear on a photomask. The method may further include a double patterning conflict check process, which may include an odd-loop check process.

Abstract: Embodiments of a computer system, a process, a computer-program product (i.e., software), and a data structure or a file for use with the computer system are described. These embodiments may be used to determine or generate source patterns that define illumination patterns on photo-masks during a photolithographic process. Moreover, a given source pattern may be determined concurrently with an associated mask pattern (to which a given photo-mask corresponds) or sequentially (i.e., either the given source pattern may be determined before the associated mask pattern or vice versa.). During the determining, the given source pattern may be represented using one or more level-set functions. Additionally, the source pattern may be determined using an Inverse Lithography (ILT) calculation.

Abstract: A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is disposed around the first main feature. A model-based feature is generated around the first main feature. An overlap Boolean feature is extracted from the rule-based features, wherein the overlap Boolean feature overlaps with the model-based feature in an overlap ratio up to a target value. The overlap Boolean feature serves as an assistant feature, and the assistant feature and the first main feature constitute a transfer feature.

Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

Abstract: A method for enabling functionality in circuit designs utilizing colorless DPT M1 route placement that maintains high routing efficiency and guarantees M1 decomposability of a target pattern and the resulting circuit are disclosed. Embodiments include: determining a boundary abutting first and second cells in an IC; determining a side of a first edge pin in the first cell facing a side of a second edge pin in the second cell; determining a first vertical segment of at least a portion of the side of the first edge pin and a second vertical segment of at least a portion of the side of the second edge pin; designating an area between the first vertical segment and the boundary as a first portion of a routing zone; and designating an area between the second vertical segment and the boundary as a second portion of the routing zone.

Abstract: The present invention relates to semiconductor inspection and provides a technology capable of efficiently detecting a systematic defect. In the present system, with regard to the process (S7, S8) of matching hot spot (HS) points that can be simulated in advance and defect points obtained as a result of a visual inspection each other and the unmatched defect points, a process (S6, S9) of classifying the defect points into groups based on similarity of pattern layout at the defect points to determine the defects belonging to a pattern layout where defects frequently occur, thereby reliably detecting the systematic defect. Also, with a process (S11) of acquiring an uneven distribution in a defect occurrence distribution on a wafer, the systematic defect occurring due to topography of the wafer can also be detected.

Abstract: A method of forming a photolithography mask including forming a first linear non-dense feature on the mask and forming a plurality of parallel linear assist features disposed substantially perpendicular to the at least one linear non-dense design feature. In an embodiment, the photolithography mask further includes a first transverse linear assist feature disposed substantially transverse to the plurality of parallel linear assist features.

Abstract: During a calculation technique, a modification to a reflective photo-mask is calculated. In particular, using information specifying a defect associated with a location on a top surface of the reflective photo-mask, the modification to the reflective photo-mask is calculated. For example, the calculation may involve an inverse optical calculation in which a difference between a pattern associated with the reflective photo-mask at an image plane in a photo-lithographic process and a reference pattern at the image plane in the photo-lithographic process is used to calculate the modification at an object plane in the photo-lithographic process. Note that the modification includes a material added to the top surface of the reflective photo-mask using an additive fabrication process. Moreover, the modification is proximate to the location.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: Disclosed is a system, method, and computer-readable medium for designing a circuit and/or IC chip to be provided using an optical shrink technology node. Initial design data may be provided in a first technology node and through the use of embedding scaling factors in one or more EDA tools of the design flow, a design (e.g., mask data) can be generated for the circuit in an optical shrink technology node. Examples of EDA tools in which embedded scaling factors may be provided are simulation models and extraction tools including LPE decks and RC extraction technology files.

Abstract: The present invention aims at proposing a library creation method and a pattern shape estimation method in which it is possible, when estimating a shape based on comparison between an actual waveform and a library, to appropriately estimate the shape. As an illustrative embodiment to achieve the object, there are proposed a method of selecting a pattern by referring to a library, a method of creating a library by use of pattern cross-sectional shapes calculated through an exposure process simulation in advance, and a method for selecting a pattern shape stored in the library.

Abstract: In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed.

Abstract: Some embodiments relate to a method for pre-coloring data within an integrated chip layout to avoid overlay errors that result from mask misalignment during multiple patterning lithography. The method may be performed by generating a graphical IC layout file containing an integrated chip layout having a plurality of IC shapes. The IC shapes within the graphical IC layout file are assigned a color during decomposition. The IC shapes are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. During mask building data associated with IC shapes that have been pre-colored is automatically sent to a same mask, regardless of the colors that are assigned to the shapes. Therefore, the pre-colored shapes are not assigned to a masked based upon a decomposition, but rather based upon the pre-coloring. By assigning IC shapes to a same mask through pre-coloring, overlay errors can be reduced.

Abstract: A method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. Designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern. Generating the second, updated DSA directing pattern includes linearizing a self-consistent field theory equation.

Abstract: A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.

Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.

Abstract: In an exemplary embodiment, a method of fabricating an integrated circuit includes designing an optical photomask for forming a pre-pattern opening in a photoresist layer on a semiconductor substrate, wherein the photoresist layer and the pre-pattern opening are coated with a self-assembly material that undergoes directed self-assembly (DSA) to form a DSA pattern. The step of designing the optical photomask includes using a computing system, inputting a DSA target pattern, and using the computing system, applying a DSA model to the DSA target pattern to generate a first DSA directing pattern. Further, the step of designing the optical photomask includes using the computing system, calculating a residual between the DSA target pattern and the DSA directing pattern, and using the computing system, applying the DSA model to the first DSA directing pattern and the residual to generate a second, updated DSA directing pattern.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A method for preparing a pattern to be printed on a plate or mask by electron beam lithography comprising the following steps: modelling of the pattern by breaking down this pattern into a set of elementary geometric shapes intended to be printed individually in order to reproduce said pattern and, for each elementary geometric shape of the model; determination of an electrical charge dose to be applied to the electron beam during the individual printing of the elementary shape, this dose being chosen from a discrete set of doses including several non-zero predetermined doses recorded in memory. The set of elementary geometric shapes is a bidimensional paving of identical elementary geometric shapes covering the pattern to be printed. In addition, when the doses to be applied to the elementary geometric shapes are determined, a discretisation error correction is made by dithering.

Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Abstract: Systems and methods for generating an image are provided. These systems and methods include generating multiple light beams from a light source by controlling at least one parameter of the light source to be different among each of the multiple light beams. The systems and methods further include forming multiple light patterns of circuit structures that are separated in frequency by directing each of the light beams at a mask of circuit features. The systems and methods, when used in lithography for example, further include directing each of the light patterns toward a silicon substrate. The silicon substrate includes a silicon wafer having a surface at least partially covered with at least one of a photoresist material and a reversible contrast enhancement material (R-CEM).

Abstract: In a multiple patterning techniques, where two or more exposures are used to form a single layer of a device, the splitting of features in a single layer between the multiple exposures is carried out additionally with reference to features of another associated layer and the splitting of that layer into two or more sets of features for separate exposure. The multiple exposure process can be a process involving repeated litho-etch steps desirably, the alignment scheme utilized during exposure of the split layers is optimized with reference to the splitting approach.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: A design layout including shapes of target areas for forming semiconductor fins employing directed self-assembly can be decomposed into guiding patterns and cut patterns. The lengthwise edges of the shapes of target areas are adjusted. Widthwise edges of the adjusted shapes are extended outward to generate diffusion shapes. Guiding pattern shapes are then generated employing the diffusion shapes. Taper edges are adjusted based on process bias of a photoresist material to be subsequently employed. Optionally, a portion of a guiding pattern shape between diffusion shapes may be removed as a connection shape. The guiding pattern shapes can define at least one guiding pattern mask for lithographic pattern of guiding pattern shapes, and cut shapes can be derived from the diffusion shapes and the guiding pattern shapes. The guiding pattern shapes and the cut shapes may be adjusted to accommodate effects at device cell edges and at device macro edges.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between two adjacent sets. In such embodiment, the sets of parallel line features along with the connection features are formed using two lithographic masks, without a need for an additional mask layer to form the connection features. In other embodiments, other features in addition to the connection features can be added in the same mask layer.

Abstract: A method for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set includes first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method includes a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region.

Abstract: A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.

Abstract: Improved masks for double patterning lithography are described. In one example, conflict spaces between features of a target design are identified. The conflict spaces are represented as nodes of a graph. Connections are inserted between nodes based on a local search. The connections are cut to determine double patterning mask assignment. The connections are extended to form a checkerboard that is then overlayed on the target mask design to split the features of the target mask design for double patterning.

Abstract: Computer-implemented methods are disclosed for providing an elastic modulus map of an integrated circuit (IC) chip of a chip/device package, for identifying a probable failure site of the chip/device package from the elastic modulus map of the IC chip, for modifying a connector footprint of the chip/device package based on identifying a probable failure site from the elastic modulus map of the IC chip, and for modifying the IC chip based on identifying a probable failure from the elastic modulus map of the IC chip. Each layer of the IC chip may be mapped, and each grid shape of the mapped layers may comprise a metal area and a dielectric area. Grid shapes from each layer of the IC are vertically aligned to provide a combined spring constant for each grid shape, which are then mapped onto the elastic modulus map to identify possible failure sites in the chip/device package.

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

Abstract: A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

Abstract: Various embodiments provide a constraint-driven environment to interactively determine coloring of layout components when the layout components are being modified or created and to provide feedback with visual aids to users in nearly real-time. Layout components are thus appropriately assigned to respective mask designs upon their creation. Various embodiments check or verify various constraints during creation or modification of layout components, and the layout thus remains design rule clean as constructed. Some embodiments use data structure(s) including information associated with mask identifications of objects of a cluster to change some mask identifications without considering any of the constraints governing these mask identifications. Some embodiments further determine the mask identification for an object based at least in part on whether object splitting and stitching is permitted.

Abstract: A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number of distinct features in the image data with the simulated defects are determined and the differences between the two obtained. The difference number is used as an indication of shorting potential or probability that shorts in the wiring may occur in the electrical wiring design. The simulating of the defects in the image data may be repeated and the difference value from each simulation or run may be used to obtain a statistical average or representative shorting potential or probability for the design.

Abstract: The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width.

Abstract: A method of optimizing a die size in a method of manufacturing devices using a lithographic apparatus, wherein the lithographic apparatus is arranged to expose an image field of variable size in a single exposure step, the image field having a certain maximum size, the method comprising: receiving a desired area for the die; and calculating a target aspect ratio for the die, wherein the target aspect ratio is determined so as to maximize the number of good dies that can be imaged per hour using the lithographic apparatus. Desirably, calculating a target aspect ratio comprises finding a first target aspect ratio that maximizes a figure of merit MF, where MF is the ratio of the number of dies exposed in each image field divided by the number of exposures on each substrate.

Abstract: There is provided a method comprising receiving data corresponding to a layout design for a plurality of input mask layers and generating a layout design for at least one generated mask layer. The relationship between a first geometric element in a first layout pattern comprising one or more of the generated mask layers and a second geometric element in a second layout pattern is then determined and verified to check if they comply with predetermined rules. If the relationship does not conform with the predetermined rules the design of at least one of the generated mask layers associated with the first or second layout pattern is modified.

Abstract: Manufacturing circuits with reference plane voids over vias with a strip segment interconnect permits routing critical signal paths over vias, while increasing via insertion capacitance only slightly. The transmission line reference plane defines voids above (or below) signal-bearing plated-through holes (PTHs) that pass through a rigid substrate core, so that the signals are not degraded by an impedance mismatch that would otherwise be caused by shunt capacitance from the top (or bottom) of the signal-bearing PTHs to the transmission line reference plane. In order to provide increased routing density, signal paths are routed over the voids, but disruption of the signal paths by the voids is prevented by including a conductive strip through the voids that reduces the coupling to the signal-bearing PTHs and maintains the impedance of the signal path conductor.

Abstract: A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Abstract: A method of decomposing a target pattern having features to be imaged on a substrate so as to allow said features to be imaged in a multi-exposure process. The method includes the steps of: segmenting a plurality of the features into a plurality of polygons; determining the image log slope (ILS) value for each of the plurality of polygons; determining the polygon having the minimum ILS value, and defining a mask containing the polygon; convolving the defined mask with an eigen function of a transmission cross coefficient so as to generate an interference map, where the transmission cross coefficient defines the illumination system to be utilized to image the target pattern; and, assigning a phase to the polygon based on the value of the interference map at a location corresponding to the polygon, where the phase defines which exposure in said multi-exposure process the polygon is assigned.

Abstract: There is provided a computer-implemented method of creating a recipe for a manufacturing tool and a system thereof. The method comprises: upon obtaining data characterizing periodical sub-arrays in one or more dies, generating candidate stitches; identifying one or more candidate stitches characterized by periodicity characteristics satisfying, at least, a periodicity criterion, thereby identifying periodical stitches among the candidate stitches; and aggregating the identified periodical stitches and the periodical sub-arrays into periodical arrays, said periodical arrays to be used for automated recipe creation.

Abstract: A method for manufacturing a semiconductor device is disclosed, wherein during the physical design process, a curvilinear path is designed to represent an interconnecting wire on the fabricated semiconductor device. A method for fracturing or mask data preparation (MDP) is also disclosed in which a manhattan path which is part of the physical design of an integrated circuit is modified to create a curvilinear pattern, and where a set of charged particle beam shots is generated, where the set of shots is capable of forming the curvilinear pattern on a resist-coated surface.

Abstract: A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.

Abstract: Obtaining a function by convoluting a function representing a light intensity distribution formed by an illumination apparatus on a pupil plane of a projection optical system and a pupil function of the projection optical system. Calculating a Fourier transformed function by Fourier transforming the product of the obtained function and a diffracted light distribution from a pattern on an object plane of the projection optical system. Producing data of the pattern of the mask based on the Fourier transformed function.

Abstract: A beam writing apparatus includes a unit to obtain a specific value by calculating an integer by dividing a total irradiation time by a multiplied value of a region number and a repeating times number, and by multiplying the integer by the repeating times number, to add the repeating times number to the specific value when a region is in the multiple writing unit regions and is not a specific region and when a region number of the multiple writing unit region, defined excluding the specific region, is below or equal to a value obtained by dividing the total irradiation time by the multiplied value of the region number and the repeating times number, to obtain a first remainder, and dividing the first remainder by the repeating times number, and to treat an added value of the repeating times number and the specific value, as a total irradiation time.

Abstract: A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a pattern, assigning target points to segments of the pattern, and producing first a simulated contour of the pattern based on the assigned target points. The method further includes reassigning the target points to the segments of the pattern based on the first simulated contour of the pattern; producing a second simulated contour of the pattern based on the reassigned target points, and after producing the second simulated contour of the pattern, producing a modified IC design layout.