Abstract: The present invention provides a computer-readable recording medium recording a program for causing a computer to execute a method of determining a pattern of a mask and an effective light source distribution with which the mask is illuminated, both of which are used for an exposure apparatus including an illumination optical system which illuminates a mask with light from a light source and a projection optical system which projects a pattern of the mask onto a substrate.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature.

Abstract: Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

Abstract: A method and system check a double patterning layout in abutting cells and switch the pattern in one of the cells if the edge patterns in each cell are in the same mask. The method includes receiving layout data having patterns in abutting cells, changing a designated mask in one cell if the edge patterns are in the same mask, adjusting cell edge spacings at a shared edge according to a minimum spacing rule and a G1-rule, and outputting a presentation of the layout data.

Abstract: A method comprises: selecting a circuit pattern or network of circuit patterns in a layout of an integrated circuit (IC) to be fabricating using double patterning technology (DPT). Circuit patterns near the selected circuit pattern or network are grouped into one or more groups. For each group, a respective expected resistance-capacitance (RC) extraction error cost is calculated, which is associated with a mask alignment error, for two different sets of mask assignments. The circuit patterns in the one or more groups are assigned to be patterned by respective photomasks, so as to minimize a total of the expected RC extraction error costs.

Abstract: Disclosed herein are correcting methods and devices for lithography hotspots of the post-routing layout, used for correcting lithography hotspots detected in the post-routing layout. At least one two-dimensional pattern of changeable size or position of the number of hotspots in the local area is selected and adjusted, so that the simulation value of the aerial image intensity of various local areas is optimized. The simulation value of the aerial image intensity is derived through calculation with respect to a set of optical simulation model cells that can be determined by the numerical value of distribution of the aerial image intensity of a number of basic two-dimensional patterns. After adjustment, the aerial image intensity of the local area can be calculated with respect to a set of optical simulation model cells, and a number of cells in the simulation model cells are selected to synthesize the two-dimensional pattern after the change.

Abstract: The present invention relates to customizing individual workpieces, such as chip, flat panels or other electronic devices produced on substrates, by direct writing a custom pattern. Customization can be per device, per substrate, per batch or at some other small volume that makes it impractical to use a custom mask or mask set. In particular, it relates to customizing a latent image formed in a patterning sensitive layer over a substrate, merging standard and custom pattern data to form a custom pattern used to produce the customized latent image. A wide variety of substrates can benefit from the technology disclosed.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Abstract: An image of a mask pattern is overlaid on an image of a mask blank annotated with the center location and dimensions of each measured mask defect. Design clips centered at the measured defects are generated with lateral dimensions less than allowable movement of the mask pattern over the mask blank. Each design clip is converted into a binary image including pixels corresponding to defect-activating regions and pixels corresponding to defect-hiding regions. Each pixel region representing the defect-activating region is expanded by laterally biasing peripheries by one half of the lateral extent of the defect located within the corresponding design clip. Biased design clips are logically compiled pixel by pixel to determine an optimal pattern shift vector representing the amount of pattern shift.

Abstract: A utility includes a design-for-manufacturing (DFM) checker configured to check layout patterns of an integrated circuit, and a layout change instruction generator configured to generate a layout change instruction based on a result generated by the DFM checker. The DFM checker and the layout change instruction generator are embodied on a non-transitory storage media. The layout change instruction specifies an identifier of a layout pattern among the layout patterns, and a respective layout change to be performed on the layout pattern.

Abstract: Apparatus includes a machine readable storage medium for storing a template library having at least one template. The template is to include a first layout representation of at least one pattern to be formed by multi-patterning a single layer of an IC. The pattern has a plurality of portions to be formed using a plurality of respectively different photomasks. The first layout representation includes data identifying on which photomask each portion is to be located. An electronic design automation (EDA) tool includes a processor configured to receive a hardware description language representation of at least a part of a circuit and generate a second layout representation of the part of the circuit having a plurality of polygons. The EDA tool has a matching module that identifies and outputs an indication of whether one or more of the plurality of portions matches a subset of the plurality of polygons.

Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Abstract: A hierarchical schematic design editor displays mask layers for each shape as mask specific colors and alerts a user to mask layer conflicts during the design and editing process. According to an embodiment, mask colors may be assigned at the time the shapes or geometries and cells are placed in a circuit design layout, or when a mask layer condition indicating that two or more shapes should be set to different mask layers is detected. In an embodiment, if the distance between two shapes is less than a predetermined threshold, those shapes may cause a mask layer condition. Shapes may be grouped to facilitate mask layer condition detection and mask layer assignment.

Abstract: The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer.

Abstract: A method of performing initial optical proximity correction (OPC) with a calibrated lithography simulation model. The method includes providing a photomask having an integrated circuit (IC) pattern formed thereon, acquiring an aerial image of the IC pattern formed on the photomask using an optical microscope, and calibrating an optical component of the lithography simulation model based on the aerial image. The method also includes exposing and developing a photoresist layer on a semiconductor wafer using the photomask to form a post-development pattern on the photoresist layer, acquiring a post-development image of the post-development pattern on the photoresist layer, and calibrating the photoresist component of the lithography simulation model based on the post-development image.

Abstract: A method of electron-beam lithography is provided, notably for technologies of critical dimension of the order of 22 nm. In such methods applied notably to networks of lines, the methods of the prior art do not offer precise and efficient correction of the shortenings of line ends. The method provided solves this problem by carrying out the insertion of contrast intensification structures of types which are optimized for the structure of the lines to be corrected. The method allows the semi-automatic or automatic calculation of the dimensions and locations of said structures. Advantageously, these calculations may be modeled to produce a target design, derived from libraries of components. They may be supplemented with a joint optimization of the size of the etchings and of the radiated doses, as a function of the process energy latitude.

Abstract: A parameter correction method includes: obtaining, from a variability-aware simulation, a simulation result value of a predetermined product performance for a reference candidate value set concerning statistics of predetermined product characteristics; calculating a likelihood by substituting the reference candidate value set, the obtained simulation result value, statistics of measurement values of the predetermined product characteristics and a measurement value of the predetermined product performance into a likelihood function that is defined from a probability density function for the statistics of the predetermined product characteristics and a probability density function for the predetermined product performance, and is a function to calculate a combined likelihood of the statistics of the predetermined product characteristics and the predetermined product performance; and searching for a reference candidate value set in case where the calculated likelihood becomes maximum, by carrying out the obtaini

Abstract: Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.

Abstract: A method for separating features in a target layout into different mask layouts for use in a photolithographic process. Features of a target layer are searched for features having a predefined shape. In one embodiment, portions of the feature having the predefined shape divided into two or more sub-features and at least one sub-feature are not considered when separating the features into two or more mask layouts. In another embodiment, features having a predefined shape are cut to form two or more sub-features and all features and sub-features are considered when separating the features of the target layout into the two or more mask layouts.

Abstract: A potential-supply connection interconnect is provided in a multilayer interconnect layer. The potential supply connection interconnect overlaps some cell of I/O cells in the outer peripheral cell column and some cell of I/O cells in the inner peripheral cell column in a plan view. The potential-supply connection interconnect connects a power potential supply interconnect located below the outer peripheral cell column to a power potential supply interconnect located below the inner peripheral cell column and also connects a ground potential supply interconnect located below the outer peripheral cell column to a ground potential supply interconnect located below the inner peripheral cell column.

Abstract: Embodiments of the invention include a method for categorizing and displaying design rule errors. The method may include receiving, from a design rule checker, more than one violation of a design rule within a design layout. The method may also include determining distinct categories of the design rule violations by comparing parameters associated with the design rule violations.

Abstract: Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

Abstract: The present disclosure relates to a method and apparatus to create a physical layout for electron-beam lithography, comprising defining a layout grid for a physical design, the layout grid further comprising vertical grid lines which coincide with stitching lines resulting from partitioning the physical design into a plurality of subfields. The physical design is assembled in accordance with design restrictions regarding interaction between design shapes and the layout grid. In some embodiments, the design restrictions are realized though layout restrictions. In some embodiments, the design restrictions are realized by shifting standard cells to minimize design shape interaction with the layout grid in a post-layout step. In some embodiments, the design restrictions are realized by exchanging positions between a plurality of standard cells for an exchange permutation which minimizes the number of interactions in a post-layout step.

Abstract: A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.

Abstract: A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set.

Abstract: A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

Abstract: In an electronic design automation technique for optical proximity correction, a mask is represented by a function with an exact analytical form over a mask region. Using the physics of optical projection, a solution based on a spatial frequency analysis is determined. Spatial frequencies above a cutoff are determined by the optical system do not contribute to the projected image. Spatial frequencies below this cutoff affect the print (and the mask), while those above the cutoff only affect the mask. Frequency components in the function below this cutoff frequency may be removed, which will help to reduce computational complexity.

Abstract: Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

Abstract: Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

Abstract: Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.

Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Abstract: An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Abstract: A method of performing double patterning (DPT) conflict repairs is described. In this method, even cycles adjacent to odd cycles in a layout can be identified (also called adjacent even/odd cycles herein). The identifying can include forming graph constructs of the layout. Route guidances for break-link operations and split-node operations can be prioritized for the adjacent even/odd cycles. A list including the route guidances for the break-link operations and the split-node operations can be generated. The list can be ordered based on the prioritizing.

Abstract: A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts.

Abstract: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.

Abstract: A reticle for lens heating mitigation includes a substrate, a target pattern and a redistributive pattern. The substrate includes a live pattern region and the target pattern is disposed within the live pattern region for constructing the target pattern onto a wafer. The redistributive pattern is also disposed within the live pattern region for redistributing energy onto a lens without being printed onto the wafer and without correcting said target pattern to be printed onto the wafer.

Abstract: A method and an apparatus for determining the position of a structure on a mask for microlithography, in which the position is determined by comparing an aerial image, measured by a recording device, of a portion of the mask with an aerial image determined by simulation. The position determination includes carrying out a plurality of such comparisons which differ from one another with regard to the input parameters of the simulation.

Abstract: According to one embodiment, a method for generating mask data is configured to form a circuit pattern on a substrate using a directed self-assembly material. The method includes extracting a first region, setting a second region and setting a third region. The first region does not existing in the circuit pattern and existing in an initial pattern. The initial pattern includes a plurality of interconnect patterns extending in a first direction. The second region is formed by elongating the first region in a second direction intersecting the first direction. The second region straddles the first region in the second direction. The third region includes at least one of the second regions. The directed self-assembly material is disposed in the third region.

Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.

Abstract: Some embodiments of the invention provide a method for verifying an integrated circuit (IC) design. The method receives a process description file that specifies a process technology for building the IC. The process description file describes a particular device type in which a first conductor overlaps a second conductor by recessing from the second conductor in one or more cut-outs. Based on the process description file, the method finds a section of the IC design that matches the particular device type and uses the description of the particular device type to compute a capacitance value and a resistance value for the section of the IC design.

Abstract: A semiconductor apparatus and a design method for the semiconductor apparatus allow debugging or repairs by using a spare cell. The semiconductor apparatus includes a plurality of metal layers. At least one repair block performs a predetermined function. A spare block is capable of substituting for a function of the repair block. And at least one of the plurality of metal layers is predetermined to be a repair layer for error revision. At least one pin of the repair block is connected to the repair layer through a first pin extension, and at least one pin of the spare block is capable of extending to the repair layer. When the repair block is to be repaired, the pin extension of the repair layer and the repair block is disconnected, and at least one pin of the spare block is connected to the repair layer through a second pin extension.

Abstract: A method, system, and computer program product for improving printability of a design of an integrated circuit (IC) using pitch-aware coloring for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A first shape is identified in a layout of the IC corresponding to the design as being apart by a first distance from a second shape. The first distance is a forbidden distance and at least equal to a minimum distance requirement of a lithography system. A determination is made that the first shape and the second shape are colored using a first color. The first shape is changed to a second color, such that even though the first distance is at least equal to the minimum distance requirement of the lithography system, the first and the second shapes are placed on different masks to print the design, thereby improving the printability of the design.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: In the embodiments, a full resistive network is used to determine resistance contributions to the total parasitic resistance of each source/drain region of a multi-fin multi-gate field effect transistor (MUGFET). These resistance contributions include: a first resistance contribution of end portions of the fins, which are connected in pseudo-parallel by a local interconnect; second resistance contributions of segments of the local interconnect, which are connected in pseudo-series; and any other resistance contributions of any other resistive elements between the end portions of the fins and a single resistive element through which all the diffusion region current flows. The multi-fin MUGFET is then represented in a netlist as a simple field effect transistor with the total parasitic resistances represented as single resistive elements connected to the source/drain nodes of that field effect transistor. This simplified netlist is then used to simulate performance of the multi-fin MUGFET.

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.