Abstract: A temporal profiling framework useful for dynamic optimization with hot data stream prefetching provides profiling of longer bursts and lower overhead. For profiling longer bursts, the framework employs a profiling phase counter, as well as a checking phase counter, to control transitions to and from instrumented code for sampling bursts of a program execution trace. The temporal profiling framework further intelligently eliminates some checks at procedure entries and loop back-edges, while still avoiding unbounded execution without executing checks for transition to and from instrumented code. Fast hot data stream detection analyzes a grammar of a profiled data reference sequence, calculating a heat metric for recurring subsequences based on length and number of unique occurrences outside of other hot data streams in the sequence with sufficiently low-overhead to permit use in a dynamic optimization framework.

Abstract: A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.

Abstract: A method for analyzing and optimizing programs that operate on a data structure where the state of the data structure must be valid at certain program points. The program is represented as a control-flow graph. The method decomposes the state of the data structure into components, and applies partial redundancy elimination to place instructions that set the state of the data structure, with a variation that permits speculative placement. Application extends to manipulating a stack that keeps track of what to do should an exception arise during execution. In this context, a control-flow representation of contingencies is converted into placement of instructions that manipulate the stack.

Abstract: An optimization apparatus (compiler program, method and recording medium) for changing the order of execution of instructions in a program to be optimized includes an exception occasion instruction detection section which detects a first instruction having a possibility to cause an exception, an assurance instruction detection section which detects a second instruction executed prior to the first instruction, the second instruction assuring that no exception of the first instruction occurs, and an execution order control section which changes the position of the first instruction in execution order so that the first instruction is executed before a conditional branch instruction for selectively executing the first instruction and after the second instruction.

Abstract: Rapid determination of placement for code and data for optimal access of the code and data during execution of software applications. An application that is to be efficiently arranged in a software carrier medium is instrumented such that the status of whether a particular unit of code or data has been accessed during a time interval is recorded in a time-ordered bit sequence for each such unit. A sort routine is used to sort the order of time-ordered bit sequences within an array of such sequences. The sort routine invokes a comparison function that operates upon the temporal information stored in the two time-ordered bit sequences that are being compared for the routine. The order of the code and data in the software application is reordered in accordance with the results of the sort routine.

Abstract: A method and apparatus are provided for analyzing software programs. The invention combines data flow analysis and symbolic execution with a new constraint solver to create a more efficient and accurate static software analysis tool. The disclosed constraint solver combines rewrite rules with arithmetic constraint solving to provide a constraint solver that is efficient, flexible and capable of satisfactorily expressing semantics and handling arithmetic constraints. The disclosed constraint solver comprises a number of data structures to remember existing range, equivalence and inequality constraints and incrementally add new constraints. The constraint solver returns an inconsistent indication only if the range constraints, equivalence constraints, and inequality constraints are mutually inconsistent.

Abstract: Embodiments of the present invention provide a method and system for optimizing processor register allocation. Variables from an acyclic call graph having a plurality of functions may be identified and a plurality of virtual registers may be created by assigning each of the identified variables to at least one virtual register. An interference graph may be constructed based on the plurality of virtual registers and may be colored with a plurality of physical registers. If the interference graph is not colorable, then at least one virtual register may be spilled from the interference graph.

Abstract: In the context of a constraint-based or rule-based model, in which nodes are interrelated by constraints, rules, and conditions, addition of and changes to nodes need to be validated against relevant constraints. A mechanism is provided for performing such validation without loading the entire configuration, which includes a set of constraints and a set of node variables. In response to an intent to modify a node, a subset of the set of constraints is determined, which includes all constraints that restrict the intent to modify. Further, a subset of the set of node variables is determined, which includes all node variables that may have values that affect whether any of the subset of constraints is violated. A subset of node variable information is loaded into volatile memory, which includes only information about the subset of node variables, rather than information about all of the nodes of the model.

Abstract: The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW processor. The basic approach of these methods is to assign a node n of the dependence graph to the cluster to which it has the strongest affinity. A node n has the strongest affinity to the cluster containing its closest common ancestor node. Then, the mirror image node or nodes of the node n are located if they are present in the graph and are assigned to other clusters in the processor to which they have the strongest affinity.

Abstract: Interprocedural side-effect analysis is performed by constructing a fixed-point problem graph for each translation unit of a software program having a plurality of separately compilable components. The method performs analyzing each routine, of a software program having a plurality of separately compilable routines, to create a plurality of local side-effect problems for each routine; and merging the local side-effect problems to create a global side-effect problem.

Abstract: An object oriented mechanism and method allow allocating Java objects on a method's invocation stack in a partial compilation environment under certain conditions. Only the classes that are visible are taken into account when performing escape analysis in accordance with the preferred embodiments. In a first aspect of the invention, conservative assumptions are made to assure that objects are only allocated on an invocation stack when this can be proven safe by examining only those classes in the compilation unit. In a second aspect of the invention, the concept of visible classes is extended to include other classes that may be found from a user-defined classpath that matches the anticipated run-time classpath used to find classes during program execution. When stack allocation decisions for a method depends on such classes that are outside the compilation unit, two versions of run time code for that method are created.

Abstract: A system and method for executing multiple graphical programs, in which program output from each graphical program is displayed in a single graphical user interface. Program output from a first graphical program and program output from a second graphical program may be displayed in a single graphical user interface on a display. The single graphical user interface may also be used for specifying program input for the first and/or the second graphical program. Any number of graphical programs may share the single graphical user interface. In one embodiment different graphical program development environments may be used to create the separate graphical programs.

Abstract: Methods are described that enhance pointer analysis for programs. Whereas previous methods are constrained by the extremes of an inverse relationship between time and information, the present methods selectively unify information so as to allow a desired level of analytical decision within a desired duration of analysis. One aspect of the present invention includes selectively retaining information at a first order of indirection based on variables in an assignment statement while unifying information at subsequent orders of indirection. The methods are used for pointer variables, but are equally useful to function definitions, function calls, function pointers, indirect function calls, and others. The methods may be used in client analysis tools such as code browsers and slicing tools.

Abstract: An optimizing compiler and method thereof performs a sequence of optimizing changes to an intermediate language representation of a routine, and measures an execution characteristic of each optimization, such as a timing of the machine language representation performed on an architecture similar to the target machine using a user selectable initialization state. The sequence of optimizations is selected according to a criterion that includes a lexicographic search and other methods. The pre-optimized code is also broken into segments wherein discrete optimizations are performed on each segment and measured using a user provided routine. The target routine is tested with the object code in main memory if not the cache if possible and optimizations are chosen only if they improve the target subroutine according to the user defined metric. After a stopping criterion is achieved, the most optimized code is selected.

Abstract: An apparatus and method for cataloging symbolic data for use in performance analysis of computer programs is provided. The apparatus and method stores symbolic data for loaded modules during or shortly after a performance trace and utilizes the stored symbolic data when performing a performance analysis at a later time. A merged symbol file is generated for a computer program, or application, under trace. The merged symbol file contains information useful in performing symbolic resolution of address information in trace files for each instance of a module. During post processing of the trace information generated by a performance trace of a computer program, symbolic information stored in the merged symbol file is compared to the trace information stored in the trace file. The correct symbolic information in the merged symbol file for loaded modules is identified based a number of validating criteria.

Abstract: A method for dynamic recompilation of source software instructions for execution by a target processor, which considers not only the specific source instructions, but also the intent and purpose of the instructions, to translate and optimize a set of equivalent code for the target processor. The dynamic recompiler determines what the source operation code is trying to accomplish and the optimum way of doing it at the target processor, in an “interpolative” and context sensitive fashion. The source instructions are processed in blocks of varying sizes by the dynamic recompiler, which considers the instructions that come before and after a current instruction to determine the most efficient approach out of several available approaches for encoding the operation code for the target processor to perform the equivalent tasks specified by the source instructions. The dynamic compiler comprises a decoding stage, an optimization stage and an encoding stage.

Abstract: A method and system makes inlining decisions that are efficient for subprograms that have significantly varying execution times over a range of variables or execution paths. A subprogram of a computer program is identified and certain execution paths of the subprogram are selectively inlined. The subprogram may be identified based on execution characteristics of the subprogram. The selective inlining of the execution paths may be based on execution characteristics of the paths. The paths may be selectively inlined based on an inline indication associated with an execution path, where the inline indication may be an inline directive. The inline directive may be included as part of a program comment statement. A compiler makes determinations whether to inline a specific execution path of a subprogram by evaluating certain information supplied in conjunction with the path.

Abstract: A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it is possible to optimize a process for elements of the multidimensional array object are added as additional information. The flags are stored in a storage device (main memory for instance). Then, a machine code corresponding to a state of the flags is executed.

Abstract: A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (105, 110, and 115). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (120). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model (200, 300, 400).

Abstract: A system and method for detecting the mutability of fields and classes in an arbitrary program component written in an object oriented programming language is disclosed. A variable is considered to be mutable if a new value is stored into it, as well as if any of its reachable variables are mutable. The system and method uses a static analysis algorithm which can be applied to any software component rather than whole programs. The analysis classifies fields and classes as either mutable or immutable. In order to facilitate open-world analysis, the algorithm identifies situations that expose variables to potential modification by code outside the component, as well as situations where variables are modified by the analyzed code. An implementation of the analysis is presented which focuses on detecting mutability of class variables, so as to avoid isolation problems. The implementation incorporates intra- and inter-procedural data-flow analyses and is shown to be highly scalable.

Abstract: A compiler and method of compiling provide enhanced performance by utilizing a skip list data structure to store various properties of a program at points of interest in the procedure, for example, the properties of the statements in each block in the control flow graph. A special procedure is used to initialize the skip list, prior to performing data flow analysis, to ensure that the skip list structure is not used in an inefficient manner as a result of initialization. Furthermore, special procedures are used to simultaneously scan and compare two skip lists as part of solving dataflow equations.

Abstract: An apparatus, method, and program product for optimizing code that contains dynamically-allocated memory. The aliasing behavior of internal pointers of dynamically-allocated memory is used to disambiguate memory accesses and to eliminate false data dependencies. It is determined whether a dynamically-allocated array will behave like a statically-allocated array throughout the entire program execution once it has been allocated. This determination is used to improve the instruction scheduling efficiency, which yields better performance.

Abstract: A method is provided for analyzing an object oriented program that supports dynamic class loading. A set A of classes in the program is identified, wherein each class within set A is capable of, during execution of the program, causing the loading of a class outside of set A. A first set of method calls belonging to the classes in set A are identified that, during execution of the program, are capable of calling only methods belonging to a class within set A. A second set of method calls belonging to the classes in set A are identified that, during execution of the program, are capable of calling methods belonging to a class outside set A. Data that identifies the first and the second set of method calls is stored for subsequent use.

Abstract: A composite object group (COG) data structure embodied in a computer-readable medium for building a control system that has both a clock cycle and event processing is provided. An interface for passing information to and from the COG data structure is provided. One or more data flow objects are provided in the COG to accept input data and to produce output data on the clock cycle. The data flow object is connected to the interface and provides sampled-data processing for the control system. One or more state machine objects are provided in the COG; each includes a plurality of states and a plurality of transitions between the states that are each triggered by an event. The state machine object provides event-driven processing for the control system, whereby the COG data structure provides both sampled-data and event-driven processing for the control system.

Abstract: Defect detection in a software system made of multiple computer program programs is facilitated by using information about cross-program interactions and dependency relationships between programs to analyze the individual programs in such a way that the behavior of the system as a whole is accurately represented. A list of dependency relationships is read in; these dependency relationships are used to determine an order in which the programs should be analyzed. The programs are then analyzed in that order. Information from the analysis of the programs is used to inform the analysis of subsequently-analyzed programs.

Abstract: A method and system for interprocedural analysis with separate compilation is disclosed. In one embodiment, the method is applied to a software program having a plurality of separately compilable components. The method performs analyzing each component separately to create a plurality of local problems for each component and merging the local problems to create a global problem.

Abstract: A method of compiling a source program to produce hardware is provided. The method includes the steps of carrying out data flow analysis of the source program to produce a data flow representation of the source program, where the data flow representation includes a number of multipliers each arranged to accept first and second input arguments having first and second input bit widths respectively, and to produce an output having a bit width; optimizing the data flow representation so that the input and output bit widths are minimised, even if this results in them being different for some or all of the multipliers; and carrying out high level synthesis on the optimised data flow representation, including sharing functional units between the multipliers in such a way that the area of silicon required to produce the functional units is minimised, even if this results in the functional unit input and output bit widths being different.

Abstract: Methods and structures are described that enhance flow analysis for programs. Whereas previous methods are complicated by the presence of function pointers, the present methods present a framework that abstracts function pointers as if they were any other program expressions so as to allow a desired level of analytical decision within a desired duration of analysis. One aspect of the present invention includes inferring types from a program, forming a type graph from the types, and forming a flow graph from the type graph to inhibit imprecise paths so as to enhance context-sensitivity of flow analysis. The methods may be used in any analysis tools such as code browsers and slicing tools.

Abstract: Processes and associated programs are described for structuring program code, comprising the steps of: procuring a single entry point reducible control flow graph representing at least a portion of an input program code; detecting in the control flow graph cycles with single entry points and marking such cycles as loops; detecting potential conditional structures in the control flow graph; scanning the detected conditional structures in a descending depth first search sequence, marking as conditional structures those of said detected potential conditional structures wherein no path from the header node of the structure to the first node of the structure where any two paths from the header meet is crossed with a marked loop or a previously marked conditional structure, whereby loop structures and conditional structures corresponding to the marked loops and conditional structures may be introduced into a syntax tree representing the program code portion in such a way that branch statements remaining in the prog

Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.

Abstract: Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of any,unused operands, the instructions defining the unused operands are removed from execution.

Abstract: A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions.

Abstract: A method and system for anticipatory optimization of computer programs. The system generates code for a program that is specified using programming-language-defined computational constructs and user-defined, domain-specific computational constructs, the computational constructs including high-level operands that are domain-specific composites of low-level computational constructs. The system generates an abstract syntax tree (AST) representation of the program in a loop merging process. The AST has nodes representing the computational constructs of the program and abstract optimization tags for folding of the composites. A composite folding process is applied to the AST according to the optimization tags to generate optimized code for the program.

Abstract: One embodiment of the present invention provides a system that generates prefetch instructions for indexed array references. Upon receiving code to be executed on a computer system, the system analyzes the code to identify candidate references to be prefetched, wherein the candidate references can include indexed array references that access a data array through an array of indices. Next, the system inserts prefetch instructions into the code in advance of the identified candidate references. If the identified candidate references include indexed array references, this insertion process involves, inserting an index prefetch instruction into the code, which prefetches a block of indices from the array of indices. It also involves inserting data prefetch instructions into the code, which prefetch data items in the data array pointed to by the block of indices.

Abstract: An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

Abstract: A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a basic block. For each time slot, operations are scheduled in order of their lowest REP values.

Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).

Abstract: An optimizer for a data transformation system. The optimizer optimizes data flow plans that describe how data is to be transformed from the form it has in a data source to the form required in a data destination. A data flow plan is made up of a sequence of transforms, and the optimized data flow plan is equivalent to the original data flow plan but has fewer transforms. One kind of optimization is read/write optimization, in which the data flow plan is modified so that operations of the original data flow plan are performed in the data source or destination. Another is merge optimization, in which a single merge transform specifies the operations specified in a plurality of the transforms of the original data flow plan. The operations specified in the merge transform can further be performed in parallel. The optimizer additionally reorders the transforms in the original data flow plan to increase the amount of optimization.

Abstract: A data processing device, data processing method and a supply medium thereof for generating machine instructions to allow faster processing. A DAG (Directed Acyclic Graph) is generated from a substitute statement input by the syntax analyzer, and instructions then generated according to the DAG in the instruction generator, and the instruction generated in the instruction execution simulator then performed and a search made by the search section for the instructions with the smallest number of clock pulses based on the number of clock pulses required to execute the instruction.

Abstract: A method and system for collaborative profiling for continuous detection of profile phase transitions is disclosed. In one embodiment, the method, comprises using hardware and software to perform continuous edge profiling on a program; detecting profile phase transitions continuously; and optimizing the program based upon the profile phase transitions and edge profile.

Abstract: A method, apparatus and article of manufacture for performing automatic intermodule call linkage optimization. In one embodiment, the run time is optimized for an object code generated from a source code. Initially, information is extracted for each procedure call in the source code. The extracted information is used to select a call linkage for each procedure call. The call linkages are selected to minimize the run time of the object code generated from the source code. Once the object code is generated form the source code, the object code is run using the selected call linkages for each procedure call.

Abstract: A system for utilizing an object library to dynamically match the type structures of a client and a server to determine compatibility. Once compatibility has been established, the client and server may communicate through a secure connection. Information may be sent asynchronously between the client and the server, and a flow control provides a buffer at the flow origin to ensure that there is no overflow of information to the recipient of the flow.

Abstract: The present invention relates generally to a method and system for performing an investigation to determine one or more hypotheses in different contexts including criminal trials, scientific inquiry and military intelligence. More specifically, the system comprises one or more tuples to represent the knowledge of one or more objects involved in the investigation wherein the tuples are exchanged among the objects to perform the investigation.

Abstract: A method for generating trace information of an information processing device that monitors operation of a processing unit without depending on the operating frequency of the processing unit. The device includes a processing unit and an interface device. The processing unit generates operational information when branching occurs, and the interface device has a buffer circuit for receiving the operational information from the processing unit.

Abstract: A goal of the present invention is to allow programmers to build software systems without regard to a specific target hardware architecture on which the software system will be implemented. An aspect of this is a high-level, coordination-centric, design methodology that permits programmers to explicitly declare the way control and data interactions between software components are coordinated. Coordination synthesis generates selectively optimizable implementation code to implement the coordination-centric software application on a target hardware architecture, and generates appropriate coordination code to implement the coordination scheme for the software application with the target hardware architecture's supported interaction protocols.

Abstract: A method for post-link code optimization by identifying cold caller functions of a hot callee function, and percolating store and restore instructions with respect to non-volatile registers from the callee function to the caller function.

Abstract: Assigns suitable registers to a plurality of variables. A compiler converts a source program into instructions for a processor having: a simultaneously used variable acquisition section which obtains, with respect to each of a plurality of variables used in the source program, some of the other variables used simultaneously with the variable; an allocation sequence generation section which generates a plurality of allocation sequences between the plurality of variables to allocate each variable to one of the plurality of registers different from those to which some of the other variables used simultaneously with the variable are allocated; an allocation priority acquisition section which obtains allocation priorities indicating to which one of the plurality of registers each variable is allocated with priority; and a register allocation section which allocates the variables to registers in accordance with an allocation sequence selected on the basis of the allocation priorities.

Abstract: Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.

Abstract: A method for memory management in execution of a program by a computer having a memory includes identifying in the program an array of array elements. At a given point in the program, a range of the elements is determined within the array such that none of the elements in the array outside the range is alive at the point. Information regarding the determined range is passed to a memory management function, so that memory locations are associated with the array elements, responsive to the determined range.

Abstract: A method, system, and program product for implementing simulation analysis instrumentation within a hardware description language (HDL) model. In accordance with the method of the present invention, one or more source code HDL design entities that simulate circuit functionality within the HDL model are compiled into one or more corresponding design entity objects. One or more source code instrumentation modules are compiled into one or more corresponding instrumentation objects. Each of the instrumentation objects is a single irreducible intermediate object code primitive that invokes a simulation analysis function in which simulation data is processed over a simulation testcase. An object code file containing the one or more design entity objects and the one or more instrumentation objects are post-compile processed to generate an executable simulation model.