Abstract: A compiler device 10 includes: an input unit inputting a data flow graph including a set of nodes and a set of edges and information indicating a range of values that can be taken by data flowing along each edge; and a determination unit determining, from among a plurality of different types of hardware resources, a hardware resource to which a first node can be assigned based on the first node type and information indicating the range of values that can be taken by data flowing along a first edge connected to the first node. The compiler device 10 makes it possible to efficiently utilize hardware resources without losing data accuracy.

Abstract: For programming of modules which can be reprogrammed during operation and for partitioning of code sequences, a control and/or data flow graph may be extracted from a program and separated into a plurality of subgraphs, which may be distributed among the modules. The separation of the flow graph may be such that connections between different ones of the subgraphs are minimized. During execution of the program, after a first module completes execution of a first part of one of the subgraphs, the first module may be reconfigured for execution of a first part of a second subgraph, while a second module executes a second part of the first subgraph.

Abstract: A storage apparatus having a non-volatile memory and a controller is provided, wherein the non-volatile memory includes a root directory area and a data area, and a password file is stored in the root directory area. The controller identifies a user by using a password in the password file, and the user can access the data area through an encryption/decryption unit of the controller only if the user passes the identification. By using the secured storage apparatus, the risk of the password and encrypted data being cracked is reduced. Accordingly, the protection over the data stored in the storage apparatus is enhanced.

Abstract: In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algorithms, performing unimodular and echelon transformations of a selected one of the first or second transformed loops, partitioning the selected transformed loop to obtain maximum outer level parallelism (MOLP), and partitioning the selected transformed loop into multiple sub-loops. Other embodiments are described and claimed.

Abstract: The present invention is directed to a method and system for distributing software components. In accordance with a particular embodiment of the present invention, a distribution hierarchy is established. The distribution hierarchy includes nodes associated with software components. A distribution path in the distribution hierarchy may be determined. The distribution path includes one or more of the nodes that are associated with a particular software application. One or more of software components may be distributed in accordance with the determined distribution path.

Abstract: The present invention provides a computer implemented method, data processing system, and computer program product for verifying a return address. A computer stores the return address into a stack based on a function call. The computer generates a first hash based on a first stack frame and a second stack frame. The computer stores the first hash in a first canary location, wherein the first canary location is in the first stack frame. The computer executes at least one instruction of a routine referenced by the function call. The computer reads the first canary location to form a first suspect hash. The computer calculates a first verification hash based on the first stack frame and the second stack frame. The computer determines that the first verification hash matches the first suspect hash to form a first positive determination. The computer responsive to the first positive determination, the computer reads a second canary location to form a second suspect hash.

Abstract: Functionality is described for providing a compiled program that can be executed in a parallel and a distributed manner by any selected runtime environment. The functionality includes a compiler module for producing the compiled program based on a dataflow representation of a program (i.e., a dataflow-expressed program). The dataflow-expressed program, in turn, includes a plurality of tasks that are connected together in a manner specified by a graph (such as a directed acyclic graph). The compiler module also involves performing static type-checking on the dataflow-expressed program to identify the presence of any mismatch errors in the dataflow-expressed program. By virtue of this approach, the above-described functionality can identify any errors in constructing the graph prior to its instantiation and execution in a runtime environment.

Abstract: A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.

Abstract: System and method for generating a data flow diagram. A first case structure may be specified. Each case of the first case structure that includes a respective plurality of input bound data flow nodes may be partitioned into one or more data flow diagram portions. The first case structure may be replaced with a first conditional structure and one or more second conditional structures. The first conditional structure may be operable to select one or more of the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The one or more second conditional structures may be operable to select at least one output from the plurality of input bound data flow diagram portions in accordance with the conditions of the first case structure. The partitioning and replacing may be performed automatically in response to specification of the first case.

Abstract: Instruction Set Extensions (ISEs) can be used effectively to accelerate the performance of embedded processors. The critical, and difficult task of ISE selection is often performed manually by designers. A few automatic methods for ISE generation have shown good capabilities, but are still limited in the handling of memory accesses, and so they fail to directly address the memory wall problem. We present here the first ISE identification technique that can automatically identify state-holding Application-specific Functional Units (AFUs) comprehensively, thus being able to eliminate a large portion of memory traffic from cache and main memory. Our cycle-accurate results obtained by the SimpleScalar simulator show that the identified AFUs with architecturally visible storage gain significantly more than previous techniques, and achieve an average speedup of 2.8× over pure software execution.

Abstract: A method and system of detecting vulnerabilities in source code. Source code is parsed into an intermediate representation. Models (e.g., in the form of lattices) are derived for the variables in the code and for the variables and/or expressions used in conjunction with routine calls. The models are then analyzed in conjunction with pre-specified rules about the routines to determine if the routine call posses one or more of pre-selected vulnerabilities.

Abstract: The analysis of an intermediate representation of source or program code. An initial version of an initial representation of the source or program code is accessed and statically analyzed. For one or more portions of this initial version, the analysis component queries an analysis-time resolution component that provides supplemental intermediate representations corresponding to the portion. This supplemental intermediate representation provides further clarity regarding the portion, and is analyzed. If defects are found, they may be reported.

Abstract: Systems and methods are described that facilitate validating electronic document conversion chain design in real time, as a designer edits a conversion chain that converts a document collection between formats. Waypoints are inserted into the document conversion chain by associating validation specifications with selected conversion components in the chain. AS the conversion chain is executed on a document collection, the validation specification is executed on all documents in the collection when a selected conversion component is executed. Validation results are returned to indicate to the designer which documents were successfully converted by the component and which were not. The designer can then modify the conversion chain, which is re-executed, and validation results are again presented to the designer for comparison to the pre-modification validation results. The designer can then approve or reject the modification(s) depending on whether document validation is improved thereby.

Abstract: A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main entry point of the program; and recording an outgoing function call within a main function. The method also includes analyzing possible object types that may occur at any given instruction from any call path for virtual calls, wherein possible object types are determined by tracking object types as they pass through plural constructs; and calling into functions generically for handling specialized native runtime type information.

Abstract: In a system where an indirect control flow instruction requires a CPU to consult a first memory address, in addition to what is encoded in the instruction itself, for program execution, a method is provided to determine if the first memory address contains a valid or plausible value. The first memory address is compared to an expected or predicted memory address. A difference between the expected or predicted memory address and the first memory address causes an evaluation of any program code about to be executed. The evaluation of code determines whether or not a malicious attack is occurring, or being attempted, that might affect proper operation of the system or program.

Abstract: A method, an information processing system, and a computer readable medium, are used to detect atomic-set serializability violations in an execution of a program. A set of classes associated with a program to be analyzed is identified. The set of classes include a set of fields. At least one subset of fields in the set of fields in the identified classes is selected. A set of code fragments associated with an execution of the program is selected. Data accesses in the selected set of code fragments are observed. It is determined if the selected set of code fragments is serializable for each selected subset of fields.

Abstract: A method for optimizing a code section prior to performing register allocation for variables referenced in the plurality of computer instructions. The method includes performing at least one of a full prematerialization or a partial prematerialization for a variable in the plurality of computer instructions. The full prematerialization replaces the variable in every use of the variable in the plurality of computer instructions with one or more variants of the variable and replaces a definition of the variable with a nop instruction. The partial prematerialization replaces some but not all occurrences of the variable in uses of the variable in the plurality of computer instructions with one or more variants of the variable without replacing the definition of the variable with the nop instruction.

Abstract: Instruction set architecture (ISA) extension support is described for control-flow integrity (CFI) and for XFI memory protection. ISA replaces CFI guard code with single instructions. ISA support is provided for XFI in the form of bounds-check instructions. Compared to software guards, hardware support for CFI and XFI increases the efficiency and simplicity of enforcement. In addition, the semantics for CFI instructions allows more precise static control-flow graph encodings than were possible with a prior software CFI implementation.

Abstract: A system traverses a directed cyclic graph to discover a relationship between a first object and a second object, and creates an alias. The alias represents the second object. The system replaces the relationship between the first object and the second object with the created alias, and creates a reference from the first object to the alias.

Abstract: The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional unit of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle functional units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased.

Abstract: Repetitive synchronization in program code is optimized through lock coarsening that is performed subject to a number of constraints. Using a forward pass over the program code followed by a backward pass, region extent bits may be determined that identify the points in the program where object locking can be coarsened. The program code may then be modified to realize coarsened locking regions determined based on the region extent bits. Alternatively, previously determined value numbers may provide much of the information collected by the two passes. In such a case, a single pass over the program code may locate features that limit lock coarsening opportunities. A set of synchronization operations that can be removed may then be determined and used when modifying the program code to coarsen locking regions.

Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs.

Abstract: According to one embodiment, a grouping method for process units, each including basic modules and data, the process units being assigned to processors in a program for a multiprocessor system, the program including the basic modules and a parallel statement describing relationships between parallel processes for the basic modules, the method includes displaying a dataflow graph visually showing a process status of each process unit based on the parallel statement, and specifying a candidate for a connection of process units on the dataflow graph, wherein the dataflow graph displays data entries, nodes in the basic modules, and edges connecting the data entries and the nodes.

Abstract: A computer implemented method, apparatus, and computer program product for obtaining aliasing information for a target variable in a computer program. A control flow graph representing the computer program is partitioned into an taken address portion that includes all reachable nodes in which an address of the target variable is taken and an untaken address portion that includes all other reachable nodes. All references to the target variable are replaced with a temporary variable in the untaken address portion. The target variable is initialized with the value from the temporary variable at each intermediary node in a set of intermediary nodes in the taken address portion. An intermediary node is a node at which an address of a target variable is taken. The aliasing information for the target variable is generated using the modified computer program.

Abstract: Core commands and aggregations of such commands are provided to programmers to enable them to generate programs that can be parallel-processed without requiring the programmer to be aware of parallel-processing techniques. The core commands and aggregations abstract mechanisms that can be executed in parallel, enabling the programmer to focus on higher-level concepts. The core commands provided include commands for applying a function in parallel and distributing and joining data in parallel. The output of each core command can implement an interface that can enable underlying mechanisms to stitch together multiple core commands in a cohesive manner to perform more complex actions.

Abstract: From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.

Abstract: A method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations. The method includes collecting all alias information using interprocedural point escape analysis, and collecting all shape information using interprocedural shape analysis. The method progresses with selecting the candidate dynamic objects based on alias and shape analysis, and determining the types of data reshaping for the candidate dynamic objects. The method further includes creating objects for selected dynamic objects with multiple object instantiations. The method proceeds by updating the memory allocation operations for the selected dynamic objects and inserting statements to initialize object descriptors. The method further includes creating the copy of the object descriptors for selected dynamic object assignments. The method concludes by replacing the object references by array-indexed references for selected dynamic objects using object descriptors.

Abstract: A method and apparatus that utilizes techniques for formatting assembly and/or machine code, including using arrows, indentations and textual symbols, so that a programmer who reads the code has an enhanced understanding of the program flow. Different methods of assessing computing time complexity (e.g., the up branch method and the strongly connected subgraph method) have strengths and weaknesses but benefit from being used together.

Abstract: A method for scheduling execution of a work unit in a data processing system, wherein the execution of the work unit involves the execution of at least one program, the method comprising: providing a first collection of pieces of information necessary to execute the work unit, said first collection of pieces of information being arranged in at least one pre-defined, re-usable program profile corresponding to the at least one program to be executed; receiving, in a request for scheduling execution of the work unit, a second collection of pieces of information necessary to execute the work unit; determining execution information for the execution of the work unit based on the first and second collections of pieces of information, and scheduling the execution of the work unit based on the determined execution information.

Abstract: According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by overlapping; that is, all iterations must impose a partial execution order. According to one embodiment, the inventive subject matter may be used to transform the dependence structure of a given loop with recurrences for maximal degree of thread-level parallelism (TLP), where the threads can be mapped on to either different logical processors (in a hyperthreaded processor) or can be mapped onto different physical cores (or processors) in a multi-core processor.

Abstract: A method and apparatus for programming a computer to execute a batch data processing procedure using a computing device having at least a processor, a memory, a display device and an input device. The memory stores a plurality of functions arranged to process individual data messages or batches of data messages. A function is selected from the plurality of functions and retrieved from the memory. A data flow diagram is arranged on the display, in response to developer input, to specify a process. The data flow diagram includes a function icon corresponding to the selected function, at least one data icon corresponding to a data object, and at least one link connecting the function icon to the data icon. The function is arranged to perform one of disassociating a batch of data messages into individual data messages and associating data messages into a batch of data messages.

Abstract: A data flow graph processing method divides a program describing target operations into two or more subprograms and converts each of the two or more subprograms into a data flow graph (DFG) representing dependency in execution between operations carried out in sequence. Also generated is flow data indicating the order of execution of DFGs corresponding to respective subprograms. DFGs are converted into configuration data and the flow data is converted into control data.

Abstract: A system and method for static detection and categorization of information-flow downgraders includes transforming a program stored in a memory device by statically analyzing program variables to yield a single assignment to each variable in an instruction set. The instruction set is translated to production rules with string operations. A context-free grammar is generated from the production rules to identify a finite set of strings. An information-flow downgrader function is identified by checking the finite set of strings against one or more function specifications.

Abstract: Embodiments of the present invention provide for minimizing the number of procedure frame unwinding operations to be performed when restoring the program control flow information. A first data structure may be constructed to contain procedure linkage information along with references to the conventional memory area where each procedure linkage information element (procedure return address or a procedure frame pointer) was originally found. The first data structure may be initialized upon the initial request for program control flow information. Upon each subsequent request, the contents of the conventional memory area as referenced by the first data structure may be compared with the corresponding elements of the first data structure. As a result of said comparison, changed and unchanged regions within the conventional memory area may be determined. Then, procedure frame unwinding operations may be performed for the changed regions.

Abstract: In an implementation, a computing device-implemented method includes identifying a non-blocking block in a graphical block diagram that includes the non-blocking block and other blocks, the other blocks including one or more non-blocking blocks, one or more blocking blocks, or a combination of one or more non-blocking blocks and one or more blocking blocks, determining whether one or more of the other blocks are dependent on an output from the non-blocking block, and partitioning execution of the non-blocking block into two or more execution stages, generating an order of execution of the graphical blocks, the order including a first stage of execution of the two or more execution stages for the non-blocking block, followed by an execution of one or more of the other blocks that have been determined not be dependent on the output from the non-blocking block, followed by a second stage of execution of the two or more execution stages.

Abstract: A data flow graph processing method divides at least one DFG generated into a plurality of sub-DFGs, in accordance with the number of logic circuits in a circuit set in a reconfigurable circuit. When the reconfigurable circuit is provided with a structure including multiple-row connections, the number of columns in the sub-DFG is configured to be equal to or fewer than the number of logic circuits per row in the reconfigurable circuit. Subsequently, the sub-DFGs are joined so as to generate a joined DFG. The number of columns in the joined DFG is also configured to be equal to or fewer than the number of columns per row in the reconfigurable circuit. The joined DFG is redivided to sizes with number of rows equal to or fewer than the number of rows in the reconfigurable circuit, so as to generate subjoined DFGs mappable into the reconfigurable circuit.

Abstract: A method for generating a fine slice for a program is provided. The method comprises receiving a set of slicing criteria, wherein the set of slicing criteria comprises one or more variable occurrences or control dependences; receiving a set of cut points, wherein the set of cut points comprises one or more variable occurrences or control dependences; and generating a slice according to the set of slicing criteria and the set of cut points. The generated slice includes statements related to computation of values for the set of slicing criteria and excludes statements related to computation of values for the set of cut points. Missing information is added to the slice so that the slice is executable.

Abstract: Techniques for reliable binary instrumentation based on annotation information are described. A binary file that comprises a code section representing the executable code of a computer program is accessed. The binary file also comprises annotation information that indicates the boundaries of one or more portions of the computer program. Accurate data flow information and control flow information may be generated based on the annotation information included in the binary file. The binary file is instrumented by inserting a set of instrumentation code at one or more points in the code section of the computer program. The one or more points are determined based on the data flow information and the control flow information.

Abstract: A computer-implemented method for determining whether an array within a loop can be privatized for that loop is presented. The method calculates the array sections that require first or last privatization and copies only those sections, reducing the privatization overhead of the known solutions.

Abstract: Disclosed are systems, methods and computer program products for efficient and reliable analysis, optimization and detection of obfuscated malware. One disclosed example method for malware detection includes loading an executable software code on a computer system and disassembling the software code into an assembly language or other low-level programming language. The method then proceeds to simplifying complex assembly instructions and constructing a data flow model of the simplified software code. The dependencies and interrelations of code elements of the data flow model are analyzed to identify obfuscated software codes therein. The identified obfuscated codes are then optimized. Based on the results of optimization, determination is made whether the software code is malicious and/or whether further antimalware analysis of the optimized software code is necessary.

Abstract: A method and apparatus for providing native undo, redo, and abort execution abilities of a runtime is disclosed. In one embodiment, a system includes a runtime to execute object-oriented source code with producer dependency declarations for methods, wherein a producer is a runtime instantiatable construct that includes at least an instance and a method associated with that instance, wherein each producer dependency declaration for a given method identifies a set of zero or more producers with outputs that are an input to the given method. According to one embodiment of the invention, the runtime includes a client code tracking module to track the client code commands being run by the runtime. Furthermore, in one embodiment, the runtime also includes a runtime tracking module to track processes of the runtime performed in response to the client code commands being tracked and run by the runtime.

Abstract: A method for handling Simple Instruction Multiple Data (SIMD) architecture restrictions through data reshaping, padding, and alignment, including: building a global call graph; creating array descriptors for maintaining array attributes; gathering array affinity information; performing global pointer analysis and escape analysis; performing loop-based analysis to identify a SIMD opportunity; building an array affinity graph; performing graph partitioning on the array affinity graph to construct an array reshaping plan; performing data reshaping on the array affinity graph; and performing SIMDization on the array affinity graph wherein SIMDization comprises automatic generation of SIMD code.

Abstract: The present invention discloses a modified computer architecture which enables an applications program to be run simultaneously on a plurality of computers. Shared memory at each computer is updated with amendments and/or overwrites so that all memory read requests are satisfied locally. During initial program loading, or similar, instructions which result in memory being re-written or manipulated are identified. Additional instructions are inserted to cause the equivalent memory locations at all computers to be updated.

Abstract: A system and method for managing data, such as in a data warehousing, analysis, or similar applications, where dataflow graphs are expressed as reusable map components, at least some of which are selected from a library of components, and map components are assembled to create an integrated dataflow application. Composite map components encapsulate a dataflow pattern using other maps as subcomponents. Ports are used as link points to assemble map components and are hierarchical and composite allowing ports to contain other ports. The dataflow application may be executed in a parallel processing environment by recognizing the linked data processes within the map components and assigning threads to the linked data processes.

Abstract: System and method for performing program-related operations over a network via a web browser. A network connection is established between a server computer and a client computer over a network. A universal resource identifier (URI) is sent from the client computer to the server computer over the network, where the URI indicates a program, e.g., a graphical program (GP), or at least a portion of a graphical program interactive development environment (GPIDE), e.g., a graphical program editor, an execution engine, a static or dynamic analyzer, and/or compiler. The at least a portion of the GPIDE is received from the server computer over the network in response to the URI, and executed in a web browser of the client computer to perform some specified functionality with respect to the GP.

Abstract: System and method for converting a class oriented data flow program to a structure oriented data flow program. A first data flow program is received, where the first data flow program is an object oriented program comprising instances of one or more classes, and wherein the first data flow program is executable to perform a first function. The first data flow program is automatically converted to a second data flow program, where the second data flow program does not include the instances of the one or more classes, and where the second data flow program is executable to perform the first function. The second data flow program is stored on a computer memory, where the second data flow program is configured to be deployed to a device, e.g., a programmable hardware element, and where the second data flow program is executable on the device to perform the first function.

Abstract: System and method for converting a class oriented data flow program to a structure oriented data flow program. A first data flow program is received, where the first data flow program is an object oriented program comprising instances of one or more classes, and wherein the first data flow program is executable to perform a first function. The first data flow program is automatically converted to a second data flow program, where the second data flow program does not include the instances of the one or more classes, and where the second data flow program is executable to perform the first function. The second data flow program is stored on a computer memory, where the second data flow program is configured to be deployed to a device, e.g., a programmable hardware element, and where the second data flow program is executable on the device to perform the first function.

Abstract: A system, computer program product and method of processing function calls in a distributed application environment are provided. A number of function calls for communication from a sending application to a receiving application are queued in a database. Dependencies among at least a portion of the function calls that are being queued are determined while the function calls are stored in the queues. A schedule of execution of the function calls is then generated based on the determined dependencies.

Abstract: A method for executing a loop in an application that includes executing iterations in a first segment of the loop by a base thread, logging memory transactions that occur during execution of iterations in the first segment by a co-inspector thread to obtain a co-inspector log, executing iterations in a second segment of the loop by a co-thread to obtain temporary results, logging memory transactions that occur during execution of iterations in the second segment to obtain a co-thread log, and comparing the co-inspector log and the co-thread log to determine whether a thread interdependency exists.

Abstract: A method, apparatus and program product are provided for parallelizing analysis and optimization in a compiler. A plurality of basic blocks and a subset of data points of a computer program is prepared for processing by a main thread selected from a plurality of hardware threads. The plurality of prepared basic blocks and subset of data points are placed in a shared data structure by the main thread. A prepared basic block of the plurality of prepared basic blocks and/or a tuple associated with the subset of data points is concurrently retrieved from the shared data structure by a work thread selected from the plurality of hardware threads. A compiler analysis or optimization is performed on the prepared basic block or tuple by the work thread.