Abstract: System and method for implicit downcasting at compile time in a data flow program. A first data flow function in an object-oriented dataflow program is identified, where the first function includes an input of a parent data type and an output of the parent data type. The first function is analyzed to determine if the output preserves the run-time data type of the input. A second dataflow function in the object-oriented data flow program is identified, where the second function includes a program element that calls the first function, passing an input parameter of a child data type of the parent data type as input. If the analysis determines that an output parameter returned by the output of the first function will always be of the child data type, the program element is automatically configured at compile time to always downcast the output parameter from the parent data type to the child data type at run-time.

Abstract: Systems and methods are described for automatically transforming essentially sequential code into a plurality of codes which are to be executed in parallel to achieve the same or equivalent result to the sequential code. User-defined task boundaries are determined in the input code to thereby define a plurality of tasks. It is then determined if the essentially sequential application code can be separated at at least one of said user-defined tasks boundaries and if so at least one code of the plurality of codes for at least one of said tasks is automatically generated.

Abstract: A system that estimates a dominant computational resource which is used by a computer program. During operation, for each basic block in the computer program, the system determines a nesting level for the basic block. Next, the system selects basic blocks with nesting levels greater than a specified threshold. For each selected basic block, the system analyzes the basic block to estimate the dominant computational resource used by the basic block. The system then uses the estimated dominant computational resources for the selected basic blocks to estimate the dominant computational resource for the computer program.

Abstract: Those files accessed by tools during a build process are invisibly tracked in such a way that the information can then be used to drive an incremental build of just enough files to bring the build fully up to date. The tracking information includes the association between distinct tool processes. Each build tool has its own file activity tracked, each thread of operation within tools are tracked separately and a tracking log is associated with a chain of tool processes so that when the tracking logs are interpreted the context in which they were created is preserved.

Abstract: The present invention provides a method, system, and program product for composing a virtualized computing environment. Specifically, under the present invention, data and a definition file that contains application runtime requirements for the data are stored on a portable memory device. Application runtime requirements can be anything related to an environment in which the data was previously used. When the portable memory device is received in a computerized device, an auto-insert script can be executed that signals a provisioning system and/or transports the definition file to the provisioning system. The provisioning system will then interpret the definition file on the computerized device to retrieve the application runtime requirements. Then, the virtualized computing environment will be composed by adapting an environment of the computerized device according to the application runtime requirements retrieved from the definition file.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: In one embodiment, the present invention includes a method for partitioning a program segment into at least a first stage and a second stage, determining a live set of variables and control flow information alive at a boundary between the first and second stages, and controlling the first stage to transmit a trace-specific portion of the live set for a first trace to the second stage via a communication channel. In such manner, reduced transmission of data between the stages is effected. Other embodiments are described and claimed.

Abstract: In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Abstract: A programmable device suitable for software defined radio terminal is disclosed. In one aspect, the device includes a scalar cluster providing a scalar data path and a scalar register file and arranged for executing scalar instructions. The device may further include at least two interconnected vector clusters connected with the scalar cluster. Each of the at least two vector clusters provides a vector data path and a vector register file and is arranged for executing at least one vector instruction different from vector instructions performed by any other vector cluster of the at least two vector clusters.

Abstract: The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.

Abstract: An input unit inputs specification description that includes a plurality of pieces of processing information each indicative of a processing performed by a design object and association information indicative of associations among the processing information. A node generating unit generates a node for each of the processing information. A link generating unit generates, based on the association information, a link that couples nodes generated by the node generating unit. A sub-chart generating unit configured to generate a plurality of sub-charts by dividing a chart indicating a content of the specification description, based on the node and the link. A function-module generating unit generates, for each of the sub-charts, a function module that executes a function based on the processing information corresponding to the node in the sub-chart and the association information corresponding to the link in the sub-chart.

Abstract: A method and apparatus for disambiguating in a dynamic binary translator is described. The method comprises selecting a code segment for load-store memory disambiguation based at least in part on a measure of likelihood of frequency of execution of the code segment; heuristically identifying one or more ambiguous memory dependencies in the code segment for disambiguation by runtime checks; based at least in part on inspecting instructions in the code segment, and using a pointer analysis of the code segment to identify all other ambiguous memory dependencies that can be removed by the runtime checks.

Abstract: Presently described is a decompilation method of operation and system for parsing executable code, identifying and recursively modeling data flows, identifying and recursively modeling control flow, and iteratively refining these models to provide a complete model at the nanocode level. The nanocode decompiler may be used to determine if flaws, security vulnerabilities, or general quality issues exist in the code. The nanocode decompiler outputs in a standardized, human-readable intermediate representation (IR) designed for automated or scripted analysis and reporting. Reports may take the form of a computer annotated and/or partially human annotated nanocode listing in the above-described IR. Annotations may include plain English statements regarding flaws and pointers to badly constructed data structures, unchecked buffers, malicious embedded code or “trap doors,” and the like. Annotations may be generated through a scripted analysis process or by means of an expert-enhanced, quasi-autonomous system.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. A first availability chain is created from a producer instruction (p1) to a first consumer instruction (c1), when the execution of the instruction requires a value produced by the producer instruction. The first availability chain includes at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the producer execution unit to a second point (22: DRF) accessible by a first consumer execution unit. When a second consumer instruction (c2), also requiring the same value, is scheduled for execution by an execution unit (23: EXU) other than the first consumer execution unit, at least part of the first availability chain is reused to move the required value to a point (23: DRF) accessible by that other execution unit.

Abstract: Methods and apparatus to create software basic block layouts are disclosed. In one example, a method identifies branch data associated with a plurality of machine accessible instructions and identifies a plurality of basic blocks associated with the branch data. The method generates a partial layout from the plurality of basic blocks and generates a substantial layout from the partial layout based on a cost metric.

Abstract: Optimizing program code in a static compiler by determining the live ranges of variables and determining which live ranges are candidates for moving code from the use site to the definition site of source code. Live ranges for variables in a flow graph are determined. Selected live ranges are determined as candidates in which code will be moved from a use site within the source code to a definition site within the source code. Optimization opportunities within the source code are identified based on the code motion.

Abstract: A system for automatically counting function points is provided. The system includes an electronic document, an analysis component, and a user interface. The electronic document contains a sequence diagram that specifies interactions in a software application. The analysis component can analyze the interactions in the sequence diagram to identify a start point and an end point in the sequence diagram as a function point. The analysis component can also maintain a count of the function points. The user interface can promote counting one or more function points when more than one of the sequence diagrams involve data that is part of a set of data objects identified via the user interface.

Abstract: An intermediate representation of sequences of instructions for a stacked based computer is a code graph using a numbering method on the nodes of the graph, along with a set of relations among the nodes, to determine, in a single pass, the independence of each node or sub-graph represented by the node. The numbering is a post-order that directly, by numerical comparison defines the relevant hierarchical relationships among sub-graphs. The sub-graph of a particular node may have one or more alias nodes that refers to target nodes, a target node being a node representing an argument which is the result of a previous program instruction. For a subgraph to be considered independent, any aliases generated by nodes within the subgraph must themselves be contained in it, and conversely, any aliases in the subgraph must have been generated by nodes also within it.

Abstract: A system and method for optimizing compiler performance including outlining cold code at link time, rather than compile time, such that trampolines are not required. Branch instructions connecting a hot block to a cold block can be converted from a short branch distance limit to a longer branch distance limit, further optimizing code performance. Editors, implementing a plurality of windows that can be maintained for each function, can display the maximum distance that code blocks can be safely outlined. Other implementations allow the optimal placement of code that is significantly greater in size than the maximum possible branch distance.

Abstract: A system for binary code instrumentation to reduce effective memory latency comprises a processor and memory coupled to the processor. The memory comprises program instructions executable by the processor to implement a code analyzer configured to analyze an instruction stream of compiled code executable at an execution engine to identify, for a given memory reference instruction in the stream that references data at a memory address calculated during an execution of the instruction stream, an earliest point in time during the execution at which sufficient data is available at the execution engine to calculate the memory address. The code analyzer generates an indication of whether the given memory reference instruction is suitable for a prefetch operation based on a difference in time between the earliest point in time and a time at which the given memory reference instruction is executed during the execution.

Abstract: A computer-implemented system and method are described for measuring the memory consumption difference between two objects in an object-oriented programming environment. For example, one embodiment of a method comprises: analyzing relationships between objects within a network of objects to determine an object network structure; generating object graph data representing the object network structure, the object graph data including nodes representing objects and arcs representing relationships between objects; removing all incoming arcs to each of two nodes; building resulting sub-graphs for each of the two nodes; summing the memory consumed by each of the sub-graphs of the two nodes; and subtracting the memory amounts consumed by each of the sub-graphs to determine the memory consumption different between the two nodes.

Abstract: A system and method to perform post pass optimizations in a dynamic compiling environment. A dynamic compiler emits machine code. Responsive to the emission of the machine code a post pass processor creates an abstract representation of the code from the dynamic compiler. Data flow analysis is then conducted on the abstract representation. Redundant instructions in the machine code are identified and eliminated as a result of the data flow analysis.

Abstract: Analysis of object flow during execution of individual instructions of a method within an object-oriented application provides information regarding the creation and flow of objects during an invocation of the method. This analysis information is used to track where objects enter an invocation of the method and track their path during the execution of the method. The operand stack, register, and local variables references to the objects are tracked as each instruction in the method is executed. Where objects are passed to elements outside of the method invocation is tracked as well. This tracking of object flow uses an iterative data-flow analysis. If an object is passed to the method or created within the method, the embodiments described herein may be used to determine where that object can go from that point onwards, whether to other method invocations, arrays, or data fields within the application.

Abstract: Commercial data processors are available that include a capability of extending their instruction set for a specified application, i.e. of introducing customized functional units in the interest of enhanced processing performance. For such processors there is a need for automatically forming the extensions from high-level application code. A technique is described for selecting maximal-speedup convex subgraphs of the application dataflow graph under micro-architectural constraints.

Abstract: Creating explicit control flow in an implicit control flow development environment. A set of explicit functions is defined in a library associated with the implicit control flow development environment. Each of the explicit functions in the set is associated with a sequence of implicit functions, such that by calling the explicit function, the sequence of selected implicit functions are called to programmatically perform the task defined by the explicit function. Property types may be designated for the explicit functions, wherein the property types are used by the sequence of implicit functions in performing the task. The explicit functions are exposed to a developer using the implicit flow development environment. The developer selects the desired explicit functions and properties for creation and execution of the application.

Abstract: A method for detecting a race condition using static analysis that includes determining a first permit set and a second permit set, and performing a static analysis, wherein the static analysis comprises using the first permit set and the second permit set to detect a race condition, wherein the static analysis is performed before accessing critical data and includes determining whether the intersection of the first permit set and the second permit set is empty, and if the intersection of the first permit set and the second permit set is empty, then outputting a value indicating the detection of a race condition.

Abstract: A method and apparatus for optimizing register allocation during scheduling and execution of program code in a hardware environment. The program code can be compiled to optimize execution given predetermined hardware constraints. The hardware constraints can include the number of register read and write operations that can be performed in a given processor pass. The optimizer can initially schedule the program using virtual registers and a goal of minimizing the amount of active registers at any time. The optimizer reschedules the program to assign the virtual registers to actual physical registers in a manner that minimizes the number of processor passes used to execute the program.

Abstract: The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of a loop in the program code. The vector-control instruction identifies elements in the vector instruction that may be operated on in parallel without causing an error due to a runtime data dependency between the iterations of the loop. The processor then executes the loop by repeatedly executing the vector-control instruction to identify a next group of elements that can be operated on in the vector instruction and selectively executing the vector instruction to perform the operation for the next group of elements in the vector instruction, until the operation has been performed for all elements of the vector instruction.

Abstract: Generating parallelized executable code from input code includes statically analyzing the input code to determine aspects of data flow and control flow of the input code; dynamically analyzing the input code to determine additional aspects of data flow and control flow of the input code; generating an intermediate representation of the input code based at least in part on the aspects of data flow and control flow of the input code identified by the static analysis and the additional aspects of data and control flow of the input code identified by the dynamic analysis; and processing the intermediate representation to determine portions of the intermediate representation that are eligible for parallel execution; and generating parallelized executable code from the processed intermediate representation

Abstract: A system and method for determining where bottlenecks in a program's data accesses occur and providing information to a software developer as to why the bottlenecks occur and what may be done to correct them. A stream of data access references is analyzed to determine data access patterns (also called data access sequences). The stream is analyzed to find frequently repeated data access sequences (called hot data streams). Properties of the hot data streams are calculated and upon selection of a hot data stream are displayed in a development tool that associates lines of code with the hot data streams.

Abstract: A dataflow instruction set architecture and execution model, referred to as WaveScalar, which is designed for scalable, low-complexity/high-performance processors, while efficiently providing traditional memory semantics through a mechanism called wave-ordered memory. Wave-ordered memory enables “real-world” programs, written in any language, to be run on the WaveScalar architecture, as well as any out-of-order execution unit. Because it is software-controlled, wave-ordered memory can be disabled to obtain greater parallelism. Wavescalar also includes a software-controlled tag management system.

Abstract: A system and method for visually indicating one or more problems in a graphical program. The graphical program may be programmatically analyzed to discover a problem (or potential problem) in the graphical program. The problem found during the programmatic analysis of the graphical program may then be visually indicated on a display device. Visually indicating the problem may comprise visually indicating one or more objects in the graphical program to which the problem corresponds. Visually indicating the graphical program object(s) may comprise displaying information or altering the appearance of the object(s) in order to call the user's attention to the object(s).

Abstract: A method is presented including assigning a first register class to at least one symbolic register in at least one instruction, determining and assigning a second register class to the at least one register, reducing register class fixups and renaming the at least one symbolic register. Also presented is a system including a processor having at least one register and a compiler executing in the processor that inputs a source program having many operation blocks. The compiler assigns a first register class in at least one instruction to at least one symbolic register, determines and assigns a second register class to the at least one symbolic register, reduces register class fixups, and renames the at least one symbolic register.

Abstract: A computer is caused to function as a parsing unit, a macroblocking analyzing unit, a junction-node restructuring unit, an identical portion merging/restructuring unit, a similar portion merging/restructuring unit, and an intermediate language restructuring unit. The parsing unit performs syntax analysis of a source code. The macroblocking analyzing unit segments the program written in the source code into blocks and appends a virtual portion representing a unique number in a statement, to a number for identifying a variable for the statement in each block to virtualize a calculation pattern. The junction-node restructuring unit extracts a node directly related to a subroutine block. The identical portion merging/restructuring unit merges pre-processing together and post-processing together for a subroutine called up at a multiple portions in the program. The similar portion merging/restructuring unit integrates subroutines having similar structures into a related subroutine.

Abstract: Methods and systems of detecting vulnerabilities in source code using inter-procedural analysis of source code. Vulnerabilities in a pre-existing source code listing are detected. The variables in the source code listing are modeled in the context of at least one of the inherent control flow and inherent data flow. The variable models are used to create models of arguments to routine calls in the source code listing. The source code listing is modeled with a call graph to represent routine call interactions expressed in the source code listing. The arguments to routine calls are modeled to account for inter-procedural effects and dependencies on the arguments as expressed in the source code listing.

Abstract: Techniques are disclosed for workflow based high availability analysis in computing systems. For example, a computer-implemented method for analyzing an information network infrastructure to identify one or more availability weak points includes the following steps. A workflow specification is provided based on one or more user-visible processes and an application topology. Service workflows associated with the specification are mapped from the application topology to the infrastructure to generate a workflow data structure. An availability weak point analysis is performed in accordance with the workflow data structure to determine one or more optimal high availability parameters for one or more deployed components of the infrastructure. The one or more optimal high availability parameters are applied in the infrastructure so as to substantially eliminate the one or more availability weak points.

Abstract: A local analysis analyzes the values of objects paying attention to program flow and a global analysis analyses the object independent of the flow. The local and global analysis interact to infer the invariants of objects used within a computer program. The local analysis is given the known invariants of an object by the global analysis when the object transitions from a valid to a mutable state. It then keeps track of all of the values of objects encountered until the object transitions from mutable to a valid state, when the information known to the local analysis is passed to the global analysis, which may use the new object values to add to the current list of invariants for the given object.

Abstract: The invention relates to a method and an automated system for determining the processing sequence of function blocks of a technological function. According to said method, a first function block, whose outputs are respectively disconnected or form exclusively one or more output signals of the technological function, is determined. Starting from said first function block, a second function block is sought in the opposite direction to the signal flow direction, whereby the block inputs of said second block are respectively disconnected or receive one or more input signals of the technological function only.

Abstract: Embodiments of the present invention provide for minimizing the number of procedure frame unwinding operations to be performed when restoring the program control flow information. A first data structure may be constructed to contain procedure linkage information along with references to the conventional memory area where each procedure linkage information element (procedure return address or a procedure frame pointer) was originally found. The first data structure may be initialized upon the initial request for program control flow information. Upon each subsequent request, the contents of the conventional memory area as referenced by the first data structure may be compared with the corresponding elements of the first data structure. As a result of said comparison, changed and unchanged regions within the conventional memory area may be determined. Then, procedure frame unwinding operations may be performed for the changed regions.

Abstract: A state component saves a present state of a program or model. This state component can be invoked by the program or model itself, thereby making state a first-class citizen. As the state of the program evolves from the saved state, the saved state remains for reflection and recall, for example, for testing, verification, transaction processing, etc. Using a state reference token, the saved state of the program or model can be accessed by the program or model. For example, the program or model by utilizing a state component, can return itself to the saved state. After returning to the saved state, a second execution path can be introduced without requiring re-execution of the actions leading to the saved state. In another example, the state space of an executing model is saved in order to generate inputs required to exercise a program or model.

Abstract: Repetitive synchronization in program code is optimized through lock coarsening that is performed subject to a number of constraints. Using a forward pass over the program code followed by a backward pass, region extent bits may be determined that identify the points in the program where object locking can be coarsened. The program code may then be modified to realize coarsened locking regions determined based on the region extent bits. Alternatively, previously determined value numbers may provide much of the information collected by the two passes. In such a case, a single pass over the program code may locate features that limit lock coarsening opportunities. A set of synchronization operations that can be removed may then be determined and used when modifying the program code to coarsen locking regions.

Abstract: A method for protecting software is provided, where source code for the software has a first directive marking an encryption beginning point and a second directive marking an encryption end point. The method contains the steps of: processing the source code to identify a block of code between the first and second directives; compiling the source code to produce a binary file; generating a valid key and a random string; encrypting the random string with the key to obtain a first encrypted value; encrypting a portion of the binary file corresponding to the block of code with the valid key to obtain a second encrypted value; and replacing the portion of the binary file corresponding to the block of code with the second encrypted value and code that can decrypt the second encrypted value during execution of the software.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: A method of intra-block memory usage analysis for a program can include identifying a memory block that has been allocated to the program and determining at least one intra-memory block usage characteristic for the allocated memory block.

Abstract: A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Abstract: A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

Abstract: A program development supporting apparatus that groups a plurality of events each executed in an information processor to divide the events into a plurality of parallel execution units to be executed in parallel with each other has a directional graph acquisition section that acquires directional graph data expressing each of the plurality of events as a vertex and a restriction on the execution order between two of the plurality of events as a directional branch, an inverse chain partial set extraction section that traces the directional branch from each event in the forward direction to extract from the directional graph data an inverse partial set that is a combination of the events having such a relationship that any one of the events cannot be reached from the other events, and a parallel execution unit assignment section that assigns the plurality of events belonging to the inverse partial set to units different from each other in the parallel execution units.

Abstract: A method for improving compile speed in irreducible code regions within a computer program is disclosed. The method comprises determining which of a plurality of code regions within a computer program is irreducible, determining an influence of the irreducible code on blocks within code regions, determining a direction of processing based on the influence of the irreducible code on adjacent blocks and performing a processing based on a current direction of processing and the determined direction of processing.

Abstract: There is disclosed a system for flattening hierarchically structured flows using a breadth-first approach. At each level of hierarchy of a hierarchically structured source flow, complex nodes are flattened by one level across the entire breadth of the flow. The results of this flattening are placed in a target flow, and any connections that existed in the source flow are reestablished in the target flow in such a way that any data input into the target flow will be processed as if it had been input into the source flow. After a processing iteration, if there are still complex nodes remaining in the target flow, the target flow becomes the next source flow, and the process is repeated until the flow has been completely flattened.