Abstract: A system, computer program product and method of processing function calls in a distributed application environment are provided. A number of function calls for communication from a sending application to a receiving application are queued in a database. Dependencies among at least a portion of the function calls that are being queued are determined while the function calls are stored in the queues. A schedule of execution of the function calls is then generated based on the determined dependencies.

Abstract: A computer implemented method, system and computer program product for accessing threadprivate memory for threadprivate variables in a parallel program during program compilation. A computer implemented method for accessing threadprivate variables in a parallel program during program compilation includes aggregating threadprivate variables in the program, replacing references of the threadprivate variables by indirect references, moving address load operations of the threadprivate variables, and replacing the address load operations of the threadprivate variables by calls to runtime routines to access the threadprivate memory. The invention enables a compiler to minimize the runtime routines call times to access the threadprivate variables, thus improving program performance.

Abstract: The present invention is a method of eliminating loops from a computer program by receiving the program, graphing its function and control, identifying its entry point, and identifying groups of loops connected to its entry point. Stop if there are no such groups. Otherwise, selecting a group of loops. Then, identifying the selected group's entry point. If the selected group includes no group of loops having a different entry point then replacing it with a recursive or non-recursive function, reconfiguring each connection entering and exiting the selected group to preserve their functionality, and returning to the fifth step. Otherwise, identifying groups of loops in the selected group connected to, but having different entry points and returning to the loop selection step.

Abstract: Apparatus and methods for performing generational escape analysis in managed runtime environments are disclosed. The disclosed apparatus and methods determine the generational age of an equivalence class while performing escape analysis. Equivalence classes having generational ages are cloned if their generational ages are less than a threshold age.

Abstract: A method includes extracting at least one object file from a library of object files. The method also includes identifying an interprocedural optimization associated with a plurality of object files. The plurality of object files includes the at least one extracted object file. The method further includes invoking recompilation of at least one of the plurality of object files to implement the identified interprocedural optimization. In addition, the method includes generating at least one executable file using the at least one recompiled object file. The plurality of object files could include interprocedural summary information generated by a compiler during a compilation of at least one source file and a compiler internal representation associated with the compiler during the compilation. The interprocedural optimization could be identified using the interprocedural summary information, and the at least one recompiled object file could be generated using the compiler internal representation.

Abstract: A method and apparatus for use in compiling data for a program shader identifies within data representing control flow information an area operator definition instruction statement located outside the data dependent control flow structures. The method identifies within one of the data dependent branches at least one area operator use instruction statement that has the resultant of the area operator definition instruction statement as an operand. After identifying the area operator use instruction statement, the area operator definition instruction statement is placed within the data dependent branch.

Abstract: A region-based register allocation system, method, and computer-program product not only provides a scalable framework across multiple applications, but also improves application runtime. They include a register pressure based model, to determine when using multiple regions may be profitable, the use of different regions for each register class, and a new region formation algorithm.

Abstract: A compiling program with cache utilization optimizations employs an inter-procedural global analysis of the data access patterns of compile units to be processed. The global analysis determines sufficient information to allow intelligent application of optimization techniques to be employed to enhance the operation and utilization of the available cache systems on target hardware.

Abstract: In a computer where a software development tool program is started, an updating elapse degree and an execution frequency for a series of source programs used for generating an execution module are acquired. An optimization option of the level according to the updating elapse degree or the execution frequency is set for each of the source programs. Compiling accompanied by the optimization of the level indicated by the optimization option is performed for each of the source programs. Object programs created by the compiling are coupled.

Abstract: A post-compilation tool can rewrite executable images produced by a compiler. The tool can add extension definitions, insert extension-trigger instructions, and add a security signature. Operating system software may be notified of extension capabilities when loading the executable image, and may proceed to load an appropriate processor extension. The operating system software can manage availability of processor extensions on behalf of the applications.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. A first availability chain is created from a producer instruction (p1) to a first consumer instruction (c1), when the execution of the instruction requires a value produced by the producer instruction. The first availability chain includes at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the producer execution unit to a second point (22: DRF) accessible by a first consumer execution unit. When a second consumer instruction (c2), also requiring the same value, is scheduled for execution by an execution unit (23: EXU) other than the first consumer execution unit, at least part of the first availability chain is reused to move the required value to a point (23: DRF) accessible by that other execution unit.

Abstract: An intermediate representation of sequences of instructions for a stacked based computer is a code graph using a numbering method on the nodes of the graph, along with a set of relations among the nodes, to determine, in a single pass, the independence of each node or sub-graph represented by the node. The numbering is a post-order that directly, by numerical comparison defines the relevant hierarchical relationships among sub-graphs. The sub-graph of a particular node may have one or more alias nodes that refers to target nodes, a target node being a node representing an argument which is the result of a previous program instruction. For a subgraph to be considered independent, any aliases generated by nodes within the subgraph must themselves be contained in it, and conversely, any aliases in the subgraph must have been generated by nodes also within it.

Abstract: A class hierarchy graph defining the baseclass-subclass relationship between classes in an object-oriented program is built by analysis of the intermediate representation of the program produced by a compiler front end. This representation includes virtual tables for classes that include virtual functions and type structure information for the classes provided to aid run time type identification (RTTI). The class hierarchy information cannot be identified from the virtual tables alone but can be identified from the type structure information.

Abstract: A method to facilitate memory allocation includes examining an executable program file configured to be executed by a processor to identify a group of functions present within the executable program file, and calculating memory requirements for each function of the group of functions. Further operations include identifying a plurality of root functions as functions which are not referred to by other functions, creating a function call tree for each of the plurality of root functions, such that each of the function call trees comprise functions which are directly or indirectly referred to by an associated one of the plurality of root functions, and calculating memory requirements for one or more function call paths of each of the function call trees based upon the calculated memory requirements of the functions included within the one or more function call paths.

Abstract: A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and removing the redundant exception handling code. The operation of identifying redundant exception handling code may comprise identifying at least one function or callsite by determining that a first function in the at least one function's or callsite's callee chain throws an exception and that the exception is handled by a second function in the function's or callsite's callee chain or by determining that an exception is not thrown in the at least one function's or callsite's callee chain. The operation of removing the redundant exception handling code may comprise removing redundant exception handling code included in at least one function or callsite and/or removing at least one entry for the at least one function or callsite from an exception lookup table.

Abstract: A system and method of detecting redundant subroutine calls in a software system is provided. Call path data is obtained for the software system and stored into a call tree comprising a plurality of nodes, each node representing a software routine of the software system, the call tree describing the calling paths between the plurality of software routines. At least one focal node is identified among the plurality of nodes in the call tree for redundancy analysis. The calling redundancy to the focal node is analyzed by determining a common ancestor node list for the focal node and by generating call path data for each of the common ancestor nodes on the list. The common ancestor list data may be sorted and call trees generated for the common ancestors in relation to the focal node. This data may then be displayed on a graphical user interface for redundancy analysis of the focal node.

Abstract: A system and method to perform post pass optimizations in a dynamic compiling environment. A dynamic compiler emits machine code. Responsive to the emission of the machine code a post pass processor creates an abstract representation of the code from the dynamic compiler. Data flow analysis is then conducted on the abstract representation. Redundant instructions in the machine code are identified and eliminated as a result of the data flow analysis.

Abstract: A code placement technique that organizes code units to at least reduce layout conflicts among caller/callee code units. A code preparation environment determines those code units of a code representation that have overlapping memory mappings with their counterpart caller/callee code units. To at least reduce the layout conflicts, or overlapping memory mappings, the code preparation environment arranges the caller/callee code units to eliminate the layout conflicts among the caller/callee code units.

Abstract: A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main entry point of the program; and recording an outgoing function call within a main function. The method also includes analyzing possible object types that may occur at any given instruction from any call path for virtual calls, wherein possible object types are determined by tracking object types as they pass through plural constructs; and calling into functions generically for handling specialized native runtime type information.

Abstract: A method for optimizing executable code includes identifying a plurality of instructions in the executable code matching a predetermined instruction pattern, assessing whether the binary number conforms to a predetermined bit pattern, and transforming the plurality of instructions into transformed instructions when the binary number conforms to the bit pattern.

Abstract: A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main entry point of the program; and recording an outgoing function call within a main function. The method also includes analyzing possible object types that may occur at any given instruction from any call path for virtual calls, wherein possible object types are determined by tracking object types as they pass through plural constructs; and calling into functions generically for handling specialized native runtime type information.

Abstract: A method and apparatus for provisioning a node with executable code is provided herein. Prior to sending out a code request, a node (101) determines a set of nodes that may potentially host the requested code and sends the request to these nodes instead of a blind broadcast. The determination of what nodes have access to the required code is based on a history information of code request of the node, the overhead traffic, and/or application dependencies that are available to the node. The code request is unicast-based and may involve a multi-hop path for both code requests and responses. If this step fails, a broadcast-based approach can be again employed to request the code.

Abstract: A method to automatically replace computationally intensive functions with optimized functions in managed code is disclosed. If the underlying processor has associated optimized functions, managed application code is disassembled and parsed to find computationally intensive functions. The computationally intensive functions are then replaced with optimized functions, and the application code is re-compiled if necessary.

Abstract: A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component/Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

Abstract: During a total temporal interval a plurality of characteristic values of the technical system are determined. The total temporal interval is divided into a plurality of partial intervals, each partial interval being between a partial interval starting point and a partial interval end point in the total interval. According to said method, for each partial interval, at least one parameter of a pre-determined predictive model is adapted to the characteristic values determined in the partial interval in such a way as to obtain a partial adaptation with which a partial interval and the end point of the partial interval are associated. Respectively one modification measure is determined for the partial adaptations in such a way as to indicate the modifications of the parameters of the respective partial adaptation in relation to the parameters of at least one adjacent partial adaptation.

Abstract: A method of generating a dynamic call graph of an application is disclosed. The method includes collecting information on what program code pages are accessed during each sampling period, defining parts of an executable program code which are accessible during each sampling period according to the collected information, defining a set of functions within the defined parts of the executable program code, generating dynamic call graphs using the defined set of functions for each sampling period, and generating dynamic call graphs for an observation period by combining accurate dynamic call graphs of each sampling period.

Abstract: Methods for representing and evaluating dependency systems are provided. In one implementation a method is provided. The method includes receiving a file. The file includes a node array having data entries corresponding to one or more nodes. The file also includes an edge array having data entries corresponding to one or more edges, the edge entries identifying an invertability state of an edge, a suppressed state of an edge, and one or more partner edge linking a first and a second edge in the edge array. The method also include processing the received file. In another implementations a method for evaluating dependencies in a cyclic system is provided as well as a method for evaluating an enhanced directed dependency graph.

Abstract: The present invention is a machine implemented, design automation method that assists a designer in the understanding of a software and/or hardware source code specification by transforming the source code into a simplified specification called a program slice. The present invention extends graph-based program slicing to the hardware-software interface that is commonly found in embedded systems. In addition to the known benefits of program slicing applied to a pure software or pure hardware, the present invention aids a designer in understanding the complex interaction between software procedures and hardware processing elements in the context of a codesign methodology.

Abstract: A computer-implemented method of finding portions of a computer program exhibiting irregular performance can include detecting an entry into a function of a computer program under test indicating a current execution of the function and, responsive to detecting an exit from the function, determining a count of a computing resource utilized by the function during the current execution of the function. The count of the computing resource can be compared with a count range determined according to at least one prior execution of the function. The function can be selectively represented within a call graph as a plurality of nodes according to the comparing.

Abstract: A computer implemented method, system and computer program product for accessing threadprivate memory for threadprivate variables in a parallel program during program compilation. A computer implemented method for accessing threadprivate variables in a parallel program during program compilation includes aggregating threadprivate variables in the program, replacing references of the threadprivate variables by indirect references, moving address load operations of the threadprivate variables, and replacing the address load operations of the threadprivate variables by calls to runtime routines to access the threadprivate memory. The invention enables a compiler to minimize the runtime routines call times to access the threadprivate variables, thus improving program performance.

Abstract: A method including analyzing a program to obtain information about variables within the program, generating a call graph based on the information, determining all possible aliases for each variable, identifying parallel accesses by two variables, a variable and an alias, and/or two aliases during an instruction in the program, generating an interference graph based on the parallel accesses, and assigning the variables to logical stacks based on the interference graph.

Abstract: A method for identifying a set of objects in a target application program includes: receiving a plurality of samples of one or more object reference graphs, wherein each object reference graph includes live objects and their references; deriving a set of candidate data structures from the samples; collecting a plurality of properties of each of the live objects in relation to data structures over time; and using a mixture model, combining the plurality of the properties of each live object in a non-linear manner for ranking leak root candidates within each set of candidate data structures The method also includes the identification of an initial set of highly-ranked candidate objects that are possible causes of at least one object leak, wherein the higher the ranking the smaller the identified set.

Abstract: An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.

Abstract: A development tool enables a device database to be created, managed, and deployed to a device as part of the a device project. The device database may have an installation property which provides logic for installing the device database at the device. Additionally, stored procedures and triggers may be registered with the device database. The registered stored procedures and triggers may be embedded in the device database and deployed to the device along with the device database.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: A software mechanism for enabling a programmer to embed selected machine instructions into program source code in a convenient fashion, and optionally restricting the re-ordering of such instructions by the compiler without making any significant modifications to the compiler processing. Using a table-driven approach, the mechanism parses the embedded machine instruction constructs and verifies syntax and semantic correctness. The mechanism then translates the constructs into low-level compiler internal representations that may be integrated into other compiler code with minimal compiler changes. When also supported by a robust underlying inter-module optimization framework, library routines containing embedded machine instructions according to the present invention can be inlined into applications. When those applications invoke such library routines, the present invention enables the routines to be optimized more effectively, thereby improving run-time application performance.

Abstract: A program development supporting apparatus that groups a plurality of events each executed in an information processor to divide the events into a plurality of parallel execution units to be executed in parallel with each other has a directional graph acquisition section that acquires directional graph data expressing each of the plurality of events as a vertex and a restriction on the execution order between two of the plurality of events as a directional branch, an inverse chain partial set extraction section that traces the directional branch from each event in the forward direction to extract from the directional graph data an inverse partial set that is a combination of the events having such a relationship that any one of the events cannot be reached from the other events, and a parallel execution unit assignment section that assigns the plurality of events belonging to the inverse partial set to units different from each other in the parallel execution units.

Abstract: The invention includes a method and apparatus for dynamically defining and instantiating an undefined portion of a graph, where the graph has a plurality of states and a plurality of state transitions. A method includes executing the graph where the graph comprises a defined portion and an undefined portion and a plurality of tokens traverse the graph executing functions, suspending the one of the tokens in response to the one of the tokens detecting the undefined portion of the graph, generating a new portion of the graph for the undefined portion of the graph, replacing the undefined portion of the graph with the new portion of the graph, and releasing the suspended token. The new portion of the graph is generated by generating at least one definition file for the undefined portion of the graph and executing the at least one definition file to form thereby the new portion of the graph.

Abstract: A method and apparatus for identifying differences in runs of a computer program that are due to changes in the code of the computer program. With the apparatus and method, call trees are generated for two or more builds of a computer program. The apparatus and method perform a “tree-subtract” operation in which the two or more call trees generated during runs of two or more different builds of a computer program are subtracted from one another to identify build to build differences in the execution of the computer program. From the resulting tree, portions of the runs of the different builds of the computer program where the resource utilization of the computer program has not changed are easily identifiable. Moreover, portions of the runs of the different builds of the computer program where there are improvements or regressions in resource utilization of the computer program may be easily identifiable.

Abstract: A software tool is provided to analyze static source code. Source Code files are selected to define the project work space. A class and a method in the class are selected from said selected source code files. The tool generates a Call Tree as an ordered recursive sequence of all method calls in different classes or their instances that are invoked by said selected method in said selected class. A Sequence Diagram is generated from said Call Tree. The tool remembers all updates to the Call Tree used to generate the Sequence Diagram. This information is used when a generated Sequence Diagram is impacted due to changes made to any source code file included in the project.

Abstract: A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired.

Abstract: The adaptation precedence of an application (or order of adaptation of various components) is given as a directed acyclic graph (DAG), with each vertex being an atomic unit of adaptation, or a component which comprises of atomic units of adaptation. Each such component has an associated DAG specifying the order of adaptation with vertices as sub-components. Relations among sub-components and associated actions are stored as a table. The relations between sub-components of different components follow a set of constraints in order to be compatible relations. A linear order from the partial order is created as represented by the DAG and follows that order for adaptation of each component. Each component x is adapted atomically and then the table of relations is updated appropriately. As and when a component y is to be adapted, the table is looked-up and it is determined which relations and actions are to be enforced upon y while its adaptation is being executed.

Abstract: Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations.

Abstract: A computer implemented method, apparatus, and computer program product for compiling source code. The source code is scanned to identify a candidate region. A procedure control descriptor is corresponding to the candidate region is generated. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false. Also responsive to the determination, code is further generated to correctly select one of the first region and the second region at runtime.

Abstract: Described herein is an implementation for exposing an “execution context” to a logical execution flow of procedures as it executes. An “execution context” is a set of data and/or sub-procedures that might be useful at some point during a logical execution flow (to manage and control the execution flow and provide additional services to the execution flow) of computer-executable instructions though the often complex, intertwined, and interconnected conglomeration of procedures of software product(s).

Abstract: A method and system capable of creating UML protocol state machine for classes and interfaces of a software, by instrumenting the software to obtain a call graph comprising classes and interfaces and respective values associated with class variables and interface variables; identifying particular classes and interfaces in the call graph; identifying call patterns from the call graph to generate a protocol state machine.

Abstract: A method and system to optimize ordering of firmware modules. Optimizing the dispatch order of firmware modules reduces the boot time of a computer system. A plurality of module-to-module interfaces are collected from a plurality of firmware modules, wherein a module-to-module interface allows a first firmware module of the plurality of firmware modules to invoke a second firmware module of the plurality of firmware modules. A plurality of dependency expressions corresponding to the plurality of firmware modules are collected, wherein each dependency expression of a firmware module describes the module-to-module interfaces needed for execution of the firmware module. The plurality of firmware modules are sorted into an optimized order based on the plurality of dependency expressions and the plurality of module-to-module interfaces. In one embodiment, the plurality of firmware modules operate in accordance with an Extensible Firmware Interface (EFI) specification.

Abstract: Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. The code unit that includes those triggering read operations is modified so that the code unit branches to a prefetch predictor. The prefetch predictor observes sequence patterns of data sources of triggering read operations and develops prefetch predictions based on the observed data source sequence patterns. After a prefetch prediction gains reliability, the prefetch predictor supplies a predicted data source to a prefetcher coincident with triggering of runahead execution.

Abstract: Techniques for cross-module in-lining are disclosed. In an embodiment, in-lining is done in conjunction with a 3-phase compiler including a front-end phase, an IPA (Inter-Procedural Analysis) phase, and a back-end phase. The front-end phase processes the source code in various modules and provides the intermediate representations of such source code. The IPA phase determines whether a function should be in-lined, and, if so, provides in-line transformation instructions for the back-end phase to execute. The back-end phase executes the instructions provided by the IPA, which, in effect, transforms the in-lining code.

Abstract: An internal memory uses a resource identifier and an entry point to identify which functional program from an external memory is to be loaded into one of a plurality of overlay spaces established in the internal memory. In executing a program statement, the resource identifier identifies a corresponding functional program to perform a particular functional operation and the identified functional program is then loaded into an overlay space specified by the entry point. The functional program is then executed in the overlay space.