Abstract: A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Abstract: Dynamic optimization of application code is performed by selecting a portion of the application code as a possible transaction. A transaction has a property that when it is executed, it is either atomically committed or atomically aborted. Determining whether to convert the selected portion of the application code to a transaction includes determining whether to apply at least one of a group of code optimizations to the portion of the application code. If it is determined to apply at least one of the code optimizations of the group of optimizations to the portion of application code, then the optimization is applied to the portion of the code and the portion of the code is converted to a transaction.

Abstract: Various technologies and techniques facilitate stack read and write operations in a software transactional memory system. If the compiler determines that an address for a variable in a code segment is a stack location, the stack location is live on entry, and the address of the variable has not been taken and passed to another thread, the code is changed to ensure failure atomicity. One example includes modifying the code so a shadow copy is saved for local variables that are live on entry. If the same prior criteria are true except the stack location is not live on entry, the code is optimized by ensuring code for logging and software transactional memory operations are not included. If the compiler does not know the address is the stack location or that the address is not passed to another thread, the code is changed to ensure failure and concurrency atomicity.

Abstract: A computer program product and computer system for implementing a method of compiler optimisation of source code during compilation of the source code in a computer environment. The compiler optimisation of source code includes: recasting two algebraic expressions into a form of one or more token pairs arranged sequentially in a string, each token pair including an operator followed by an operand; reducing the strings in accordance with a set of predetermined simplifying rules; and comparing the reduced strings by matching to detect an equivalence of the two algebraic expressions.

Abstract: A modification to source code is applied in an automated manner to improve program performance while maintaining the meaning of an associated program. Source code is rewritten to improve the operation of the associated program. Prior to applying the source code optimization to the program, confirmation of approval by the programmer must be maintained. In one embodiment, the programmer is presented with numerical data pertaining to an improvement ratio associated with application of the source code optimization.

Abstract: A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.

Abstract: A method is disclosed that comprises modifying a method's byte code instructions for purposes of testing, debugging and/or monitoring. Additional byte code instructions are inserted into the method's byte code instructions at an entry point of the method and at an exit point of the method. The first additional byte code instruction causes a first output function to be executed for the method as a consequence of the entry point being reached during runtime. The second additional byte code instruction causes a second output function to be executed for the method as a consequence of the exit point being reached during runtime. The Application of the method to Distributed Statistical Record (DSR) keeping is also disclosed.

Abstract: A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.

Abstract: A compiler has the capability to selectively compile individual portions of a compilable code module for optimum execution performance or for serviceability. In one aspect, individual portions, such as procedures (being less than the entire module) are selectively optimized. In another aspect, debug activity data is used for determining whether or not to optimize compiled code. It is optionally possible to support one or more levels of partial selective optimization.

Abstract: In an embodiment, a method includes receiving a program code that includes a first calling function having a call instruction to call a first called function that passes, by reference, a variable as a parameter of a number of parameters. The method also includes compiling the program code to generate compiled instructions. The compiled instructions do not include a compiled instruction to load the variable onto a call stack, during execution, based on the call instruction.

Abstract: A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the binary to detect its critical code regions, and the dynamic partitioning module partitions the binary into critical and non-critical code regions, re-implements the critical code regions in the configurable logic, and then transforms the binary so that it accesses the configurable logic rather than execute the critical code regions.

Abstract: The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one of true and false. An evaluation of true results in a unique identifier being pushed into a predefined area of storage. This unique identifier is associated with the instructions executed as a result of an evaluation of true.

Abstract: The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N) of the same hardware model, and facilities and signals of different instantiations are resolved by instantiation-specific name space specifications in a code switch (24,26). Thus, computing time is saved because by simulating the meta model, the processor resources, for instance, storage spaces, are utilized more efficiently.

Abstract: A system is disclosed for accessing information about an object, where such information is available at the time of creation of the object but not necessarily available at all times later. In one embodiment, existing object code is modified to add the ability to access the information. The modified code is then executed.

Abstract: Intercepting function calls. In one embodiment of the application, an import address table for an application is accessed and an address, in the import address table, associated with a function to which calls from the application are to be intercepted is replaced with an address to be used to access a proxy function. In another embodiment, the application is loaded in debugging mode. Once the import address table for the application has been populated with addresses for functions called by the application, the execution of the application is paused. An address, in the import address table, associated with a function to which calls from the application are to be intercepted is replaced with an address to be used to access a proxy function. Execution of the application is then resumed.

Abstract: Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be made that causes the conditional branch instruction to trigger, or execute, when an opposite condition is true. A method is directed to producing a binary-level conditional branch reversal within a binary program on a computer architecture that supports a predicated execution. The method includes obtaining a predicate expression representing a condition that influences a direction of program flow of the binary-level conditional branch to be reversed, determining a binary-level transformation that causes the binary-level conditional branch to be triggered when an opposite condition is true, and modifying the binary-level conditional branch with the determined binary-level transformation, wherein the binary-level conditional branch is reversed.

Abstract: Method and apparatus to make code more difficult to reverse engineer is described. Inert instructions are inserted between instructions within a program. The inert instructions may perform logic operations with the net effect of not changing an argument. Furthermore, the inserted inert instructions may be repositioned within the program to further obfuscate the desired function of the program, making the code more difficult to reverse engineer.

Abstract: A method for enabling COBOL programs for asynchronous and distributed processing is provided. The distributed processing method includes providing a technical layer for use by a COBOL program, the technical layer enabling a distributed processing module. The method includes providing a COBOL program and employing, by the COBOL program, the distributed processing module to enable the COBOL program to perform distributed processing. The COBOL program and the technical layer operate in the same runtime environment. A method for enabling COBOL programs for asynchronous processing is also provided. The method includes providing a technical layer for use by a COBOL program, the technical layer enabling an asynchronous processing module. The method includes providing a COBOL program and employing, by the COBOL program, the asynchronous processing module to enable the COBOL program to perform asynchronous processing. The COBOL program and the technical layer operating in the same runtime environment.

Abstract: An embodiment of the present invention provides an optimizer for optimizing source code to generate optimized source code having instructions for instructing a central processing unit (CPU) to iteratively compute values for a primary recurrence element. A computer programmed loop for computing the primary recurrence element and subsequent recurrence elements is an example of a case involving iteratively computing the primary recurrence element. The CPU is operatively coupled to fast operating memory (FOM) and operatively coupled to slow operating memory (SOM). SOM stores the generated optimized source code. The optimized source code includes instructions for instructing said CPU to store a computed value of the primary recurrence element in a storage location of FOM. The instructions also includes instructions to consign the computed value of the primary recurrence element from the storage location to another storage location of the FOM.

Abstract: A code region forming part of a computer program is modified during execution of the computer program by a plurality of threads. In one aspect, identical modification instructions are provided to each thread for modifying a site in the code region having a desirable idempotent atomic modification, and the modification instructions direct each thread to make the desirable idempotent atomic modification. In another aspect, a thread is selected to modify the code region, each thread other than the selected thread is directed to execute an alternative execution path that generates output identical to the output of the code region after the code region has been modified, and, responsive to directing each thread other than the selected thread, the selected thread is directed to modify the code region.

Abstract: An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple sub-graphs of a DDG) which are independent, and substantially identical. The improvement in instruction scheduling and reduction of hot spots is achieved by evenly distributing such groups of instructions around the schedule for a given loop.

Abstract: A method of converting an original code sequence to a modified code sequence where the original code sequence includes a procedure call that is prior to a load instruction to one of a first plurality of registers is provided. The method includes inserting the load instruction into the modified code sequence and inserting the procedure call into the modified code sequence subsequent to the load instruction. The method further includes inserting an advanced load instruction to one of a second plurality of registers into the modified code sequence prior to the procedure call and inserting a checking instruction associated with the advanced load instruction into the modified code sequence subsequent to the procedure call.

Abstract: The present invention includes a native language verification method for verifying native language information associated with an emulation class. Verification information associated with native language code is obtained. The native language code is referred to by an emulation language class. The legitimacy of the verification information is examined to confirm the native language is uncorrupted.

Abstract: A grid-enabled ANT system that includes ANT XML task files that can run on both grid-enabled machines or stand-alone computers is disclosed. A network file server is used to store files accessed during the build process, and ANT's standard XML tagging and parameters are used, thus enabling the user to use a standardized format for entering XML information. This grid-enabled ANT is transparent to the user since ANT parses the tasks and automatically sends jobs to the grid, when appropriate, instead of the user deciding which tasks to implement as grid tasks.

Abstract: Methods and apparatus for preserving precise exceptions in code reordering by using control speculation are disclosed. A disclosed system uses a control speculation module to reorder instructions within an application program and preserve precise exceptions. Instructions, excepting and non-excepting, can be reordered by the control speculation module if the instructions meet certain conditions. When an excepting instruction is reordered, a check instruction is inserted into the program execution path and a recovery block is generated. The check instruction determines if the reordered excepting instruction actually needs to generate an exception. The recovery block contains instructions to revert the effects of code reordering. If the check instruction detects the need for an exception, the recovery block is executed to restore the architectural state of the processor and the exception is handled.

Abstract: A method for improving program performance including reordering a global data area of a program and for each load instruction referencing global variables within range of the immediate part of an add immediate instruction from a TOC anchor, replacing the load instruction with an add immediate instruction. The method may further include placing a TOC at the top, or within a predetermined distance from the top, of the global data area. The method may also include placing the global variables after the TOC, wherein more frequently referenced global variable are closer to the TOC than less frequently referenced global variables. Also, the method may further include placing in run-time order, groups of the global variables that frequently follow each other in run-time.

Abstract: An apparatus, program product and method utilize a heuristic-based algorithm such as simulated annealing to order program code segments in a computer memory to provide improved computer performance in terms of memory access, e.g., by minimizing cache misses or other memory-related performance penalties that may be present in a multi-level memory architecture. Program code is ordered in a computer memory by selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm, and ordering the plurality of program code segments in a memory of a computer using the selected ordering.

Abstract: Historically, resources (e.g., dynamic link libraries) were organized based on factors including the expertise of development teams. Unfortunately, this creates shared resources of much greater functionality than required by any one client application. By reformulating shared resources according to nodes reachable by classified applications, reformulated resources reduce the over-inclusive nature of shared resources formed based on the expertise of development teams. Further, layering resources for lower order classified applications also reduces memory requirements.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: A method of preparing an executable program from a plurality of object code modules, at least one of said object code modules including section data specifying a plurality of functions associated with relocation instructions, at least some of which functions are called in the executable program. The method comprises the steps of assigning an attribute to each function, said attribute being capable of providing an indication of whether the function is reachable, reading the section data and relocation instructions to ascertain if the function is called and setting the attribute to indicate the called status and preparing the executable program to only include functions with an indicated called status of reachable. A linker is provided for preparing the executable program from object code modules containing the relocation instructions. A computer program is provided to control the linker.

Abstract: A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the return address after any IL call to a subroutine at a target entry address P, the corresponding OL return address is stored in an array at a location determined by an index calculated as a function of P. After completion of execution of the OL translation of the IL subroutine, execution is transferred to the address stored in the array at the location where the OL return address was previously stored. A confirm instruction block is included in each OL call site to determine whether the transfer was to the correct or incorrect call site, and a back-up routine is included to handle the cases of incorrect call sites.

Abstract: A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present invention to count the number of times a branch is taken when branch instructions are executed. Branch count statistics generated from the hardware counters are available to a program in order to analyze whether code reorganization is necessary. If reorganization is necessary, the program autonomically reorganizes instructions locally at run time to allow more instructions to be executed prior to taking a branch, so that the number of branches taken is minimized without modifying underlying program code.

Abstract: Source code is compiled using a multi-stage compiler that includes a tokenizer, a type checker, and a composer. The tokenizer segments source code into a sequence of tagged segments. The source code includes at least one instruction that composes a first abstraction and a second abstraction with a selected composition operator. The parser builds a tree using the sequence of tagged segments. The type checker performs a first pass of the tree to determine whether abstractions on the tree are well typed. The composer reduces the at least one instruction composing the first and the second abstractions on the tree to a third abstraction. The composer substitutes the first and the second abstractions on the tree with the third abstraction, wherein the type checker performs a second pass of the tree to determine whether the third abstraction is well typed.

Abstract: The present invention provides methods, apparatus, and systems to remove a redundant, sign extension instruction from a program and to improve the execution efficiency of the program. In an example embodiment, a conversion program for controlling a computer for the conversion of an execution program, especially a compiler, permits the computer to perform: a function for analyzing a sign extension instruction issued in order to perform the sign extension of a value defined in the execution program; and a function for, in accordance with analysis results, removing a predetermined sign extension instruction from those included in the execution program.

Abstract: Methods and systems are provided for adapting software applications for download and execution on a variety of different mobile devices which employ different Application Execution Environments. An Application Download Protocol for transferring applications to mobile devices is also provided. Mobile devices can be matched with compatible applications according to functionality required by the applications and functionality provided by the mobile devices. Applications submitted by developers can be automatically matched to application categories, thus facilitating user selection of applications. Data used by applications running on mobile devices can be remotely managed by application developers, allowing developers to remotely control the type and presentation of data on mobile devices without the need for data management servlets to be provided by the developers.

Abstract: The present disclosure relates to whole program analysis and, more particularly, short data optimization obtained through whole program analysis. In one embodiment, short data optimization is achieved by analyzing the program to estimate the size of existing short data and the size of any linkage tables, providing the size estimates to a compiler that is to compile the program, and compiling the program with the compiler in view of the size estimates such that a relatively large amount of data is allocated to a short data area.

Abstract: The method and apparatus for compiling high level code is described. A method may be utilized that may include integrating the allocation of registers, scheduling instructions, and selecting code functions to produce an intermediate representation of a high level code segment with scheduled instructions. Additionally, a modular conflict handler may be utilized to resolve register and/or scheduler conflicts as may be required or useful in compiling the high level code. Also, a modular transformation interface may be utilized to invoke analyzers as may be required or useful to generate a compiled version of the high level code.

Abstract: The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention, a parallel processor program for defining a processor integrated circuit includes a plurality of processor commands with addresses. The plurality of processor commands may includes a starting processor command, and each of the plurality of processor commands includes one or more subcommands. When the processor integrated circuit executes the parallel processor program, the processor integrated circuit executes the staring processor command first and then executes the rest of the plurality of processor commands based on an order of the addresses.

Abstract: A system and method to reduce the size of source code in a processing system are described. Multiple subgraph structures are identified within a graph structure constructed for multiple source code instructions in a program. Unifiable variables that are not simultaneously used in the source code instructions are identified within each subgraph structure. Finally, one or more unifiable instructions from a tine of a corresponding subgraph structure are transferred to a handle of the corresponding subgraph structure, each unifiable instruction containing one or more unifiable variables.

Abstract: Improving performance of a computer program is disclosed. A first set of escape data is gathered. A first compiled program is provided using the first set of escape data. A second set of escape data is gathered based on the first compiled program. A second compiled program is provided using the second set of escape data. The second compiled program is more optimized than the first compiled program.

Abstract: An improved method is provided for performing register allocation in a compiler. This method determines the allocation of a plurality R of registers of a processor for use during the execution of a software program. The register allocation process is treated as a graph-coloring problem, such that an interference graph is constructed for the software program, the graph is simplified, and an R-coloring the interference graph to the extent possible is attempted. Then, spill code is inserted in the software program each for each uncolored node of the graph, a new interference graph is constructed, and the process is repeated. During the simplification process, nodes with degree greater than or equal to R are removed from the graph in an order dictated by a spill cost metric. During the coloring process, these same nodes are reinserted in the graph in an order dictated by reapplying the spill cost metric.

Abstract: One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data references to be prefetched. This analysis can involve: using a two-phase marking process in which blocks that are certain to execute are considered before other blocks; and analyzing complex array subscripts. Next, the system inserts prefetch instructions into the code in advance of the identified data references. This insertion can involve: dealing with non-constant or unknown stride values; moving prefetch instructions into preceding basic blocks; and issuing multiple prefetches for the same data reference.

Abstract: Comparison indices each for two components incorporated in a source program are used for easy and quantitative evaluation of functional redundancy in the program, effective and accurate extraction of redundant code segments from the program and also effective and accurate extraction of components to be modified simultaneously. A tree T is entered and an initial level of functional redundancy m(P) is set at 0 in a program P expressed by the tree T. The top node of the tree T is selected as a node N. A specific computation is performed for the top node selected as the node N with attribute information including the similarity and the number of children of the node N to obtain a level ?. The level ? is added to the functional redundancy m(P). The specific computation is performed for every node in the tree T, to obtain functional redundancy m(P) including the total of ? for all nodes.

Abstract: A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a main loop structure having indexing expressions based on the original loop structure is included. The indexing expressions included in the main loop preferably cannot produce an underflow or an overflow. Also included in the range check elimination loop structure is a post-loop structure based on the original loop structure that is capable of testing indexing expressions for overflow.

Abstract: An optimizing apparatus includes a data item extraction unit, a layout unit, an unused data item extraction unit, a merge determination unit, and a data item merge unit. The data item extraction unit extracts data items from a program. The layout unit lays out the extracted data item in memory. The unused data item extraction unit extracts defined but unused data items from the extracted data items. The merge determination unit determines based on the layout result whether or not a plurality of unused data items forming a data item having a hierarchical structure can be merged into a new data item. The data item merge unit merges the plurality of data items into a data item based on the determination result.

Abstract: A method and a system for constructing a control flow graph (CFG, 106) from an executable computer program (104). The solution detects data intermixed with instructions and instruction set changes. The method includes the steps of defining block leader types specifying basic block boundaries in the program (104), building a CFG structure (106) according to the basic blocks found in the program, and adding control flow and addressing information to the CFG (106) by propagating through the basic blocks and internals thereof. The CFG (106) may be then optimised (108) and a compacted executable (112) created as a result.

Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.

Abstract: Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be made that causes the conditional branch instruction to trigger, or execute, when an opposite condition is true. A method is directed to producing a binary-level conditional branch reversal within a binary program on a computer architecture that supports a predicated execution. The method includes obtaining a predicate expression representing a condition that influences a direction of program flow of the binary-level conditional branch to be reversed, determining a binary-level transformation that causes the binary-level conditional branch to be triggered when an opposite condition is true, and modifying the binary-level conditional branch with the determined binary-level transformation, wherein the binary-level conditional branch is reversed.

Abstract: A resource-constrained device such as a smart card or the like includes memory for storing an application software program comprising an object-oriented, verifiable, platform-independent, type-safe and pointer-safe sequence of instructions. The device can also include a virtual machine implemented on a microprocessor where the virtual machine is capable of executing the sequence of instructions. Each instruction includes an operation code, and each data manipulation instruction is specific to a particular data type. The application program can be stored on a computer-readable medium prior to being received by the resource-constrained device. Methods of using such an application program, including accessing the program over the Internet and downloading it to a smart card, also are disclosed.

Abstract: A method and system for compiling a program written in a type-safe language. Instructions are reordered for speculative execution while reducing the execution time of the program. A dependency graph is generated wherein exception dependent arcs are discriminated from arcs of other dependency types. Determination is made whether earliest execution start time of the H-PEI will be earlier when executed with or without a constraint by the exception dependent arc. If it is determined that it will be earlier in the latter case, the instruction sequence including the H-PEI is reordered for speculative execution.