Abstract: Exemplary embodiments of the present invention comprise an algorithm described herein that utilizes a technique to shrink a set of potentially reachable elements to a close approximation of the actually reachable elements within a software application by closely approximating how the application executes at runtime. The algorithm attempts to identify all of the reachable elements of an object-oriented software application by starting with the entry points into the application and thereafter progressively determining all of the software elements within the application that are reachable. The algorithm instantiates application objects in the same way they would be instantiated at runtime and passes references to these objects from one method and field to the next; emulating as closely as possible object instantiation performed by the application at runtime.

Abstract: A “kill” intrinsic that may be used in programs for designating specific data objects as having been “killed” by a preceding action is provided. The concept of a data object being “killed” is that the compiler is informed that no operations (e.g., loads and stores) on that data object, or its aliases, can be moved across the point in the program flow where the data object is designated as having been “killed.” The “kill” intrinsic limits the reordering capability of an optimization scheduler of a compiler with regard to operations performed on “killed” data objects. The “kill” intrinsic may be used with direct memory access (DMA) operations. Data objects being DMA'ed from a local store of a processor may be “killed” through use of the “kill” intrinsic prior to submitting the DMA request. Data objects being DMA'ed to the local store of the processor may be “killed” after verifying the transfer completes.

Abstract: A computer program consisting of a compiler for compiling source code programs into executable code. The compiler is suited to achieving high efficiency on a processor that can process many instructions at once but the instructions have dependency constraints and the processor has no internal mechanism for dealing with these constraints, such as the Itanium class of processors. As each instruction is considered for addition to a group of instructions for a single cycle, dependencies are checked to determine whether the entire group can be scheduled in any possible order. Once all the instructions of the group have been selected, the instructions are then reordered for placement in a reservation table. For implementation in the Itanium class of processors, detailed requirements of the processor are accommodated with a structure that can be adjusted for any processor in the class. The structure can also be adjusted for other classes of processors.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A method of a fast system call is provided. First, a logical operation to compute a kernel service routine is used. Then the logical operation result is compared with ciphertext from a key register. At least one input for the logical operation is from the relevant information of the required kernel service routine. For example, the start address of the kernel service routine or the content of the start address of the kernel service routine, or combinations thereof. If the logical operation result equals to the ciphertext of the key register, a switch from a user mode to a kernel mode to read the kernel service routine is allowed. Otherwise, the central processing system executes a corresponding exceptional handler routine. Then the operating system terminates the mode switch request and reports an error to the operating system.

Abstract: A method for transforming access to a structure array, that includes compiling source code, wherein compiling the source code includes identifying the structure array in the source code, performing an object safety analysis to determine whether the structure array is safe for transformation, wherein the object safety analysis includes an inter-procedural alias class analysis, performing a profitability analysis on the structure array when the structure array is safe for transformation, wherein the profitability analysis includes selecting a transformation from a plurality of transformations, wherein the plurality of transformations includes a pointer based fully splitting transformation, a pointer based partially splitting transformation, and an address based fully splitting transformation, and performing the selected transformation on the structure array, and storing the compiled code.

Abstract: In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code is prevented and all accesses to the fields of that object are performed using transactional code. In one embodiment, the current visibility of an object is stored in the object itself. This stored visibility can be checked at runtime by code that accesses the object fields or code can be generated to check the visibility prior to access during compilation.

Abstract: A method for operating a binary executable in which some of the data or code is to be protected includes the step of pruning the binary executable of the code andor data to be protected. Nonfunctional code is substituted for the code pruned from the binary executable, to form a pruned executable which does not contain the code to be protected. The code pruned from the binary executable is loaded into a code injection service or program (CIS). The binary executable is placed in memory as with any application. Invoking the pruned executable alone results in crash. The CIS is made part of the operating system service, and is loaded into RAM when the computer starts. When the pruned executable is invoked, the CIS detects its presence, and as the pruned executable runs, the CIS substitutes the actual data or code into the pruned executable, whereby it operates normally.

Abstract: An obfuscation evaluation method which sufficiently evaluates an obfuscation performed on a program. The obfuscation evaluation method includes: a step of executing an obfuscated code module produced by obfuscating an original code module of a program, and generating a trace output file by logging a result of the execution; and a step of identifying the degree of obfuscation of the obfuscated code module by evaluating the trace output file.

Abstract: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

Abstract: A mechanism is provided for performing scalar operations using a SIMD data parallel execution unit. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.

Abstract: A computer implemented method, computer usable program code, and a system for parallelizing a loop. A parameter that will be used to limit parallelization of the loop is identified to limit parallelization of the loop. The parameter specifies a minimum number of loop iterations that a thread should execute. The parameter can be adjusted based on a parallel performance factor. A parallel performance factor is a factor that influences the performance of parallel code. A number of threads from a plurality of threads is selected for processing iterations of the loop based on the parameter. The number of threads is selected prior to execution of the first iteration of the loop.

Abstract: Repetitive synchronization in program code is optimized through lock coarsening that is performed subject to a number of constraints. Using a forward pass over the program code followed by a backward pass, region extent bits may be determined that identify the points in the program where object locking can be coarsened. The program code may then be modified to realize coarsened locking regions determined based on the region extent bits. Alternatively, previously determined value numbers may provide much of the information collected by the two passes. In such a case, a single pass over the program code may locate features that limit lock coarsening opportunities. A set of synchronization operations that can be removed may then be determined and used when modifying the program code to coarsen locking regions.

Abstract: Methods, computer program products, and system for generating code for an extract, transform, and load (ETL) data flow are provided. In one implementation, the method includes receiving an ETL data flow representing a logical transformation and flow of data, placing a staging table at a pre-determined location in the ETL data flow to reduce a total number of staging tables required by the transformation, and generating code for the transformation based on the ETL data flow including the staging table placed at the pre-determined location.

Abstract: A software transactional memory system is described which utilizes decomposed software transactional memory instructions as well as runtime optimizations to achieve efficient performance. The decomposed instructions allow a compiler with knowledge of the instruction semantics to perform optimizations which would be unavailable on traditional software transactional memory systems. Additionally, high-level software transactional memory optimizations are performed such as code movement around procedure calls, addition of operations to provide strong atomicity, removal of unnecessary read-to-update upgrades, and removal of operations for newly-allocated objects. During execution, multi-use header words for objects are extended to provide for per-object housekeeping, as well as fast snapshots which illustrate changes to objects. Additionally, entries to software transactional memory logs are filtered using an associative table during execution, preventing needless writes to the logs.

Abstract: A technique is provided for eliminating maximum and minimum expressions within loop bounds are provided. A loop in a code is identified. The loop is determined to meet conditions, which require an upper loop bound and a lower loop bound to contain maximum and minimum expressions, loop-invariant operands, a predetermined size for a code size, and a total number of instructions to be greater than a predetermined constant. A profitability of loop versioning is determined based on a performance gain of a fast version of the loop, a probability of executing the fast version of the loop at runtime, and an overhead for performing loop versioning. A pair of lower loop bound and upper loop bound values resulting in a constant number is identified. A loop iteration value is checked to be a non-zero constant. Branches are identified, and loop versioning is performed to generate a versioned loop.

Abstract: A system that reduces overly optimistic program execution. During operation, the system encounters a bounded-execution block while executing a program, wherein the bounded execution block includes a primary path and a secondary path. Next, the system executes the bounded execution block. After executing the bounded execution block, the system determines whether executing instructions on the primary path is preferable to executing instructions on the secondary path based on information gathered while executing the bounded-execution block. If not, the system dynamically modifies the instructions of the bounded-execution block so that during subsequent passes through the bounded-execution block, the instructions on the secondary path are executed instead of the instructions on the primary path.

Abstract: A computer implemented method, apparatus, and computer program product for obtaining aliasing information for a target variable in a computer program. A control flow graph representing the computer program is partitioned into an taken address portion that includes all reachable nodes in which an address of the target variable is taken and an untaken address portion that includes all other reachable nodes. All references to the target variable are replaced with a temporary variable in the untaken address portion. The target variable is initialized with the value from the temporary variable at each intermediary node in a set of intermediary nodes in the taken address portion. An intermediary node is a node at which an address of a target variable is taken. The aliasing information for the target variable is generated using the modified computer program.

Abstract: Data processing delay is reduced during data processing, using compiler optimization. Blocks of code are scanned in an order from blocks recurring most often to blocks recurring least often. In an order from blocks recurring most often to block recurring least often, shifts are inserted before arithmetic references, such that a previous use of the arithmetic reference does not require a shift, shifts are inserted after each memory use such that the next use of the memory does not require a shift, and shifts are inserted after each arithmetic reference such that the next use of the arithmetic reference requires no shift. In addition, if there is a mismatch between the last shifted amount of any one block and the required initial shifted amount in any of its successors, shifts are inserted to make up for the mismatch.

Abstract: A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous stream of memory is disclosed. A preferred embodiment identifies groups of isomorphic statements within a loop body where the isomorphic statements operate over a contiguous stream of memory over the iteration of the loop. Those identified statements are then converted into virtual-length vector operations. Next, the hardware's available vector length is used to determine a number of virtual-length vectors to aggregate into a single vector operation for each iteration of the loop. Finally, the aggregated, vectorized loop code is converted into SIMD operations.

Abstract: The present invention provides a probe system and method for multithreaded user-space programs. The system includes an instrumentation module that enables single stepping out of line processing for multithreaded programs, an establish probepoint module that divides up an area of the probed program's memory into a plurality of instruction slots, an ensure slot assigned module that ensures that an instruction slot is assigned to a probepoint, a slot acquisition module that acquires the instruction slot for the probepoint, stealing a slot from another probepoint as needed, and a free slot module that relinquishes the instruction slot owned by the probepoint when the probepoint is being unregistered.

Abstract: A method and apparatus for reducing a memory footprint of an embedded system. The method may include analyzing packages installed in a root file system of the embedded system, and determining which package components are not required for the operation of the embedded system. The method further includes reducing a memory footprint of the embedded system based on the above determination.

Abstract: APIs are provided, that are external to a programming language but that provide functionality that can be plugged into a language compiler. The provided APIs tailor functionality associated with asynchronous programming, iterators or writing symmetric co-routines using a generalized pattern-based approach. Several types of resumable methods are provided in the APIs which can be applied to method bodies written in traditional program code. Syntactically distinguishable control points in method bodies written in traditional program code invoke transformation of the code by the compiler using the external APIs. The transformed code enables the pausing and resumption of the code sandwiched between control points in the transformed code. The source code contained within a method having control points in it is transformed so that code within the method can be executed in discrete parts, each part starting and ending at a control point in the transformed code.

Abstract: Core commands and aggregations of such commands are provided to programmers to enable them to generate programs that can be parallel-processed without requiring the programmer to be aware of parallel-processing techniques. The core commands and aggregations abstract mechanisms that can be executed in parallel, enabling the programmer to focus on higher-level concepts. The core commands provided include commands for applying a function in parallel and distributing and joining data in parallel. The output of each core command can implement an interface that can enable underlying mechanisms to stitch together multiple core commands in a cohesive manner to perform more complex actions.

Abstract: A control flow graph may be generated from a model. The control flow graph may be restructured by converting at least one unstructured region of a control flow graph into a structured region. The restructuring may include locating at least one block between two merge nodes in the control flow graph, moving the located block to a different section of the control flow graph, and creating the structured region by surrounding the moved code block with a test of a guard variable.

Abstract: A method for providing parallel processing capabilities including: performing scalar and array privatization analysis via a compiler; checking whether an assignment statement is reducible; recognizing reduction patterns through a pattern matching algorithm; classifying a reduction type of each of the reduction patterns; and performing transformations and code generation for each reduction the reduction type of each of the reduction patterns.

Abstract: The present invention provides for a system for computer program functional partitioning for heterogeneous multi-processing systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A whole program representation is generated based on received computer program code. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one node-specific SESE region is identified based on identified SESE regions and the at least one system parameter. Each node-specific SESE region is grouped into a node-specific subroutine. Each node-specific subroutine is compiled based on a specified node characteristic. The computer program code is modified based on the node-specific subroutines and the modified computer program code is compiled.

Abstract: Critical sections used for multiple threads in a parallel program to access shared resource may be selected to merge with each other to reduce the number of signals/tokens used to create critical sections. Critical section merge may be based on a summarized dependence graph which is obtained from an instruction level dependence graph constructed based on a result of critical section minimization.

Abstract: The present invention provides for a system for computer program code size partitioning for multiple memory multi-processor systems. At least one system parameter of a computer system comprising one or more disparate processing nodes is identified. Computer program code comprising a program to be run on the computer system is received. A program representation based on received computer program code is generated. At least one single-entry-single-exit (SESE) region is identified based on the whole program representation. At least one SESE region of less than a certain size (store-size-specific) is identified based on identified SESE regions and the at least one system parameter. Each store-size-specific SESE region is grouped into a node-specific subroutine. The non node-specific parts of the computer program code are modified based on the partitioning into node-specific subroutines. The modified computer program code including each node-specific subroutine is compiled based on a specified node characteristic.

Abstract: Method, apparatus, and computer readable medium for restructuring a software program hierarchy having interface files and implementation files that include the interface files are described. In one example, dependencies between program units in the interface files and the implementation files are determined. The dependencies are represented as a plurality of bit strings. Correlated bitstrings of the plurality of bit strings are clustered into a plurality of partitions. Each of the plurality of partitions is transformed into corresponding program units. New interface files are respectively created having the corresponding program units for each of the plurality of partitions.

Abstract: Parallelization of loops is performed for loops having indirect loop index variables and embedded conditional statements in the loop body. Loops having any finite number of array variables in the loop body, and any finite number of indirect loop index variables can be parallelized. There are two particular limitations of the described techniques: (i) that there are no cross-iteration dependencies in the loop other than through the indirect loop index variables; and (ii) that the loop index variables (either direct or indirect) are not redefined in the loop body.

Abstract: A method and system for improving debug information pertaining to user variables using a compiler. The method may include identifying a statement to be removed from its current position in an internal representation of a program by a compiler as part of the compiler optimization, replacing the statement to be removed with a debug annotation, adding references to the debug annotation in subsequent debug expressions referring to the removed statement, and emitting debug location information for a user variable using the debug annotation.

Abstract: Various technologies and techniques are disclosed for transforming a sequential loop into a parallel loop for use with a transactional memory system. Open ended and/or closed ended sequential loops can be transformed to parallel loops. For example, a section of code containing an original sequential loop is analyzed to determine a fixed number of iterations for the original sequential loop. The original sequential loop is transformed into a parallel loop that can generate transactions in an amount up to the fixed number of iterations. As another example, an open ended sequential loop can be transformed into a parallel loop that generates a separate transaction containing a respective work item for each iteration of a speculation pipeline. The parallel loop is then executed using the transactional memory system, with at least some of the separate transactions being executed on different threads.

Abstract: One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

Abstract: A computer implemented method, computer usable program code, and a data processing system for selecting a candidate implementation of a virtual overridden method for inlining into a calling method. A determination as to which implementation of a virtual overridden method to inline is made based on its relative “hotness” compared to the other implementations of the same method. The relative hotness can be inferred from the invocation count and sampling count that the virtual machine and the just-in-time compiler already collect for other purposes, that is, without collecting and storing of call-edge profiling information. When a method is being compiled and it is identified that the method contains a call to an overridden method, a candidate for inlining from among the implementations of the overridden method is selected based on relative hotness values. The candidate implementation of the overridden method is then inlined, with a guard, into the calling method.

Abstract: A mechanism is provided for managing the referencing of at least two versions of a function. A first version is a single threaded version that does not ensure multi-thread safety. A second version is a multi threaded version that does ensure multi-thread safety. The mechanism determines whether a set of executable code (e.g. a program) is currently executing in single-threaded mode or multi-threaded mode. If the executable code is executing in single-threaded mode, then the mechanism causes the executable code to reference the first version of the function. If the executable code is executing in multi-threaded mode, then the mechanism causes the executable code to reference the second version of the function. By doing so, the mechanism ensures that the additional overhead of ensuring multi-thread safety is incurred only when it is needed. In this manner, the mechanism makes execution of the function more optimal.

Abstract: A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.

Abstract: Performing scalar operations using a SIMD data parallel execution unit is provided. With the mechanisms of the illustrative embodiments, scalar operations in application code are identified that may be executed using vector operations in a SIMD data parallel execution unit. The scalar operations are converted, such as by a static or dynamic compiler, into one or more vector load instructions and one or more vector computation instructions. In addition, control words may be generated to adjust the alignment of the scalar values for the scalar operation within the vector registers to which these scalar values are loaded using the vector load instructions. The alignment amounts for adjusting the scalar values within the vector registers may be statically or dynamically determined.

Abstract: It has been discovered that a control transfer table can be structured to reduce the overhead resulting from its use (e.g., misses from accessing the control transfer table). Entries of a control transfer table (e.g., a jump table or a procedure linkage table) can be organized in accordance with their respective use frequencies, as well as other parameters. For example, entries can be organized in a manner that would group the most frequently used entries, thus facilitating their contemporaneous availability in a memory (e.g., cache). The use frequencies may be determined from profile information for a code that references the control transfer table.

Abstract: The present invention includes program storing unit 11 for storing a program, parsing/dependence-information generating unit 12 for generating dependence information and a syntax tree for a program, dependence-information storing unit 13 for storing dependence information, syntax-tree storing unit 14 for storing a syntax tree, dependence-information tracking unit 17 for extracting interface information on a program fragment according to specifying-information specifying the program fragment and extracting a part of a program fragment associated with interface information according to selection information for selecting the interface information, and information input/output unit 15 for passing specifying-information and selection information to dependence-information tracking unit 17 and outputting interface information and a part of a program fragment passed from dependence-information tracking unit 17.

Abstract: Generally, piping applications defined by combining stages of programming with a sequence control program and specifying to the sequence control program piping commands. The stages may be functions to send data to a shared queue. The piping commands identify current stages, and parameters for the current stages identify the queue and a key for the data to be sent to the queue. The piping commands do not identify preceding and/or subsequent piping applications.

Abstract: Embodiments described herein disclose the use of a compiler pre-processing component for the optimization of a firmware image so that it can be made to take up less space in a memory device without the use of compression. Embodiments identify repeated modules or common components across previously separate binary firmware modules within a body of software and automatically and seamlessly merge the content of these modules so they occupy less space in their binary form. The overhead footprint of the binary is reduced without modifying the pre-existing source code defining the individual components. In general, the resulting space savings is additive to the savings provided by existing compression savings techniques.

Abstract: Methods for optimizing a region of an application program are described. A delinquent region of the application program is identified based on a data utilization parameter. The delinquent region is optimized by creating an optimized structure type associated with the delinquent region. The optimized structure type includes one or more data fields selected based on delinquent region profile information.

Abstract: The present invention provides a method and system for optimization of an intermediate representation in a graphical modeling environment. A first intermediate representation is provided. At least one optimization technique is applied to the first intermediate representation. A second intermediate representation is generated responsive to the application of the at least one optimization technique to the first intermediate representation.

Abstract: Embodiments of the present invention include code generation methods. In one embodiment, a table of patterns is generated. Each pattern in the table includes an FMA (fused multiply-add) DAG (Directed Acyclic Graph), a canonical form equivalent of the FMA DAG, and a shape corresponding to the canonical form equivalent. Incoming floating-point expressions are matched against the patterns in the table during compilation of a program to obtain optical sequences of FMA, FMS (fused multiply-subtract), and FNMA (fused negate multiply-add) instructions as compiled instructions for computing the floating point expressions.

Abstract: A method of determining ranges for algorithmic variables for a processor that uses fixed point arithmetic is provided. The method comprises expressing overflow requirements of processor instructions as inequalities. The method also expresses precision requirements and expressiveness requirements as inequalities and merit functions. A global constraint and optimizer tool is used to find ranges for algorithmic variables based on the inequalities and the merit functions. The use of constraint equation solving and optimization finds optimal algorithmic ranges that provide overflow-free arithmetic as well as optimal expressiveness and precision.

Abstract: A method, computer program product, and system for memory optimization by partitioning extraneous information from executable virtual machine code or interpreted code. The extraneous information may be stored separately, or accessed from the original code if needed for debugging or servicing the code in the field. This approach optimizes memory usage by reducing memory footprint while maintaining accessibility of the non-executable information for debugging and other processes necessary for servicing code in the field.

Abstract: A computer-implemented method, computer program product and data processing system to improve runtime performance of executable program code when executed on the data-processing system. During execution, data is collected and analyzed to identify runtime behavior of the program code. Heuristic models are applied to select region(s) of the program code where application of a performance improvement algorithm is expected to improve runtime performance. Each selected region is recompiled using selected performance improvement algorithm(s) for that region to generate corresponding recompiled region(s), and the program code is modified to replace invocations of each selected region with invocations of the corresponding recompiled region. Alternatively or additionally, the program code may be recompiled to be adapted to characteristics of the execution environment of the data processing system.

Abstract: The method and system for data speculation of multicore systems are disclosed. In one embodiment, a method includes dynamically determining whether a current speculative load instruction and an associated store instruction have same memory addresses in an application thread in compiled code running on a main core using a dynamic helper thread running on a idle core substantially before encountering the current speculative load instruction. The instruction sequence associated with the current speculative load instruction is then edited by the dynamic helper thread based on the outcome of the determination so that the current speculative load instruction becomes a non-speculative load instruction.

Abstract: A generalized on-line solution for achieving transparent binary optimization using pre-existing profiling facilities and virtual memory remapping of text regions. An optimization environment is initialized which comprises a debugger program, a profiling facility, and an optimizer. A running target program is attached to the debugger program, wherein the debugger program monitors process execution of the target program. Responsive to monitoring the running target program, profile data of the running target program is collected using the profiling facility. The profile data is provided to the optimizer, wherein the optimizer analyzes the profile data and existing code of the running target program. Responsive to a determination to optimize the existing code based on the profile data, optimized code is generated for the running target program. The optimized code is provided to the debugger program, wherein the debugger program inserts the optimized code into a virtual address space of the running target program.