Abstract: In general, in one aspect, the disclosure describes a method of determining if a first query for data related to a protocol data unit in a first table is a query to a table merged into a combination table formed from multiple tables. If so, the method can generate a second query for the first query for data stored by the combination table.

Abstract: A system and method to perform post pass optimizations in a dynamic compiling environment. A dynamic compiler emits machine code. Responsive to the emission of the machine code a post pass processor creates an abstract representation of the code from the dynamic compiler. Data flow analysis is then conducted on the abstract representation. Redundant instructions in the machine code are identified and eliminated as a result of the data flow analysis.

Abstract: A method for compiler optimization particularly well suited to object-oriented language that permit dynamic class loading. The method permits the compiler optimization of code associated with a potentially polymorphic object that is a call parameter to a virtual procedure where the procedure is a candidate for devirtualization through inlining. The method includes steps for guarded devirtualizing of the procedure, insertion of code to ensure privatization of the object before the procedure is executed, creation of a guard assumptions associated with the object and application of known optimization techniques to the code associated with the object.

Abstract: A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.

Abstract: A method and system customize and thus extend a fixed mapping between a computer program code language and a code-model notation. Given a fixed mapping, the invention method and system define customization points in the mapping based on known/predefined relatively over rigid points. For each customization point, there is a respective mapping key that enables a piece of the computer program code to be derived from a corresponding piece of the code-model, and vice versa. The code-model reflects the customizable perspective, and contents of the code-model can be tailored to elide implementation details.

Abstract: An optimization method that optimizes programs is disclosed. A pattern for multiple instructions is used to replace one of a plurality of partial programs with a replacement set of instructions. The partial program to be optimized is detected within a first set of instructions. The first set of instructions is transformed in the one of the plurality of partial programs and is replaced with the replacement set of instructions.

Abstract: A system and method are presented that persist assembly bind information for applications at each stage of execution of the assembly policy. New assembly bind history files are created and persisted to disc when changes in assembly bind policy results in a change in the assemblies with which the application binds. This persisted information is used to reconfigure assembly binds to a prior state when operation of the application conformed to a user's desires. Since this assembly bind reconfiguration is on a per application basis, only the binding of the selected application is affected. Likewise, the assembly bind history files are associated with a particular user to allow personalized execution of applications on a system.

Abstract: A code placement technique that organizes code units to at least reduce layout conflicts among caller/callee code units. A code preparation environment determines those code units of a code representation that have overlapping memory mappings with their counterpart caller/callee code units. To at least reduce the layout conflicts, or overlapping memory mappings, the code preparation environment arranges the caller/callee code units to eliminate the layout conflicts among the caller/callee code units.

Abstract: Selected regions of native instructions translated in a DBT environment from non-native instructions are compressed based on the independent compression of different fields of selected instructions using compression tables to reduce a length of selected fields. The regions of compressed instructions are stored and de-compressed into the native instructions during subsequent execution using de-compression tables. Specifically, for native instructions of a selected region, selected types of opcodes and/or operands may be compressed independently. The types may be selected by profiling the opcodes using benchmark programs and creating an opcode conversion table prior to compression, and scanning of the operands and creating an operand conversion table during compression of the opcodes.

Abstract: A method that allows the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task that needs to be split up into shorter SMIs, a new task context stack is created in memory. From that point forward, the SMI handler uses the task context, leaving the original stack unchanged. When the time limit for a single SMI is about to be reached, the CPU is directed back to the original stack, and the task context stack persists in memory and retains the context of the task in hand. The soft SMI exits with a return code or other indication to signify that a new SMI should be invoked to continue processing. The driver or other software that caused the first soft SMI then invokes another, passing in a code or other indication to signify that this is a continuation of a previously started task. On entering the SMI handler for the second time, the handler notes the request for continuation, switches back to the saved task context stack and continues processing where it left off.

Abstract: A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a “if” conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

Abstract: Linear transformations of statements in code are performed to generate linear expressions associated with the statements. Parallel code is generated using the linear expressions. Generating the parallel code includes splitting the computation-space of the statements into intervals and generating parallel code for the intervals.

Abstract: Modification of source code reduces a launch time associated with an application program so that the application program more quickly responds to input from a user after startup. One technique of modifying source code includes converting globally defined variables in the source code to local static variables associated with respective newly created functions. Inclusion of the globally defined variables in the source code impacts application launch time because a compiler creates initialization code associated with the globally defined variables that must be run at launch time to initialize the variables in case they are used by functions in the application program. On the other hand, local static variables are initialized when the function that contains them is first called. Thus, use of local static variables in respective newly created functions in lieu of globally defined variables reduce application program launch time.

Abstract: A linker profiler tool facilitates maintenance and management of object ordering between releases of firmware. By maintaining object ordering, code differences between firmware builds are reduced, which reduces the size of a package of update information used to update an electronic device from one version of firmware to another. Information used by an object code linker in a firmware build activity is processed to minimize changes in code object ordering between builds. The impact on the size of the update information caused by updates to firmware/software component in the build is thereby reduced to a minimum.

Abstract: An apparatus for optimizing a transaction comprising an initial sequence of computer operations, the apparatus includes a processing unit which identifies one or more idempotent operations comprised within the initial sequence, and which reorders the initial sequence to form a reordered sequence comprising a first sub-sequence of the computer operations followed by a second sub-sequence of the computer operations, the second sub-sequence comprising only the one or more idempotent operations.

Abstract: Embodiments of the present invention provide for platform independence, low intrusiveness, and optimal memory usage of the binary instrumentation process by means of employing one procedure (interceptor function) implemented in a high-level programming language to intercept an arbitrary number of functions or blocks of code. Each time a function or code block needs to be intercepted a new copy of the procedure from a provided memory region may be associated with the address of the function or block of code by means of a memory region descriptor and an intercepted function address table. Once activated, the interceptor function may retrieve its current address and, by searching memory region descriptors, determine the region the current address belongs to; the region's base address may then be obtained. A reference to the intercepted function address table may be fetched from the region descriptor; and an index to the intercepted function address table may be computed.

Abstract: A method for optimizing executable code includes identifying a plurality of instructions in the executable code matching a predetermined instruction pattern, assessing whether the binary number conforms to a predetermined bit pattern, and transforming the plurality of instructions into transformed instructions when the binary number conforms to the bit pattern.

Abstract: Disclosed herein are systems, methods, and computer readable-media for obfuscating code through conditional expansion obfuscation. The method includes identifying a conditional expression in a computer program, identifying a sequence of conditional expressions that is semantically equivalent to the conditional expression, and replacing the conditional expression with the semantically equivalent sequence of conditional expressions. One option replaces each like conditional expression in the computer program with a diverse set of sequences of semantically equivalent conditional expressions. A second option rearranges computer instructions that are to be processed after the sequence of conditional expression is evaluated so that a portion of the instructions is performed before the entire sequence of conditional expressions is evaluated. A third option performs conditional expansion obfuscation of a conditional statement in combination with branch extraction obfuscation.

Abstract: The efficient use of type descriptors with frozen objects. A frozen object might actually include several type descriptors, a primary type descriptor that is canonical according to a set of canonicalization rules, and an auxiliary type descriptor that is not identical to the primary type descriptor. The auxiliary type descriptor may be used to access the canonical type descriptor. When performing an operation, if the auxiliary type descriptor can be used to perform the operation, then that auxiliary type descriptor may be used. If the canonical type descriptor is to be used to perform the operation, the auxiliary type descriptor is used to gain access to the canonical primary type descriptor. The primary type descriptor is then used to perform the operation.

Abstract: Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.

Abstract: A technique for accessing a shared resource of a computerized system involves running a first portion of a first thread within the computerized system, the first portion (i) requesting a lock on the shared resource and (ii) directing the computerized system to make operations of a second thread visible in a correct order. The technique further involves making operations of the second thread visible in the correct order in response to the first portion of the first thread running within the computerized system, and running a second portion of the first thread within the computerized system to determine whether the first thread has obtained the lock on the shared resource. Such a technique alleviates the need for using a MEMBAR instruction in the second thread.

Abstract: A dynamic race detection system is provided that detects race conditions in code that executes concurrently in a computer system. The dynamic race detection system uses a modified software transactional memory (STM) system to detect race conditions. A compiler converts portions of the code that are not configured to operate with the STM system into pseudo STM code that operates with the STM system. The dynamic race detection system detects race conditions in response to either a pseudo STM transaction in the pseudo STM code failing to validate when executed or an actual STM transaction failing to validate when executed because of conflict with a concurrent pseudo STM transaction.

Abstract: A method of verifying properties of a source program includes creating a directed multigraph from the source program. The directed multigraph is then minimized by identifying removable vertices in the multigraph. Based on the minimization of the directed multigraph, the source program is transformed by inlining variables in the source program to produce a transformed program. The transformed program is then model checked using a model checking tool in order to verify properties of the source program.

Abstract: A method and apparatus for improving parallelism through optimal code replication is herein described. An optimal replication factor for code is determined based on costs associated with a plurality of replication factors. The code is replicated by the optimal replication factor, and then the code is potentially executed in parallel to obtain parallelized efficient execution.

Abstract: An intrusion-resistant mechanism based on restricted code segments and code individualization is able to thwart significant amounts of known and unknown low-level attacks that inject invalid code, in the form of false data or instructions for execution by a victim application, by varying the locations of code-containing segments within a memory space corresponding to an application.

Abstract: A system, method for modifying insurance transaction processing software are provided. A library of code packets may be stored in a database. One or more code packets may implement at least one business requirement of an insurance organization. If the organization changes one of the business requirements or develops a new business requirement, a user may modify an insurance transaction processing program to reflect the change via a rules engine. The rules engine may be operable to generate program code assembly instructions based on user input. The assembly instructions may be used by a code assembler to form program code for an insurance transaction processing program software module. The insurance transaction processing program may be changed by adding a formed software module.

Abstract: A compiler that forms an intermediate representation of a program using a flow graph with less than all possible edges used to model asynchronous transfers within the program. The flow graph is formed in multiple phases. In one phase, the flow graph is formed without modeling asynchronous transfers. In later phases, representations of the effects of the asynchronous transfers are selectively added. As part of the later phases, edges modeling a possible asynchronous transfer are added to the flow graph following definitions in protected regions of variables that are live outside the protected region. A modified definition of live-ness of a variable is used to incorporate use of the variable in any region, including the protected region, following an asynchronous transfer. Edges from the protected region are also added to the model if the only use of the defined variable is in a handler.

Abstract: A method to optimize speculative parallel thread execution comprises selecting a plurality of partition candidate pairs for speculative parallel thread execution, transforming each partition candidate pair of the plurality of partition candidate pairs to improve the expected performance gain of each pair, and selecting a set of one or more transformed partition candidate pairs that do not interfere with each other and produce a maximum expected performance gain.

Abstract: In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache.

Abstract: A dependence graph having a linear number of edges and one or more tie vertices is generated by constructing a tree of nodes, receiving requests to create cut and/or fan vertices corresponding to each node, adjusting a frontier of nodes up or down, and creating one or more cut or fan vertices, zero or more tie vertices, and at least one predecessor edge.

Abstract: A method address storage table information, a class information and a function reference information are extracted from an intermediate code and analyzed. When any method determined in execution is not overridden in one of classes by the other class, method address storage tables of the respective classes are deleted and a method address storage table that can be commonly used in the both classes is generated. Then, method address storage table pointers of the both classes are renewed to a leading address value of the generated method address storage table that can be commonly used in the both classes. As described, the method address storage tables redundantly generated in the different classes are deleted so that an object code size can be reduced.

Abstract: A method and an apparatus take software source code to synthesize a hardware platform for running the software. The method determines which processor is suitable for running the code and meeting the performance parameters determined by the user. The method also determines which hardware devices are accessed by software. If the hardware target is a semiconductor chip, the invention selects the appropriate IP and creates an HDL description of the chip. If the hardware target is a printed circuit board, the invention creates a schematic or netlist that includes the appropriate microprocessor, the various semiconductor chips, and the necessary interconnections.

Abstract: The program to be executed is compiled by translating it into native instructions of the instruction-set architecture of the processor system, organizing the instructions deriving from the translation of the program into respective bundles in an order of successive bundles, each bundle grouping together instructions adapted to be executed in parallel by the processor system. The bundles of instructions are ordered into respective sub-bundles, said sub-bundles identifying a first set of instructions, which must be executed before the instructions belonging to the next bundle of said order, and a second set of instructions, which can be executed both before and in parallel with respect to the instructions belonging to said subsequent bundle of said order.

Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.

Abstract: A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. The method includes parallelizing the candidate code, in response to determining said profitability meets a predetermined criteria; and generating object code corresponding to the source code. The generated object code includes both a non-parallelized version of the candidate code and a parallelized version of the candidate code. During execution of the object code, a dynamic selection between execution of the non-parallelized version of the candidate code and the parallelized version of the candidate code is made. Changing execution from said parallelized version of the candidate code to the non-parallelized version of the candidate code, may be in response to determining a transaction failure count meets a pre-determined threshold.

Abstract: Intermediate code is executable on a virtual machine. Hence, source code that is compiled on a first computing device can be distributed to a second computing device in an intermediate form as long as the second computing device has the appropriate virtual machine. In this way, the compilation can be done without regard to the underlying native processor on the second computing device. However, the intermediate code loses the original type information defined in the source code. By determining the variable types in the intermediate code, the intermediate code can be converted to a different intermediate language.

Abstract: An example apparatus and method described herein involves determining if a class object has been dynamically loaded, performing an escape analysis on the program code and determining if assumptions made during an initial escape analysis are valid. Additionally, the example apparatus and method restore synchronization to at least a portion of the program code affected by loading of the class object if the assumptions made during the initial escape analysis are no longer valid.

Abstract: Embodiments of the present invention provide a method, apparatus and system which may include splitting a dependency chain into a set of reduced-width dependency chains; mapping one or more dependency chains onto one or more clustered dependency chain processors, wherein an issue-width of one or more of the clusters is adapted to accommodate a size of the dependency chains; and/or processing in parallel a plurality of dependency chains of a trace. Other embodiments are described and claimed.

Abstract: A compiling method for compiling software which is adapted to output an intermediate result at a given timing, the compiling method includes extracting, by a computer, a process block related to parallel processing and conditional branch from a processing sequence included in a source code of a software which is processed time-sequentially, and generating, by the computer, an execution code by restructuring the process block that is extracted.

Abstract: Managed code, including applications, runtime, and driver, have a priori knowledge of the client's exact hardware configuration, just as the JIT compiler has a priori knowledge of the microprocessor type on the target computer system. At compile time, the compiler knows the effective version various system drivers, so that the compiler can emit an executable tuned for a particular driver version and target system.

Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words of a line being combined into a line of compressed words; and constituting an addressing table localizing each of the lines of compressed words in a block of lines compressed words and comprising one input per group of lines of compressed words, each input (j) specifying the position of a first line of compressed words in the block, and the respective lengths of the lines of compressed words of group, except for a last line of compressed words of the group, whereof the length is determined by means of the position of a first line of compressed words of a following group.

Abstract: The data sharing apparatus in the present invention includes a first processor and a second processor, each of a different endianness, that are both connected to the memory via the data bus, in a byte order based on the endianness of the first processor. It also includes an address conversion unit which converts at least one lower bit of an address to indicate a reversed position of data in the data bus, and outputs the converted address to the memory, in the case where the second processor performs a memory access on the shared memory for data with a smaller width than the data bus.

Abstract: Methods and systems are provided for automatically generating code from a graphical model representing a design to be implemented on components of a target computational hardware device. During the automatic code generating process, a memory mapping is automatically determined and generated to provide an optimization of execution of the program on the target device. The optimized memory mapping is incorporated into building the program executable from the automatically generated code of the graphical model.

Abstract: A high level shader language compiler incorporates transforms to optimize shader code for graphics processing hardware. An instruction reordering transform determines instruction encapsulations of dependent instructions that reduce concurrent register usage by the shader. A phase pulling transform re-organizes the shader's instructions into phases that reduce a measure of depth of texture loads. A register assigning transform assigns registers to lower register usage by the shader.

Abstract: We present a technique to perform dependence analysis on more complex array subscripts than the linear form of the enclosing loop indices. For such complex array subscripts, we decouple the original iteration space and the dependence test iteration space and link them through index-association functions. The dependence analysis is performed in the dependence test iteration space to determine whether the dependence exists in the original iteration space. The dependence distance in the original iteration space is determined by the distance in the dependence test iteration space and the property of index-association functions. For certain non-linear expressions, we show how to transform it to a set of linear expressions equivalently. The latter can be used in dependence test with traditional techniques. We also show how our advanced dependence analysis technique can help parallelize some otherwise hard-to-parallelize loops.

Abstract: A program may be partitioned into at least two stages, where at least one of the stages comprises more than one parallel thread. Data required by each of the stages, which data is defined in a previous stage may be identified. Transmission of the required data between consecutive stages may then be provided for.

Abstract: This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in the same fetch packet. In the prior architecture 32-bit instructions may not span a 32-bit boundary. The 16-bit instruction set is implemented with a special fetch packet header that signals whether the fetch packet includes some 16-bit instructions. This fetch packet header also has special bits that tell the hardware how to interpret a particular 16-bit instruction. These bits essentially allow overlays on the whole or part of the 16-bit instruction space. This makes the opcode space larger permitting more instructions than with a pure 16-bit opcode space.

Abstract: A method, system and apparatus for preserving platform independence of a program while supporting native accelerators for performance critical program objects. In a method for preserving platform independence of a program while supporting native accelerators for performance critical program objects, the method can include identifying a reference to a program object in a platform independent computer program and determining if a platform specific implementation of the program object has been separately stored in addition to a platform independent implementation of the program object. If it can be determined that a platform specific implementation of the program object has been separately stored in addition to a platform independent implementation of the program object, the platform specific implementation of the program object can be loaded in lieu of the platform independent implementation.

Abstract: A compiler optimizing conversion of a character coding system for a character stored in a string variable in a target program to be optimized has a conversion instruction generation section which generates a conversion instruction to convert a character from a first character coding system to a second character coding system and to store the converted character in the string variable, the conversion instruction being generated before each of a plurality of procedures by which the character in the string variable written in the first character coding system is read out and is used in the second character coding system, and a conversion instruction removal section which removes each of conversion instructions generated by the conversion instruction generation section if a character in the second character coding system is stored in the string variable in each of the execution paths executed before the conversion instruction.

Abstract: A system and method for reorganizing source code using frequency based instruction loop replication are provided. Code is reorganized based on the frequency of execution of blocks of the code so as to favor frequently executed blocks of code over rarely executed code with regard to subsequent optimizations. Frequently executed blocks of instructions are maintained within loop/switch statements and rarely executed blocks of instructions are removed from the loop/switch statements. The rarely executed blocks of instructions may be replicated after the loop/switch statement with a reference back to the loop/switch statement. In this way, when subsequent loop/switch statement optimizations are applied, the frequently executed blocks of instructions within the loop are more likely to benefit from such optimizations since the negative influence of the rarely executed blocks of instructions has been removed.