Spintronics Or Quantum Computing Patents (Class 977/933)
  • Patent number: 8816479
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: August 26, 2014
    Assignees: National Research Council of Canada, The Governors of The University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 8811073
    Abstract: A magnetic device includes a reference layer, the magnetization direction of which is fixed, and a storage layer, the magnetization direction of which is variable. In a write mode, the magnetization direction of the storage layer is changed so as to store a “1” or a “0” in the storage layer. In a reading mode, the resistance of the magnetic device is measured so as to know what is stored in the storage layer. The magnetic device also includes a control layer, the magnetization direction of which is variable. The magnetization direction of the control layer is controlled so as to increase the effectiveness of the spin-transfer torque in the event writing to the storage layer is desired, and to decrease the effectiveness of the spin-transfer torque in the event reading the information contained in the storage layer, without modifying the information, is desired.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 19, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Bernard Dieny
  • Patent number: 8797621
    Abstract: Disclosed herein are atom phase-controlled double rephasing-based quantum memory and a double-rephased photon echo method therefor. The atom phase-controlled double rephasing-based quantum memory includes an optical medium and an optical pulse generation unit. The optical medium has three energy levels (|1>, |2> and |3>), receives one or more optical pulses from an optical pulse generation unit, and generates output light that satisfies phase matching conditions. The optical pulse generation unit generates at least five optical pulses that resonate among the energy levels of the optical medium.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: August 5, 2014
    Assignees: INHA Industry Partnership Institute, Gwangju Institute of Science and Technology
    Inventor: Byoung Seung Ham
  • Patent number: 8792271
    Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirofumi Morise, Hideaki Fukuzawa, Akira Kikitsu, Yoshiaki Fukuzumi
  • Patent number: 8750035
    Abstract: There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The storing of the information is performed by inverting the magnetization of the memory layer by using a spin torque magnetization inversion occurring according to a current flowing in the lamination direction of a layered structure having the memory layer, the intermediate layer, and the magnetization-fixed layer, the memory layer includes an alloy region containing at least one of Fe and Co, and a magnitude of an effective diamagnetic field which the memory layer receives during magnetization inversion thereof is smaller than the saturated magnetization amount of the memory layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: June 10, 2014
    Assignee: Sony Corporation
    Inventors: Kazuhiro Bessho, Masanori Hosomi, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8750036
    Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 10, 2014
    Assignee: Seagate Technology, LLC
    Inventors: Xiaohua Lou, Haiwen Xi
  • Patent number: 8750030
    Abstract: According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Ueda, Tadashi Kai, Toshihiko Nagase, Katsuya Nishiyama, Eiji Kitagawa, Tadaomi Daibou, Makoto Nagamine, Hiroaki Yoda
  • Publication number: 20140151770
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Publication number: 20140151771
    Abstract: A method for depositing a material on a graphene layer includes arranging a graphene layer having an exposed substantially planar surface proximate to a magnetron assembly that is operative to emit a plasma plume substantially along a first line, wherein the exposed planar surface of the graphene layer is arranged at an angle that is non-orthogonal to the first line where the first line intersects the exposed planar surface; and emitting the plasma plume from the magnetron assembly such that a layer of deposition material is disposed on the graphene layer without appreciably damaging the graphene layer.
    Type: Application
    Filed: August 13, 2013
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Ching-Tzu Chen, Marcin J. Gajek, Simone Raoux
  • Publication number: 20140151620
    Abstract: A method for fabricating a spintronic cell includes forming a cavity in a substrate, forming a wire in the cavity, depositing a spacer layer over exposed portions of the substrate and the conductive field line, depositing a layer of conductive material on a portion of the spacer layer, removing portions of the layer of conductive material to define a conductive strap portion, wherein the conductive strap portion has a first distal region a second distal region and a medial region arranged therebetween, wherein the medial region has a cross sectional area that is less than a cross sectional area of the first distal region and a cross sectional area of the second distal region, and forming an spintronic device stack on the conductive strap portion above the conductive field line.
    Type: Application
    Filed: August 6, 2013
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: David W. Abraham, Philip L. Trouilloud, Daniel C. Worledge
  • Publication number: 20140153327
    Abstract: A spin transport channel includes a dielectric layer contacting a conductive layer. The dielectric layer includes at least one of a tantalum oxide, hafnium oxide, titanium oxide, and nickel oxide. An intermediate spin layer contacts the dielectric layer. The intermediate spin layer includes at least one of copper and silver. The conductive layer is more electrochemically inert than the intermediate spin layer. A polarizer layer contacts the intermediate spin layer. The polarizer layer includes one of a nickel-iron based material, iron, and cobalt based material. The conductive layer and intermediate layer are disposed on opposite sides of the dielectric layer. The dielectric layer and the polarizer layer are disposed on opposite sides of the intermediate spin layer. The intermediate spin layer is arranged to form a conducting path through the dielectric layer configured to transport a plurality of electrons. Each of the plurality of electrons maintains a polarized electron spin.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: The National Institute of Standards and Technology Government of the United States of America, as Re
    Inventor: The National Institute of Standards and Technology, Government of the United States of America, as R
  • Publication number: 20140133001
    Abstract: A method and device for optimal processing of a plurality of sets of coherent states of lights. The method includes: receiving a light having a coherent state; splitting the coherent state into a plurality of identical states (slices), each a coherent state with lower intensity than that of the received coherent state; transferring the information of each of the identical coherent states into a qubit; compressing the quantum information of the qubit into a quantum memory; and quantum processing the quantum information from the quantum memory.
    Type: Application
    Filed: October 5, 2012
    Publication date: May 15, 2014
    Applicant: RAYTHEON BBN TECHNOLOGIES CORP.
    Inventor: RAYTHEON BBN TECHNOLOGIES CORP.
  • Patent number: 8724376
    Abstract: An antiferromagnetic nanostructure according to one embodiment includes an array of at least two antiferromagnetically coupled magnetic atoms having at least two magnetic states that are stable for at least one picosecond even in the absence of interaction with an external structure, the array having a net magnetic moment of zero or about zero, wherein the array has 100 atoms or less along a longest dimension thereof. An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero; two or more stable magnetic states; and having an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Donald M. Eigler, Andreas J. Heinrich, Sebastian Loth, Christopher P. Lutz
  • Patent number: 8717812
    Abstract: The present disclosure concerns a magnetic memory element suitable for a thermally-assisted switching write operation, comprising a current line in electrical communication with one end of a magnetic tunnel junction, the magnetic tunnel junction comprising: a first ferromagnetic layer having a fixed magnetization; a second ferromagnetic layer having a magnetization that can be freely aligned at a predetermined high temperature threshold; and a tunnel barrier provided between the first and second ferromagnetic layer; the current line being adapted to pass a heating current through the magnetic tunnel junction during the write operation; wherein said magnetic tunnel junction further comprises at least one heating element being adapted to generate heat when the heating current is passed through the magnetic tunnel junction; and a thermal barrier in series with said at least one heating element, said thermal barrier being adapted to confine the heat generated by said at least one heating element within the magnet
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 6, 2014
    Assignee: Crocus Technology SA
    Inventors: Kenneth Mackay, Ioan Lucian Prejbeanu
  • Publication number: 20140118024
    Abstract: Systems and methods are provided for generating a high-fidelity Toffoli state from a plurality of low-fidelity single qubit magic states. First and second qubits are prepared in a high-fidelity initial state. N target qubits are prepared in the single qubit magic state. A series of gates are performed on the qubits, such that the system is in a state ½|0001 . . . 0N+½|0101 . . . 0N+|½|1001 . . . 0N+½|1111 . . . 1N. A parity check is performed on the N target qubits. The parity check provides at least a first measurement value. The first qubit, the second qubit, and the first target qubit are accepted as the Toffoli state if the measurement values assume the desired values.
    Type: Application
    Filed: February 12, 2013
    Publication date: May 1, 2014
    Inventor: BRYAN K. EASTIN
  • Patent number: 8693239
    Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein the memory layer has a lamination structure of a Co—Fe—B layer and an element belonging to any one of 1A group, 2A group, 3A group, 5A group, or 6A group, an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed with respect to the memory layer, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Sony Corporation
    Inventors: Masanori Hosomi, Kazuhiro Bessho, Hiroyuki Ohmori, Yutaka Higo, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8687413
    Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 1, 2014
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Haiwen Xi, Dimitar V. Dimitrov, Dexin Wang
  • Patent number: 8681542
    Abstract: A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past both ends of the free layer. The magnetic memory device further includes a switching element connected to a second surface of the free layer. Another magnetic memory device includes: a first reference layer having a first magnetic domain wall; a second reference layer having a second magnetic domain wall; and a memory structure between the first and second reference layers. The memory structure includes: a first free layer adjacent to the first reference layer; a second free layer adjacent to the second reference layer; and a switching element between the first and second free layers.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-jun Hwang
  • Patent number: 8675401
    Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: March 18, 2014
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Kang Yong Kim, Dimitar V. Dimitrov, Henry F. Huang
  • Patent number: 8675400
    Abstract: According to one embodiment, a magnetic memory includes a magnetoresistive element includes a first reference layer, a first nonmagnetic layer, a recording layer, a second nonmagnetic layer, and a second reference layer which are sequentially stacked, the recording layer being connected to a terminal to which a high-level voltage is applied, a magnetization direction of the recording layer being variable, magnetization directions of the first and second reference layers being invariable and antiparallel, a first selection transistor connected between a first bit line and the first reference layer, and constituted of an N-channel MOSFET, a second selection transistor connected between a second bit line and the second reference layer, and constituted of an N-channel MOSFET, and a word line connected to gates of the first and second selection transistors.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Katayama
  • Patent number: 8665638
    Abstract: Systems and method for reading/sensing data stored in magnetoresistive random access memory (MRAM) cells using magnetically annealed reference cells. A MRAM includes a reference circuit comprising at least one magnetic storage cell, wherein each magnetic storage cell in the MRAM is programmed to the same state. The reference circuit includes a load element coupled to the magnetic storage cell, wherein the load element is configured to establish a reference voltage during a read operation.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Hari M. Rao, Xiaochun Zhu
  • Publication number: 20140050475
    Abstract: Computing bus devices that enable quantum information to be coherently transferred between topological and conventional qubits are disclosed. A concrete realization of such a topological quantum bus acting between a topological qubit in a Majorana wire network and a conventional semiconductor double quantum dot qubit is described. The disclosed device measures the joint (fermion) parity of the two different qubits by using the Aharonov-Casher effect in conjunction with an ancillary superconducting flux qubit that facilitates the measurement. Such a parity measurement, together with the ability to apply Hadamard gates to the two qubits, allows for the production of states in which the topological and conventional qubits are maximally entangled, and for teleporting quantum states between the topological and conventional quantum systems.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 20, 2014
    Applicant: Microsoft Corporation
    Inventors: Parsa Bonderson, Roman M. Lutchyn
  • Patent number: 8654577
    Abstract: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
    Type: Grant
    Filed: May 4, 2013
    Date of Patent: February 18, 2014
    Assignees: MagIC Technologies, Inc., International Business Machines Corporation
    Inventors: Hsu-Kai Yang, Yutaka Nakamura, John Debrosse
  • Patent number: 8638587
    Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: John K. De Brosse, William J. Gallagher, Yu Lu
  • Patent number: 8630112
    Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: January 14, 2014
    Assignee: Crocus Technology SA
    Inventor: Bertrand Cambou
  • Patent number: 8625342
    Abstract: A storage element includes: a storage layer which retains information by a magnetization state of a magnetic substance; a magnetization pinned layer having magnetization which is used as the basis of the information stored in the storage layer; and an interlayer of a non-magnetic substance provided between the storage layer and the magnetization pinned layer. The storage element is configured to store information by reversing magnetization of the storage layer using spin torque magnetization reversal generated by a current passing in a laminate direction of a layer structure including the storage layer, the interlayer, and the magnetization pinned layer, and when the saturation magnetization of the storage layer and the thickness thereof are represented by Ms (emu/cc) and t (nm), respectively, (1489/Ms)?0.593<t<(6820/Ms)?1.55 holds.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: January 7, 2014
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Tetsuya Asayama, Kazutaka Yamane, Hiroyuki Uchida
  • Patent number: 8625341
    Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: January 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: William H. Xia
  • Patent number: 8620855
    Abstract: A method for changing qubit encoding for implementation of a quantum computational gate is disclosed. Such a method may include providing first and second qubits encoded in a plurality of non-abelian anyons according to a first encoding scheme. The first encoding scheme may not be suitable for implementing a certain topologically protected quantum computational gate, such as an entangling gate, for example. Successive topological charge measurements may be performed on at least a subset of the anyons until the qubits are encoded according to a second encoding scheme. The second encoding scheme may be different from the first encoding scheme, and may be suitable for implementing the gate.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: December 31, 2013
    Assignee: Microsoft Corporation
    Inventor: Parsa Bonderson
  • Patent number: 8611147
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 17, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall, Yiming Huai
  • Patent number: 8611139
    Abstract: There is disclosed a memory element including a layered structure including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer; and an insulating layer provided between the memory layer. An electron that is spin-polarized is injected in a lamination direction of a layered structure, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, in regard to the insulating layer that comes into contact with the memory layer, and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film, and the memory layer includes at least one of non-magnetic metal and oxide in addition to a Co—Fe—B magnetic layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: December 17, 2013
    Assignee: Sony Corporation
    Inventors: Kazutaka Yamane, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Hiroyuki Uchida
  • Publication number: 20130308956
    Abstract: A method and system for transferring data comprising : an entangled photon source for producing first and second entangled photons associated with a receiver and a sender, respectively; a Bell state measurement device for performing a joint Bell state measurement on the second entangled photon and the at least one qubit; the Bell state measurement device outputting two bits of data to be used at the receiver; a transmission channel for transmitting two bits from the outcome of the Bell state measurement device to the receiver; a unitary transformation device for performing a unitary transformation operation on the first entangled photon based upon the value of the two bits of data; at least one detector for detecting encoded information from the first entangled photon; at least one processor operating to determine whether or not to transmit portions of data from a sequential successive qubit based upon the preceding qubit.
    Type: Application
    Filed: July 23, 2013
    Publication date: November 21, 2013
    Inventors: Ronald E. Meyers, Keith S. Deacon
  • Patent number: 8537588
    Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: John K. De Brosse, William J. Gallagher, Yu Lu
  • Patent number: 8531876
    Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: September 10, 2013
    Assignee: Seagate Technology LLC
    Inventors: Xiaohua Lou, Haiwen Xi
  • Patent number: 8520433
    Abstract: A magnetoresistive element according to an embodiment includes a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, at least one of the first magnetic layer and the second magnetic layer including a magnetic film of MnxAlyGez (10 atm %?x?44 atm %, 10 atm %?y?65 atm %, 10 atm %?z?80 atm %, x+y+z=100 atm %).
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: August 27, 2013
    Assignees: Kabushiki Kaisha Toshiba, Tohoku University
    Inventors: Yushi Kato, Tadaomi Daibou, Eiji Kitagawa, Takahide Kubota, Shigemi Mizukami, Terunobu Miyazaki
  • Patent number: 8514618
    Abstract: The present disclosure concerns a magnetic random access memory MRAM cell comprising a tunnel magnetic junction formed from a first ferromagnetic layer, a second ferromagnetic layer having a second magnetization that can be oriented relative to an anisotropy axis of the second ferromagnetic layer at a predetermined high temperature threshold, and a tunnel barrier; a first current line extending along a first direction and in communication with the magnetic tunnel junction; the first current line being configured to provide an magnetic field for orienting the second magnetization when carrying a field current; wherein the MRAM cell is configured with respect to the first current line such that when providing the magnetic field, at least a component of the magnetic field is substantially perpendicular to said anisotropy axis. The MRAM cell has an improved switching efficiency, lower power consumption and improved dispersion of the switching field compared to conventional MRAM cells.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 20, 2013
    Assignee: Crocus-Technology SA
    Inventors: Lucien Lombard, Ioan Lucian Prejbeanu
  • Patent number: 8514619
    Abstract: A magnetic memory device includes: a free layer for storing information; and a reference layer disposed on a first surface of the free layer. The reference layer includes at least two magnetic domains and a magnetic domain wall between the at least two magnetic domains. The reference layer extends past both ends of the free layer. The magnetic memory device further includes a switching element connected to a second surface of the free layer. Another magnetic memory device includes: a first reference layer having a first magnetic domain wall; a second reference layer having a second magnetic domain wall; and a memory structure between the first and second reference layers. The memory structure includes: a first free layer adjacent to the first reference layer; a second free layer adjacent to the second reference layer; and a switching element between the first and second free layers.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: August 20, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-jun Hwang
  • Patent number: 8503225
    Abstract: Method for writing and reading more than two data bits to a MRAM cell comprising a magnetic tunnel junction formed from a read magnetic layer having a read magnetization, and a storage layer comprising a first storage ferromagnetic layer having a first storage magnetization, a second storage ferromagnetic layer having a second storage magnetization; the method comprising: heating the magnetic tunnel junction above a high temperature threshold; and orienting the first storage magnetization at an angle with respect to the second storage magnetization such that the magnetic tunnel junction reaches a resistance state level determined by the orientation of the first storage magnetization relative to that of the read magnetization. The method allows for storing at least four distinct state levels in the MRAM cell using only one current line to generate a writing field.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: August 6, 2013
    Assignee: Crocus-Technology SA
    Inventors: Lucien Lombard, Ioan Lucian Prejbeanu
  • Patent number: 8503223
    Abstract: In a memory, the MTJ elements respectively have a first end electrically connected to any one of a source and a drain of one of the cell transistors. First bit lines each of which is electrically connected to the other one of the source and the drain of one of the cell transistors. Second bit lines each of which is electrically connected to a second end of one of the MTJ elements. Word lines each of which is electrically connected to a gate of one of the cell transistors or functions as a gate of one of the cell transistors. A plurality of the second bit lines correspond to one of the first bit lines. A plurality of the MTJ elements share the same word line and the same active area. The active area is continuously formed in an extending direction of the first and second bit lines.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Susumu Shuto
  • Patent number: 8498149
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: July 30, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8498148
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 30, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8498150
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: July 30, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8493777
    Abstract: A non-volatile current-switching magnetic memory element includes a bottom electrode, a pinning layer formed on top of the bottom electrode, and a fixed layer formed on top of the pinning layer. The non-volatile current-switching magnetic memory element further includes a tunnel layer formed on top of the pinning layer, a first free layer with a perpendicular anisotropy that is formed on top of the tunnel layer, a granular film layer formed on top of the free layer, a second free layer formed on top of the granular film layer, a cap layer formed on top of the second layer, and a top electrode formed on top of the cap layer.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: July 23, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Patent number: 8493780
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: July 23, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8493779
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 23, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8493778
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: July 23, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Publication number: 20130182303
    Abstract: Disclosed herein are atom phase-controlled double rephasing-based quantum memory and a double-rephased photon echo method therefor. The atom phase-controlled double rephasing-based quantum memory includes an optical medium and an optical pulse generation unit. The optical medium has three energy levels (|1>, |2> and |3>), receives one or more optical pulses from an optical pulse generation unit, and generates output light that satisfies phase matching conditions. The optical pulse generation unit generates at least five optical pulses that resonate among the energy levels of the optical medium.
    Type: Application
    Filed: May 8, 2012
    Publication date: July 18, 2013
    Applicant: INHA-INDUSTRY PARTNERSHIP INSTITUTE
    Inventor: Byoung Seung HAM
  • Patent number: 8488232
    Abstract: An operating method for stimulated Raman adiabatic passage to change probability amplitude in a three-level system including states of |0>, |1> and |e>, includes the following two steps. One is to direct a first laser beam and a second laser beam which have frequencies in the vicinity of resonance frequencies corresponding to energy differences between |0> and |e> and between |1> and |e>, respectively. The other is to change temporally two-photon detuning to be a difference between first detuning and second detuning. The first detuning is a difference between a first energy difference and a frequency of the first laser beam. The first energy difference is a difference between energy of |0> and energy of |e>. The second detuning is a difference between a second energy difference and a frequency of the second laser beam. The second energy difference is a difference between energy of |1> and energy of |e>.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Nakamura, Kouichi Ichimura, Hayato Goto
  • Patent number: 8488375
    Abstract: According to one embodiment, a magnetic recording element includes a stacked body including a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer and a first nonmagnetic layer. Magnetization of the first ferromagnetic layer is substantially fixed in a first direction being perpendicular to a first ferromagnetic layer surface. The second stacked unit includes a third ferromagnetic layer, a fourth ferromagnetic layer and a second nonmagnetic layer. Magnetization of the fourth ferromagnetic layer is substantially fixed in a second direction being perpendicular to a fourth ferromagnetic layer surface. The first direction is opposite to the second direction.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: July 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Saida, Minoru Amano, Junichi Ito, Yuichi Ohsawa, Saori Kashiwada, Chikayoshi Kamata, Shigeki Takahashi
  • Patent number: 8488376
    Abstract: A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: July 16, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Roger Klas Malmhall
  • Patent number: 8477530
    Abstract: A non-uniform switching based non-volatile magnetic memory element includes a fixed layer, a barrier layer formed on top of the fixed layer, a first free layer formed on top of the barrier layer, a non-uniform switching layer (NSL) formed on top of the first free layer, and a second free layer formed on top of the non-uniform switching layer. Switching current is applied, in a direction that is substantially perpendicular to the fixed layer, barrier layer, first free layer, non-uniform switching layer and the second free layer causing switching between states of the first free layer, second free layer and non-uniform switching layer with substantially reduced switching current.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Petro Estakhri, Mahmud Assar, Parviz Keshtbod