Abstract: The present invention introduces a method and a structure for effectively generating spin currents in a metallic electric conductor. When, for example, a conductor manufactured from copper is evenly coated with a thin carbon layer, the internal direction of the magnetic axis, i.e. the spin, of the electrons acting as charge carriers can be polarized in such a way that the spins of the set of electrons align in the area of the interface between carbon and copper. This results in intensive generation of the spin current in the coated conductor. The generation of the spin current enables reduction of losses, shortening of delays relating to signal transfer and improvement of the general immunity to interferences.

Abstract: A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ?10 ohm/?m2.

Abstract: A memory includes: a memory device that has a memory layer storing data as a magnetization state of a magnetic body and a magnetization fixed layer whose direction of magnetization is fixed through a nonmagnetic layer interposed between the memory layer and the magnetization fixed layer and stores the data in the memory layer by changing a magnetization direction of the memory layer when a write current flowing in a stacked direction of the memory layer and the magnetization fixed layer is applied; and a voltage control unit that supplies the write current configured by independent pulse trains of two or more to the memory device by using a write voltage that is configured by independent pulse trains of two or more.

Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.

Abstract: There are provided magnetic storage elements capable of performing a high-reliability write operation by inhibiting erroneous reversal of data of the magnetic storage element put in a semi-selected state, and a magnetic storage device using this. A recording layer having an easy axis and a hard axis overlaps at least one of a first or second conductive layer at the entire region thereof in plan view. First endpoints of a first line segment along the easy axis and maximum in dimension overlapping the recording layer in plan view don't overlap the second conductive layer in plan view. At least one of second endpoints of a pair of endpoints of a second line segment passing through the middle point of the first line segment, orthogonal to the first line segment in plan view, and overlapping the recording layer in plan view doesn't overlap the first conductive layer in plan view.

Abstract: A logic device includes: a substrate having a channel layer; two input terminal patterns of ferromagnetic material formed on the substrate and spaced apart from each other along a longitudinal direction of the channel layer so as to serve as the input terminals of a logic gate; and an output terminal pattern of ferromagnetic material formed on the substrate and disposed between the two input terminal patterns to serve as an output terminal of the logic gate. The output terminal pattern reads an output voltage by using spin accumulation and diffusion of electron spins which are injected into the channel layer from the input terminal patterns.

Abstract: One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer.

Abstract: A method and system for providing a magnetic junction usable in a magnetic memory are described. The magnetic junction includes first and second pinned layers, first and second nonmagnetic spacer layers, and a free layer. The pinned layers are nonmagnetic layer-free and self-pinned. In some aspects, the magnetic junction is configured to allow the free and second pinned layers to be switched between stable magnetic states when write currents are passed therethrough. The magnetic junction has greater than two stable states. In other aspects, the magnetic junction includes at least third and fourth spacer layers, a second free layer therebetween, and a third pinned layer having a pinned layer magnetic moment, being nonmagnetic layer-free, and being coupled to the second pinned layer. The magnetic junction is configured to allow the free layers to be switched between stable magnetic states when write currents are passed therethrough.

Abstract: An MRAM array structure and a method of its operation that is not subject to accidental writing on half-selected elements. Each element of the MRAM is an MTJ (magnetic tunneling junction) cell operating in accord with an STT (spin torque transfer) scheme for changing its free layer magnetization state and each cell is patterned to have a C-shape in the horizontal plane. The cell thereby operates by C-mode switching to provide stability against accidental writing by half-selection. During operation, switching of a cell's magnetization is accomplished with the assist of the pulsed magnetic fields of additional word lines that are formed either orthogonal to or parallel to the existing bit lines and that can carry currents in either direction as required to provide the assist.

Abstract: A system may include first and second qubits that cross one another and a first coupler having a perimeter that encompasses at least a part of the portions of the first and second qubits, the first coupler being operable to ferromagnetically or anti-ferromagnetically couple the first and the second qubits together. A multi-layered computer chip may include a first plurality N of qubits laid out in a first metal layer, a second plurality M of qubits laid out at least partially in a second metal layer that cross each of the qubits of the first plurality of qubits, and a first plurality N times M of coupling devices that at least partially encompasses an area where a respective pair of the qubits from the first and the second plurality of qubits cross each other.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.

Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.

Abstract: The invention relates to a writable magnetic element comprising a stack of layers presenting a write magnetic layer, wherein the stack has a central layer of at least one magnetic material presenting a direction of magnetization that is parallel or perpendicular to the plane of the central layer, said central layer being sandwiched between first and second outer layers of non-magnetic materials, the first outer layer comprising a first non-magnetic material and the second outer layer comprising a second non-magnetic material that is different from the first non-magnetic material, at least the second non-magnetic material being electrically conductive, wherein it includes a device for causing current to flow through the second outer layer and the central layer in a current flow direction parallel to the plane of the central layer, and a device for applying a magnetic field having a component along a magnetic field direction that is either parallel or perpendicular to the plane of the central layer and the curr

Abstract: In an information storage device, a writing magnetic layer is formed on a substrate and has a magnetic domain wall. A connecting magnetic layer is formed on the writing magnetic layer, and an information storing magnetic layer is formed on an upper portion of side surfaces of the connecting magnetic layer. A reader reads information stored in the information storing magnetic layer.

Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.

Abstract: A method and system for providing a magnetic memory are described. The method and system include providing magnetic storage cells, bit lines coupled with the magnetic storage cells, preset lines, and word lines coupled with the magnetic storage cells. Each magnetic storage cell includes magnetic element(s). The bit lines drive write current(s) through selected storage cell(s) of the magnetic storage cells to write to the selected storage cell(s). The preset lines drive preset current(s) in proximity to but not through the selected storage cell(s). The preset current(s) generate magnetic field(s) to orient the magnetic element(s) of the selected storage cell(s) in a direction. The word lines enable the selected storage cell(s) for writing. Either the bit lines reside between the preset lines and the storage cells or the preset lines reside between the storage cells and on a storage cell side of the bit lines.

Abstract: Perpendicular magnetic tunnel junction (MTJ) devices, methods of fabricating a perpendicular MTJ device, electronic devices including a perpendicular MTJ device and methods of fabricating the electronic device are provided, the perpendicular MTJ devices include a pinned layer, a tunneling layer and a free layer. At least one of the pinned layer and the free layer includes a multi-layered structure including an amorphous perpendicular magnetic anisotropy (PMA) material.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have either in-plane or perpendicular anisotropy.

Abstract: A magnetic memory device may include a tunnel barrier, a reference layer on a first side of the tunnel barrier, and a free layer on a second side of the tunnel barrier so that the tunnel barrier is between the reference and free layers. The free layer may include a first magnetic layer adjacent the tunnel barrier, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer. More particularly, the nonmagnetic layer may be between the first and second magnetic layers, and the first magnetic layer may be between the tunnel barrier and the second magnetic layer. A product of a saturated magnetization of the first magnetic layer and a thickness of the first magnetic layer may be less than a product of a saturated magnetization of the second magnetic layer and a thickness of the second magnetic layer. Related methods are also discussed.

Abstract: A memory is provided that is capable of improving the thermal stability without increasing the write current. The memory is configured to include: a storage element which has a storage layer that holds information according to a magnetization state of a magnetic substance and in which a magnetization fixed layer is provided on the storage layer with an intermediate layer 16 interposed therebetween, the intermediate layer is formed of an insulator, the direction of magnetization of the storage layer is changed by injecting electrons spin-polarized in a lamination direction such that the information is recorded in the storage layer, and distortion is applied to the storage layer from an insulating layer which exists around the storage layer and has a smaller coefficient of thermal expansion than the storage layer. A wiring line for supplying a current flowing in the lamination direction of the storage element.

Abstract: An information storage device using movement of magnetic domain walls includes a writing magnetic layer having a magnetic domain wall. A stack structure is formed on the writing magnetic layer. The stack structure includes a connecting magnetic layer and an information storing magnetic layer stacked sequentially. The information storage device also includes a reader for reading information stored in the information storing magnetic layer.

Abstract: By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the free layer.

Abstract: A multi-bit cell of magnetic random access memory comprises a magnetic tunnel junction element including a first and second free layer comprising a changeable magnetization oriented substantially perpendicular to a layer plane in its equilibrium state and a switching current, a first and second tunnel barrier layer, and a pinned layer comprising a fixed magnetization oriented substantially perpendicular to a layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers, a selection transistor electrically connected to a word line, and a bit line intersecting the word line. The magnetic tunnel junction element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.

Abstract: A ferromagnetic graphene includes at least one antidot such that the ferromagnetic graphene has ferromagnetic characteristics. A spin valve device includes a ferromagnetic graphene. The ferromagnetic graphene includes a first region, a second region, and a third region. At least one antidot is formed in each of the first region and the third region. The first region and the third region are ferromagnetic regions, whereas the second region is a non-ferromagnetic region.

Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and a magnetic memory that operate with low power consumption and current writing and without element destruction. The magnetoresistive effect element includes a first magnetization pinned layer comprising at least one magnetic layer and in which a magnetization direction is pinned, a magnetization free layer in which a magnetization direction is changeable, a tunnel barrier layer provided between the first magnetization pinned layer and the magnetization free layer, a non-magnetic metal layer provided on a first region in an opposite surface of the magnetization free layer from the tunnel barrier layer, a dielectric layer provided on a second region other than the first region in the opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided to cover opposite surfaces of the non-magnetic metal layer and the dielectric layer from the magnetization free layer.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: Disclosed herein are a nanowire and a current-induced domain wall displacement-type memory device using the same.

Abstract: In a method for measurement of very small local magnetic fields, in particular of local magnetic stray fields produced by magnetic beads, at least one magnetoresistive element is used. The element includes a hard-magnetic reference layer and a soft-magnetic sensor layer, whose magnetization can be rotated to a parallel position or an antiparallel position with respect to the reference layer magnetization, and whose output signal which can be tapped off is dependent on the position of the sensor layer magnetization with respect to the reference layer magnetization.

Abstract: Provided is a high-speed and ultra-low-power-consumption nonvolatile memory having a high temperature stability at a zero magnetic field. In a tunnel magnetoresistive film constituting a nonvolatile magnetic memory that employs a writing method using a spin-transfer torque, an insulating layer and a nonmagnetic conductive layer are stacked above a ferromagnetic free layer.

Abstract: A spin high-frequency mixer includes a spin current generator generating a spin current upon input of a local oscillator signal, a TMR device which inputs a high-frequency signal and the spin current and generates a mixed signal, and an output device outputting the generated mixed signal from the TMR device.

Abstract: A method of operating an information storage device using a magnetic domain wall movement in a magnetic nanowire is provided. The magnetic nanowire includes a plurality of magnetic domains and pinning sites formed in regions between the magnetic domains. The method includes depinning the magnetic domain wall from a first pinning site by applying a first pulse current having a first pulse current density to the magnetic nanowire and moving the magnetic domain wall to a second pinning site by applying a second pulse current having a second pulse current density to the magnetic nanowire. The first pulse current density is greater than the second pulse current density.

Abstract: The present invention relates to a method and a device for providing a current of spin-polarised electrons. More particularly, the present invention is suited for use in spin electronics or detection of spin-polarised electrons.

Abstract: Measurement-only topological quantum computation using both projective and interferometrical measurement of topological charge is described. Various issues that would arise when realizing it in fractional quantum Hall systems are discussed.

Abstract: Devices, methods and articles advantageously allow communications between qubits to provide an architecture for universal adiabatic quantum computation. The architecture includes a first coupled basis A1B1 and a second coupled basis A2B2 that does not commute with the first basis A1B1.

Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.

Abstract: In one embodiment, the invention is a magnetic shift register memory device. One embodiment of a memory cell includes a magnetic column including a plurality of magnetic domains, a reader coupled to the magnetic column, for reading data from the magnetic domains, a temporary memory for storing data read from the magnetic domains, and a writer coupled to the magnetic column, for writing data in the temporary memory to the magnetic domains.

Abstract: A quantum bit computation method includes operating a two-quantum-bit gate on quantum bits of a first physical system and a second physical system, second energy states of second physical systems except for the first physical system and the second physical system do not change, three energy states being represented by |0>, |1> and |3>, the two energy states being represented by |2> and |4>, energies of |2> and |4> being higher than energies of |0>, |1> and |3>, a transition frequency between |3> and |2> being equal to the resonance frequency, |0> and |1> representing quantum bits, flipping quantum bits of first physical systems after operating the two-quantum-bit gate, executing no operations by a time equal to a time for operating the two-quantum-bit gate, after flipping the quantum bits, and again flipping the quantum bits of the first physical systems after executing no operations.

Abstract: A memory device includes: a memory layer that retains information based on a magnetization state of a magnetic material, a first intermediate layer and a second intermediate layer that are provided to sandwich the memory layer and are each formed of an insulator, a first fixed magnetic layer disposed on an opposite side of the first intermediate layer from the memory layer, a second fixed magnetic layer disposed on an opposite side of the second intermediate layer from the memory layer, and a nonmagnetic conductive layer provided between either the first intermediate layer or the second intermediate layer and the memory layer, the memory device being configured so that spin-polarized electrons are injected thereinto in a stacking direction to change the magnetization direction of the memory layer, thereby storing information in the memory layer.

Abstract: Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster.

Abstract: The present invention relates to compositions comprising functionalized or un-functionalized multi cyclic hydrocarbons and functional organic compounds, which can be used in different electronic devices. The invention further relates to an electronic device comprising one or more organic functional layers, wherein at least one of the layers comprises at least one functionalized or un-functionalized multi cyclic hydrocarbon. Another embodiment of the present invention relates to a formulation comprising functionalized or un-functionalized multi cyclic hydrocarbons, from which a thin layer comprising at least one functionalized or un-functionalized multi cyclic hydrocarbon can be formed.

Abstract: A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.

Abstract: Quantum and digital processors are employed together to solve computational problems. The quantum processor may be configured with a problem via a problem Hamiltonian and operated to perform adiabatic quantum computation and/or quantum annealing on the problem Hamiltonian to return a first solution to the problem that is in the neighborhood of the global minimum of the problem Hamiltonian. The digital processor may then be used to refine the first solution to the problem by casting the first solution to the problem as a starting point for a classical optimization algorithm. The classical optimization algorithm may return a second solution to the problem that corresponds to a lower energy state in the neighborhood of the global minimum, such as a ground state of the problem Hamiltonian. The quantum processor may include a superconducting quantum processor implementing superconducting flux qubits.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element is disclosed and has a fixed layer, a barrier layer formed upon the fixed layer, and a free layer comprised of a low-crystallization temperature alloy of CoFeB—Z where Z is below 25 atomic percent of one or more of titanium, (Ti), yittrium (Y), zirconium (Zr), and vanadium (V), wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.

Abstract: A magnetic memory element includes a pair of electrodes, a junction layer, at least one carbon nanotube, and at least one nanowire. The at least one nanowire is made of a ferromagnetic material and extends through a hole of each the at least one carbon nanotube with both ends being electrically connected to the pair of electrodes, respectively. The junction layer is made of a non-magnetic material and disposed between one of the pair of electrodes and one end of each the at least one nanowire. The one of the pair of electrodes is made of a ferromagnetic material. Magnetization of the at least one nanowire is reversed by spin injection performed through the junction layer with the one of the pair of electrodes.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.

Abstract: An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization fixed layer, a first magnetization free layer, a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer, a second magnetization fixed layer, a second magnetization free layer and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the second magnetization free layer. The first magnetization fixed layer and the first magnetization free layer have perpendicular magnetic anisotropy, and the second magnetization fixed layer and the second magnetization free layer have in-plane magnetic anisotropy. The first magnetization free layer and the second magnetization free layer are magnetically coupled to each other.

Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.

Abstract: Method and apparatus is described for a general purpose transistor of the higher dimensional (HD) spacetime backcloth consistent with symmetry parameters of a new cosmological paradigm with a unique M-Theoretic background making correspondence to a complex scale-invariant covariant Dirac polarized aether where energy pathways follow spacetime geodesics; and switching is achieved by manipulating resonant modes of a Calabi-Yau mirror symmetry hierarchy inherent in continuous-state brane topology of the structural-phenomenology of least cosmological units tiling the raster of spacetime as it emerges from the infinite potential of the unified field.

Abstract: Systems, circuits and methods for controlling write operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A reduced bit cell size is achieved by arranging the source lines (SL) substantially in parallel with the word lines (WL) and substantially perpendicular to the bit lines (BL). Further, in one embodiment during a write operation, a high logic/voltage level is applied to the bit lines of unselected bit cells to prevent an invalid write operation.

Abstract: An operating method for stimulated Raman adiabatic passage to change probability amplitude in a three-level system including states of |0>, |1> and |e>, includes the following two steps. One is to direct a first laser beam and a second laser beam which have frequencies in the vicinity of resonance frequencies corresponding to energy differences between |0> and |e> and between |1> and |e>, respectively. The other is to change temporally two-photon detuning to be a difference between first detuning and second detuning. The first detuning is a difference between a first energy difference and a frequency of the first laser beam. The first energy difference is a difference between energy of |0> and energy of |e>. The second detuning is a difference between a second energy difference and a frequency of the second laser beam. The second energy difference is a difference between energy of |1> and energy of |e>.