Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

Abstract: The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).

Abstract: A process for forming a functionalized sensor for sensing a molecule of interest includes providing at least one single or multi-wall carbon nanotube having a first and a second electrode in contact therewith on a substrate; providing a third electrode including a decorating material on the substrate a predetermined distance from the at least one single or multi-wall carbon nanotube having a first and a second electrode in contact therewith, wherein the decorating material has a bonding affinity for a bioreceptors that react with the molecule of interest; and applying a voltage to the third electrode, causing the decorating material to form nanoparticles of the decorating material on the at least one single or multi-wall carbon nanotube.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor device includes a substrate including a first top surface, a second top surface lower in level than the first top surface, and a first perpendicular surface disposed between the first and second top surfaces, a first source/drain region formed under the first top surface, a first nanowire extended from the first perpendicular surface in one direction and being spaced apart from the second top surface, a second nanowire extended from a side surface of the first nanowire in the one direction, being spaced apart from the second top surface, and including a second source/drain region, a gate electrode on the first nanowire, and a dielectric layer between the first nanowire and the gate electrode.

Abstract: A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: The present invention relates to compositions comprising functionalized or un-functionalized multi cyclic hydrocarbons and functional organic compounds, which can be used in different electronic devices. The invention further relates to an electronic device comprising one or more organic functional layers, wherein at least one of the layers comprises at least one functionalized or un-functionalized multi cyclic hydrocarbon. Another embodiment of the present invention relates to a formulation comprising functionalized or un-functionalized multi cyclic hydrocarbons, from which a thin layer comprising at least one functionalized or un-functionalized multi cyclic hydrocarbon can be formed.

Abstract: One example of the present invention is a nanoscale electronic device comprising a first conductive electrode, a second conductive electrode, and an anisotropic dielectric material layered between the first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material. Additional examples of the present invention include integrated circuits that contain multiple nanoscale electronic devices that each includes an anisotropic dielectric material layered between first and second electrodes having a permittivity in a direction approximately that of the shortest distance between the first and second electrodes less than the permittivity in other directions within the anisotropic dielectric material.

Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).

Abstract: A transistor includes a substrate, a source electrode, a drain electrode and a nanowire-layer. The source electrode, the drain electrode and the nanowires-layer are formed on the substrate. The source electrode includes a plurality of first pointed portions, and the drain electrode includes a plurality of second pointed portions each aligned with a corresponding first pointed portions. The nanowire-layer is interconnected between the first pointed portions and the second pointed portions.

Abstract: Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transistors, or other ambipolar transistors. Here, a current minor has been provided that uses ambipolar transistors, which accounts for the more unusual I-V (drain current to gate-source voltage) characteristics of ambipolar transistors.

Abstract: A technique of the invention reduces significantly the distance between the gate and single-walled carbon nanotubes to improve performance and efficiency of a carbon nanotube transistor device. Without using a porous template structure, single-walled carbon nanotubes are grown perpendicularly to a substrate between a base metal layer and a middle mesh layer. The nanotubes are insulated with a thin insulator and then gate regions are formed.

Abstract: Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), and a quantum well layer. A fin structure is formed in the quantum well structure, and an interfacial layer provided over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

Abstract: Disclosed are a biosensor, a method of producing the same, and a method of detecting a biomaterial through the biosensor. The biosensor includes a substrate, an insulating layer, source and drain electrodes formed on the insulating layer, a middle-discontinuous channel provided between the source and drain electrodes, and a detection area on which a detection target material is to be fixed, covering the middle-discontinuous channel.

Abstract: The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.

Abstract: A structure includes a surface and a non-equilibrium two-dimensional semiconductor micro structure on the surface.

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.

Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.

Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.

Abstract: A device for storing data using nanoparticle shuttle memory having a nanotube. The nanotube has a first end and a second end. A first electrode is electrically connected to the first end of the nanotube. A second electrode is electrically connected to the second end of the nanotube. The nanotube has an enclosed nanoparticle shuttle. A switched voltage source is electrically connected to the first electrode and the second electrode, whereby a voltage may be controllably applied across the nanotube. A resistance meter is also connected to the first electrode and the second electrode, whereby the electrical resistance across the nanotube can be determined.

Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract: Nanowire devices comprising core-shell or segmented nanowires are provided. In these nanowire devices, strain can be used as a tool to form metallic portions in nanowires made from compound semiconductor materials, and/or to create nanowires in which embedded quantum dots experience negative hydrostatic pressure or high positive hydrostatic pressure, whereby a phase transitions may occur, and/or to create exciton crystals.

Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.

Abstract: An apparatus including a first electrode; a second electrode; a nano-scale channel between the first electrode and the second electrode wherein the nano-scale channel has a first state in which an electrical impedance of the nano-scale channel is relatively high and a second state in which the electrical impedance of the nano-scale channel is relatively low; dielectric adjacent the nano-scale channel; and a gate electrode adjacent the dielectric configured to control a threshold number of quanta of stimulus, wherein the nano-scale channel is configured to switch between the first state and the second state in response to an application of a quantum of stimulus above the threshold number of quanta of stimulus.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: The present invention provides devices, methods and systems to selectively detect the binding of a molecular species to a biomolecule. In its olfactory sensing application, the hybrid sensor arrays of the present invention provide a high dimensional signature of odorants present that is also readily reversible, together enabling the identification and localization of a source analyte in the presence of the background odorant landscape inherent in a real-world setting.

Abstract: The invented ink-jet printing method for the construction of thin film transistors using all SWNTs on flexible plastic films is a new process. This method is more practical than all of existing printing methods in the construction TFT and RFID tags because SWNTs have superior properties of both electrical and mechanical over organic conducting oligomers and polymers which are often used for TFT. Furthermore, this method can be applied on thin films such as paper and plastic films while silicon based techniques cannot be used on such flexible films. These are superior to the traditional conducting polymers used in printable devices since they need no dopant and they are more stable. They could be used in conjunction with conducting polymers, or as stand-alone inks.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The semiconducting layer includes at least two stacked carbon nanotube films. Each carbon nanotube film includes an amount of carbon nanotubes. At least a part of the carbon nanotubes of each carbon nanotube film are aligned along a direction from the source electrode to the drain electrode.

Abstract: A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost.

Abstract: A nanostructure includes a nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A nanostructure in another embodiment includes a substrate having an area with a nanofeature; and a nanowire extending from the nanofeature, the nanowire having metallic spheres formed therein, the spheres being characterized as having at least one of about a uniform diameter and about a uniform spacing there between. A method for forming a nanostructure is also presented. A method for reading and writing data is also presented. A method for preparing nanoparticles is also presented.

Abstract: Electrodes made from metallic material are formed on a layer of dielectric material. A bottom layer of at least one of the electrodes constitutes a catalyst material in direct contact with the layer of dielectric material. Nanowires are grown by means of the catalyst, between the electrodes, parallel to the layer of dielectric material. The nanowires connecting the two electrodes are then made from single-crystal semi-conductor material and in contact with the layer of dielectric material.

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: Methods and articles providing for precise aligning, positioning, shaping, and linking of nanotubes and carbon nanotubes. An article comprising: a solid surface comprising at least two different surface regions including: a first surface region which comprises an outer boundary and which is adapted for carbon nanotube adsorption, and a second surface region which is adapted for preventing carbon nanotube adsorption, the second region forming an interface with the outer boundary of the first region, at least one carbon nanotube which is at least partially selectively adsorbed at the interface. The shape and size of the patterns on the surface and the length of the carbon nanotube can be controlled to provide for selective interfacial adsorption.

Abstract: A method of making nanostructures using a self-assembled monolayer of organic spheres is disclosed. The nanostructures include bowl-shaped structures and patterned elongated nanostructures. A bowl-shaped nanostructure with a nanorod grown from a conductive substrate through the bowl-shaped nanostructure may be configured as a field emitter or a vertical field effect transistor. A method of separating nanoparticles of a desired size employs an array of bowl-shaped structures.

Abstract: Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom.

Abstract: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Abstract: A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.

Abstract: A biosensor using a nanodot and a method of manufacturing the same are provided. A silicon nanowire can be formed by a CMOS process to reduce manufacturing costs. In addition, an electrically charged nanodot is coupled to a target molecule to be detected, in order to readily change conductivity of the silicon nanowire, thereby making it possible to implement a biosensor capable of providing good sensitivity and being manufactured at a low cost.

Abstract: A method for making a thin film transistor, the method includes the steps of: providing a plurality of carbon nanotubes and an insulating substrate; flocculating the carbon nanotubes to acquire a carbon nanotube structure, applying the carbon nanotube structure on the insulating substrate; forming a source electrode, a drain electrode, and a gate electrode; and covering the carbon nanotube structure with an insulating layer. The source electrode and the drain electrode are connected to the carbon nanotube structure, the gate electrode is electrically insulated from the carbon nanotube structure by the insulating layer.

Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.

Abstract: A nanoscale variable resistor including a metal nanowire as an active element, a dielectric, and a gate. By selective application of a gate voltage, stochastic transitions between different conducting states, and even length, of the nanowire can be induced and with a switching time as fast as picoseconds. With an appropriate choice of dielectric, the transconductance of the device, which may also be considered an “electromechanical transistor,” is shown to significantly exceed the conductance quantum G0=2e2/h.

Abstract: The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Abstract: Disclosed are methods of using magnetic or electric fields to align magnetically responsive nanoparticles in a polymeric matrix, which has not yet been completely solidified. The nanoparticles are preferably magnetically doped, then blended with photovoltaic polymer material to form devices. The methods provided are particularly useful for the formation of solar cell devices. The devices include nanostructured electron-conducting channels arranged approximately parallel to one another, where the channels comprise magnetically doped materials, as well as photovoltaic materials interspersed with the nanostructured electron-conducting channels. The method provides a way to control the morphology of blended photovoltaic devices, which will improve efficiencies. In addition, the new method provides a way to control the growth of novel, cheap, solar cells, which can in turn lead to enhanced performance.

Abstract: Electronic devices having carbon-based materials and techniques for making contact to carbon-based materials in electronic devices are provided. In one aspect, a device is provided having a carbon-based material; and at least one electrical contact to the carbon-based material comprising a metal silicide, germanide or germanosilicide. The carbon-based material can include graphene or carbon nano-tubes. The device can further include a segregation region, having an impurity, separating the carbon-based material from the metal silicide, germanide or germanosilicide, wherein the impurity has a work function that is different from a work function of the metal silicide, germanide or germanosilicide. A method for fabricating the device is also provided.

Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.

Abstract: Methods and devices for manufacturing carbon nanotube based field effect transistors are disclosed including providing a substrate; printing a gate electrode layer onto the substrate and sintering and/or UV curing; printing a gate isolation layer onto the gate electrode and air drying and/or UV curing; printing one or more carbon nanotube channel layers onto the gate isolation layer, wherein each carbon nanotube channel layer is air dried prior to subsequent printings; and printing a source and drain electrode layer onto the one or more carbon nanotube channel layers and sintering and/or UV curing. Other embodiments are described and claimed.

Abstract: A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.