Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.

Abstract: Graphene electronic devices may include a gate electrode on a substrate, a first gate insulating film covering the gate electrode, a plurality of graphene channel layers on the substrate, a second gate insulating film between the plurality of graphene channel layers, and a source electrode and a drain electrode connected to both edges of each of the plurality of graphene channel layers.

Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate contains a nanowire mesh device and a second portion of the SOI substrate contains a partially depleted semiconductor on insulator (PDSOI) device. The nanowire mesh device includes stacked and spaced apart semiconductor nanowires located on the SOI substrate with each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region. The nanowire mesh device further includes a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires. The PDSOI device includes a partially depleted semiconductor layer on the substrate, and a gate region over at least a portion of the partially depleted semiconductor layer.

Abstract: A semiconductor hybrid structure on an SOI substrate. A first portion of the SOI substrate containing a nanowire mesh device and a second portion of the SOI substrate containing a FINFET device. The nanowire mesh device including stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region; and a gate region over at least a portion of the stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region. The FINFET device including spaced apart fins on a top semiconductor layer on the second portion of the substrate; and a gate region over at least a portion of the fins.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A method of forming a self-aligned device is provided and includes depositing carbon nanotubes (CNTs) onto a crystalline dielectric substrate, isolating a portion of the crystalline dielectric substrate encompassing a location of the CNTs, forming gate dielectric and gate electrode gate stacks on the CNTs while maintaining a structural integrity thereof and forming epitaxial source and drain regions in contact with portions of the CNTs on the crystalline dielectric substrate that are exposed from the gate dielectric and gate electrode gate stacks.

Abstract: Three-dimensional integrated circuits and method for fabricating the same include forming one or more passive components in a passive-layer dielectric; depositing additional dielectric material on the passive-layer dielectric; forming a gate structure in the additional dielectric material; forming a gate dielectric layer on the gate structure and the additional dielectric material; forming a thin channel material on the gate dielectric; forming source and drain regions in electrical contact with the thin channel material to form a transistor; and passivating the transistor and providing electrical access to the source and drain regions.

Abstract: A method is provided for fabricating a nanowire-based semiconductor structure. The method includes forming a first nanowire with a first polygon-shaped cross-section having a first number of sides. The method also includes forming a semiconductor layer on surface of the first nanowire to form a second nanowire with a second polygon-shaped cross-section having a second number of sides, the second number being greater than the first number. Further, the method includes annealing the second nanowire to remove a substantial number of vertexes of the second polygon-shaped cross-section to form the nanowire with a non-polygon-shaped cross-section corresponding to the second polygon-shaped cross-section.

Abstract: An alternating stack of first and second semiconductor layers is formed. Fin-defining mask structures are formed over the alternating stack. A planarization dielectric layer and first and second gate cavities therein are subsequently formed. The first and second gate cavities are extended downward by etching the alternating stack employing a combination of the planarization layer and the fin-defining mask structures as an etch mask. The germanium-free silicon material is isotropically etched to laterally expand the first gate cavity and to form a first array of semiconductor nanowires including the silicon-germanium alloy, and the silicon-germanium alloy is isotropically etched to laterally expand the second gate cavity and to form a second array of semiconductor nanowires including the germanium-free silicon material. The first and second gate cavities are filled with replacement gate structures. Each replacement gate structure laterally can surround a two-dimensional array of semiconductor nanowires.

Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is formed on a substrate. A portion of the substrate is removed to form a recess below a section of the carbon nanotube. A doped material is applied in the recess to fabricate the semiconducting device. The recess may be between one or more contacts formed on the substrate separated by a gap.

Abstract: Methods for making non-volatile switches include depositing gate material in a recess of a substrate; depositing drain metal in a recess of the gate material; planarizing the gate material, drain metal, and substrate; forming sidewalls by depositing material on the substrate around the gate material; forming a flexible conductive element between the sidewalls to establish a gap between the flexible conductive element and the gate material, such that the gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening a circuit; and forming a source terminal in electrical contact with the flexible conductive element.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: A carbon nanotube field-effect transistor is disclosed. The carbon nanotube field-effect transistor includes a first carbon nanotube film, a first gate layer coupled to the first carbon nanotube film and a second carbon nanotube film coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first carbon nanotube film as well as to influence an electric field of the second carbon nanotube film. At least one of a source contact and a drain contact are coupled to the first and second carbon nanotube film and are separated from the first gate layer by an underlap region.

Abstract: A nanogap device includes a first insulation layer having a nanopore formed therein, a first nanogap electrode which may be formed on the first insulation layer and may be divided into two parts with a nanogap interposed between the two parts, the nanogap facing the nanopore, a second insulation layer formed on the first nanogap electrode, a first graphene layer formed on the second insulation layer, a first semiconductor layer formed on the first graphene layer, a first drain electrode formed on the first semiconductor layer, and a first source electrode formed on the first graphene layer such as to be apart from the first semiconductor layer.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: A nano resonance apparatus includes a gate electrode configured to generate a magnetic field, and a nanowire connecting a source electrode to a drain electrode and configured to vibrate in the presence of the magnetic field. The nanowire includes a protruding portion extending in a direction of the gate electrode.

Abstract: A method for wetting a nanopore device includes filling a first cavity of the nanopore device with a first buffer solution having a first potential hydrogen (pH) value, filling a second cavity of the nanopore device with a second buffer solution having a second pH value, wherein the nanopore device includes a transistor portion having a first surface, an opposing second surface, and an orifice communicative with the first surface and the second surface, the first surface partially defining the first cavity, the second surface partially defining the second cavity, applying a voltage in the nanopore device, and measuring a current in the nanopore device, the current having a current path partially defined by the first cavity, the second cavity, and the orifice.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.

Abstract: A nanowire field effect transistor device includes a first nanowire having a first distal end connected to a source region, a second distal end connected to a drain region, and a channel region therebetween, the source region and the drain region arranged on a substrate, and a second nanowire having a first distal end connected to the source region and a second distal end connected to the drain region, and a channel region therebetween, a longitudinal axis of the first nanowire and a longitudinal axis of the second nanowire defining a plane, the plane arranged substantially orthogonal to a plane defined by a planar surface of the substrate.

Abstract: A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first sacrificial layer, depositing a second sacrificial layer on the first layer of semiconductor material, depositing a second layer of the semiconductor material on the second sacrificial layer, pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer, patterning a dummy gate stack, removing the dummy gate stack, removing portions of the sacrificial layer to define a first nanowire including a portion of the first semiconductor layer and a second nanowire including a portion of the second semiconductor layer, and forming gate stacks about the first nanowire and the second nanowire.

Abstract: A graphene transistor includes: (1) a substrate; (2) a source electrode disposed on the substrate; (3) a drain electrode disposed on the substrate; (4) a graphene channel disposed on the substrate and extending between the source electrode and the drain electrode; and (5) a top gate disposed on the graphene channel and including a nanostructure.

Abstract: A separated carbon nanotube-based active matrix organic light-emitting diode (AMOLED) device including a substrate and transistors. Each transistor includes an individual back gate patterned on the substrate and a gate dielectric layer disposed over the substrate. An active channel including a network of separated semiconducting nanotubes is disposed over a functionalized surface of the gate dielectric layer. A source contact and a drain contact are formed on two ends of the active channel, with the network of separated nanotubes between the source contact and the drain contact. An organic light-emitting diode (OLED) display device is coupled to the drain of one of the transistors. A system includes a display control circuit having a substrate, with scan lines, data lines, and AMOLED devices formed on the substrate, with each AMOLED device coupled to one of the scan lines and one of the data lines.

Abstract: A method is provided for eliminating catalyst residues that are present on the surface of solid structures. The solid structures are made from a first material and are obtained by catalytic growth from a substrate. The method includes the following steps: catalytically growing, from the catalyst residues, solid structures made from a second material; and selectively eliminating the solid structures made from the second material, thereby eliminating the catalyst residues.

Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.

Abstract: Fabricating semiconductor nanowires (5) on a substrate (1) having a metallic oxide layer (2), includes: a) exposing the metallic oxide layer to a hydrogen plasma (11) of power P for a duration t suitable for reducing the layer and for forming metallic nanodrops (3) of radius (Rm) on the surface of the metallic oxide layer; b) low temperature plasma-assisted deposition of a thin layer (4) of a semiconductor material on the metallic oxide layer including the metallic nanodrops, the thin layer having a thickness (Ha) suitable for covering the metallic nanodrops; and c) thermal annealing at a temperature T sufficient to activate lateral growth of nanowires by catalysis of the material deposited as a thin layer from the metallic nanodrops. Nanowires are obtained by this method and nanometric transistors including a semiconductor nanowire.

Abstract: This disclosure generally relates to a device with a monolayer of metal nanoparticles and a method for making the same. The nanoparticles of the monolayer of metal nanoparticles are grouped in an ultrahigh density with an average distance between each neighboring metal nanoparticle less than or equal to about 3 nanometers. The monolayer can be self-assembled on a substrate to facilitate controllable voltage shifts within the device.

Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.

Abstract: A method of fabricating a semiconductor device is disclosed. A first contact layer of the semiconductor device is fabricated. An electrical connection is formed between a carbon nanotube and the first contact layer by electrically coupling of the carbon nanotube and a second contact layer. The first contact layer and second contact layer may be electrically coupled.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: A composition and method for forming a field effect transistor with a stable n-doped nano-component. The method includes forming a gate dielectric on a gate, forming a channel comprising a nano-component on the gate dielectric, forming a source over a first region of the nano-component, forming a drain over a second region of the nano-component to form a field effect transistor, and exposing a portion of a nano-component of a field effect transistor to dihydrotetraazapentacene, wherein dihydrotetraazapentacene is represented by the formula: wherein each of R1, R2, R3, and R4 comprises one of hydrogen, an alkyl group of C1 to C16 carbons, an alkoxy group, an alkylthio group, a trialkylsilane group, a hydroxymethyl group, a carboxylic acid group and a carboxylic ester group.

Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Abstract: A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.

Abstract: According to example embodiments, a field effect transistor includes a graphene channel layer on a substrate. The graphene channel layer defines a slit. A source electrode and a drain electrode are spaced apart from each other and arranged to apply voltages to the graphene channel layer. A gate insulation layer is between the graphene channel layer and a gate electrode.

Abstract: Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A transistor device includes an insulator on a substrate and a gate embedded in the insulator. The transistor device further includes a dielectric material, a channel, and a self-assembled monolayer. The dielectric material is deposited over the gate and insulator forming a dielectric layer. The channel includes carbon nanotubes and is formed on the dielectric layer over the gate. The self-assembled monolayer is formed over at least the channel.

Abstract: A field effect transistor device includes: a reservoir bifurcated by a membrane of three layers: two electrically insulating layers; and an electrically conductive gate between the two insulating layers. The gate has a surface charge polarity different from at least one of the insulating layers. A nanochannel runs through the membrane, connecting both parts of the reservoir. The device further includes: an ionic solution filling the reservoir and the nanochannel; a drain electrode; a source electrode; and voltages applied to the electrodes (a voltage between the source and drain electrodes and a voltage on the gate) for turning on an ionic current through the ionic channel wherein the voltage on the gate gates the transportation of ions through the ionic channel.

Abstract: A field effect transistor having at least one Ge nanorod and a method of manufacturing the field effect transistor are provided. The field effect transistor may include a gate oxide layer formed on a silicon substrate, at least one nanorod embedded in the gate oxide layer having both ends thereof exposed, a source electrode and a drain electrode connected to opposite sides of the at least one Ge nanorod, and a gate electrode formed on the gate oxide layer between the source electrode and the drain electrode.

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

Abstract: Stress sensors and stress sensor integrated circuits using one or more nanowire field effect transistors as stress-sensitive elements, as well as design structures for a stress sensor integrated circuit embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and related methods thereof. The stress sensors and stress sensor integrated circuits include one or more pairs of gate-all-around field effect transistors, which include one or more nanowires as a channel region. The nanowires of each of the field effect transistors are configured to change in length in response to a mechanical stress transferred from an object. A voltage output difference from the field effect transistors indicates the magnitude of the transferred mechanical stress.

Abstract: A photodetector includes: a substrate; a first dielectric material positioned on the substrate; an optical waveguide positioned on the first dielectric material; a second dielectric material positioned on the optical waveguide; a graphene layer positioned on the second dielectric material; and a first electrode and a second electrode that are positioned on the graphene layer.

Abstract: The present invention is directed to methods of preparing nanoprobes, including multifunctional cellular endoscope-like devices, comprising nanotubes, nanorods, and/or nanowires.

Abstract: A graphene electronic device and a method of fabricating the graphene electronic device are provided. The graphene electronic device may include a graphene channel layer formed on a hydrophobic polymer layer, and a passivation layer formed on the graphene channel layer. The hydrophobic polymer layer may prevent or reduce adsorption of impurities to transferred graphene, and a passivation layer may also prevent or reduce adsorption of impurities to a heat-treated graphene channel layer.

Abstract: The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

Abstract: Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.

Abstract: The present invention relates to a method for producing a microelectronic device having a channel structure formed from superimposed nanowires, in which a nanowire stack having a constant transverse section is firstly formed, followed by a sacrificial gate and insulating spacers, where source and drain areas are then formed by growth of semiconductor material on areas of the stack which are not protected by the sacrificial gate and the insulating spacers (FIG. 4D).