Abstract: A circuit for reading or writing a RAM includes a shift register coupled to the RAM, a test data input, and a test data output. The circuit further includes a control circuit configured to generate a pulse every N clock cycles, each pulse triggering a RAM access operation transferring data between the shift register and the RAM, N being equal to a data width of the RAM divided by a parallel factor, the parallel factor being a number of pins in either the test data input or the test data output configured for parallel data loading.

Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and a write operation method. The write operation circuit includes a serial-to-parallel conversion circuit, a data buffer, a DBI decoder, and a precharge module. The serial-to-parallel conversion circuit performs serial-to-parallel conversion on first DBI data of a DBI port to generate second DBI data for transmission via a DBI signal line and generates input data of the data buffer according to the second DBI data and input data of a DQ port. The data buffer determines, according to the input data of the data buffer, whether to invert the global bus. The DBI decoder receives the second DBI data, decodes the global bus data and writes the decoded global bus data into the memory bank, where the decoding comprises determining whether to invert the global bus data. The precharge module sets an initial state of the global bus to Low.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.

Abstract: A computer-implemented method according to one embodiment includes applying a predetermined augmentation to the sample set of training data to create an augmented sample set, training a model with the augmented sample set, determining a performance of the trained model, and assigning a weight to the predetermined augmentation for the training data set based on the determined performance. A determination is made as to whether to apply the predetermined augmentation to a larger training data set before the training data set is applied to the model, based on the weight assigned to the predetermined augmentation.

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

Abstract: This application relates to a data transmission circuit, method, and storage devices. The comparison module compares the bus data on the data bus with the global data on the global data line, and the comparison result shows whether the number of bits that are different from the global data on the output bus data exceeds the preset threshold, which is set based on the comparison result. When the comparison result exceeds the preset threshold, a first data conversion module inverts the bus data and provides it to the data bus buffer module, and when the comparison result does not exceed the preset threshold, the bus data is provided to the data bus buffer module. The data bus buffer module generates a data polarity identification signal according to the comparison result, and transmit the bus data or the inverted data of the bus data to the global data line.

Abstract: Disclosed herein are a Gaussian sampling apparatus and method based on resistive RAM. The Gaussian sampling apparatus based on resistive RAM includes Resistive RAM (RRAM) in which a resistive switching layer is disposed between an upper electrode and a lower electrode, and a sampling controller, wherein the sampling controller is configured to perform an operation corresponding to an erase command of applying a reset voltage to the RRAM when a Gaussian error request is received from an outside of the Gaussian sampling apparatus, perform an operation corresponding to a program command of applying a set voltage to the RRAM after the operation corresponding to the erase command has been completed, perform an operation of reading resistance data from the RRAM, and provide a response to the outside of the Gaussian sampling apparatus by transmitting the resistance data of the RRAM as Gaussian error data.

Abstract: Provided are a Fail Bit (FB) repair solution determination method and device, which are applied to a chip including multiple subdomains. The chip further includes Redundancy (RD) circuits, and the RD circuits are configured to repair FBs in the subdomains. The method includes that: after one or more available RD circuits are determined for a target FB presently to be repaired in a subdomain, a reliability value of each available RD circuit is acquired from an RD circuit reliability list, the RD circuit reliability list including reliability values of multiple RD circuits, and a repair solution for the target FB in the subdomain is determined according to the reliability value of the available RD circuit. The reliability value of the RD circuit is obtained by performing big data analysis on relationships between generated FBs and RD circuits where NFBs are located in the RD circuits.

Abstract: A power gating control circuit includes an operational period signal generating circuit, a period termination detecting circuit, a power gating period signal generating circuit and a power gating control signal generating circuit. The operational period signal generating circuit generates a plurality of operational period signals based on internal clock signals and one or more of command shift signals. The period termination detecting circuit generates a write period termination signal and a read period termination signal based on the command signals and the plurality of operational period signals. The power gating period signal generating circuit generates a first power gating period signal and a second power gating period signal based on the write period termination signal, the read period termination signal and remaining command shift signals other than the one or more command shift signals.

Abstract: Methods, apparatus, systems and articles of manufacture to facilitate atomic compare and swap in cache for a coherent level 1 data cache system are disclosed. An example system includes a cache storage; a cache controller coupled to the cache storage wherein the cache controller is operable to: receive a memory operation that specifies a key, a memory address, and a first set of data; retrieve a second set of data corresponding to the memory address; compare the second set of data to the key; based on the second set of data corresponding to the key, cause the first set of data to be stored at the memory address; and based on the second set of data not corresponding to the key, complete the memory operation without causing the first set of data to be stored at the memory address.

Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Abstract: An angle sensor generates an angle detection value based on a first and a second detection signal. A correction apparatus performs correction processing for generating a first corrected detection signal by adding a first correction value to the first detection signal and generating a second corrected detection signal by adding a second correction value to the second detection signal. When an angle to be detected varies with a period T and if no correction processing is performed, the angle detection value contains an Nth-order angle error component varying with a period of T/N. Each of the first and second detection signals contains an (N?1)th-order signal error component and an (N+1)th-order signal error component. The order of the first and second correction values is N?1 or N+1.

Abstract: Systems and methods for improving the reliability of non-volatile memory by reducing the number of memory cell transistors that experience excessive hole injection are described. The excessive hole injection may occur when the threshold voltage for a memory cell transistor is being set below a particular negative threshold voltage. To reduce the number of memory cell transistors with threshold voltages less than the particular negative threshold voltage, the programmed data states of the memory cell transistors may be reversed such that the erased state comprises the highest data state corresponding with the highest threshold voltage distribution. To facilitate programming of the memory cell transistors with reversed programmed data states, a non-volatile memory device structure may be used in which the bit line connections to NAND strings comprise direct poly-channel contact to P+ silicon and the source line connections to the NAND strings comprise direct poly-channel contact to N+ silicon.

Abstract: Memory devices may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations may use multiple (e.g., at least two) sets or groupings of read commands and the write operations may use multiple (e.g., at least two) sets or groupings of write commands.

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.

Abstract: The present disclosure includes apparatuses and methods related to copying data in a memory system with an artificial intelligence (AI) mode. An apparatus can receive a command indicating that the apparatus operate in an artificial intelligence (AI) mode, a command to perform AI operations using an AI accelerator based on a status of a number of registers, and a command to copy data between memory devices that are performing AI operations. The memory system can copy neural network data, activation function data, bias data, input data, and/or output data from a first memory device to a second memory device, such that that the first memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a first AI operation and the second memory device can use the neural network data, activation function data, bias data, input data, and/or output data in a second AI operation.