Etching Inorganic Substrate Patents (Class 216/74)
  • Patent number: 8231796
    Abstract: A method and system provide a magnetic transducer that includes an underlayer and a nonmagnetic layer on the underlayer. The method and system include providing a trench in the nonmagnetic layer. The trench has a plurality of sides. The method and system also include providing a separation layer in the trench. A portion of the separation layer resides on the sides of the trench. The method and system include providing the main pole. At least part of the main pole resides in the trench on the portion of the separation layer and has a plurality of pole sides. The method and system further include removing at least a portion of the second nonmagnetic layer, thereby exposing the portion of the separation layer. The method and system also include providing a side shield. The separation layer magnetically separates the pole sides from the side shield.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 31, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Yun-Fei Li, Yingjian Chen
  • Patent number: 8231795
    Abstract: An acoustic device includes a transducer formed on a first surface of a substrate and an acoustic horn formed in the substrate by a dry-etching process through an opposing second surface of the substrate. The acoustic horn is positioned to amplify sound waves from the transducer and defines a non-linear cross-sectional profile.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: July 31, 2012
    Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.
    Inventors: David Martin, Joel Philliber, John Choy
  • Patent number: 8216663
    Abstract: A member having high non-electrostatic properties and high hydrophilicity and preventing an adhesion of contaminants, a surface-treating process and an apparatus for the surface-treating process are provided. A surface-treatment apparatus comprises a water vapor-generating unit 1, a superheating unit 5 for superheating a water vapor to generate a superheated water vapor, and a processing unit 11 for spraying the superheated water vapor to a member 14 to be treated (a ceramic, a metal) or for exposing the member to the superheated water vapor. Treating the untreated member with a superheated water vapor having a temperature 300 to 1000° C., hydrophilicity and antistatic properties are imparted to the member. The untreated member may be a member (a window member) contacting with a processing space in a vapor phase surface process apparatus (e.g., a chamber) for the surface process of a substrate by a vapor phase method such as a PVD, a CVD, or a dry etching.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: July 10, 2012
    Assignee: Canaan Precision Co., Ltd.
    Inventor: Koichiro Takayanagi
  • Patent number: 8216481
    Abstract: A method for manufacturing a magnetoresistive read sensor that allows the sensor to be constructed with clean well defined side junctions, even at very narrow track widths. The method involves using first and second etch mask layers, that are constructed of materials such that the second mask (formed over the first mask) can act as a mask during the patterning of the first mask (bottom mask). The first mask has a well defined thickness that is defined by deposition and which is not affected by the etching processes used to define the mask. This allows the total ion milling etch mask thickness to be well controlled before the ion milling process used to define the sensor side walls.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: July 10, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventor: Liubo Hong
  • Publication number: 20120171463
    Abstract: A method of forming a ceramic article including providing a ceramic body comprising silicon carbide, and treating the ceramic body in an atmosphere comprising an oxidizing material to remove a portion of the ceramic body through a chemical reaction between a portion of the ceramic body and the oxidizing material.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Applicant: SAINT-GOBAIN CERMAICS & PLASTICS, INC.
    Inventors: Christopher J. Reilly, Yu Zhong
  • Patent number: 8211805
    Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: July 3, 2012
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Shun Lo, Hsing-Chao Liu
  • Patent number: 8202435
    Abstract: A method for selectively etching areas of a substrate is described. The method includes providing in a process chamber a substrate containing a first material having a film deposition surface and a second material having an etch surface. The method further includes forming a gas cluster ion beam (GCIB) from a pressurized gas containing a deposition-etch gas, and exposing the substrate to the GCIB to remove at least a portion of the second material from the etch surface and deposit a thin film on the film deposition surface of the first material. According to some embodiments, the deposition-etch gas may contain silicon (Si) and carbon (C), and it may possess a Si—C bond.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: June 19, 2012
    Assignee: TEL Epion Inc.
    Inventor: Martin D. Tabat
  • Patent number: 8137574
    Abstract: The present invention is to provide a processing method for manufacturing a highly flat and highly smooth glass substrate with good productivity. A highly flat and highly smooth glass substrate is obtained with good productivity by processing of a glass substrate, which comprises a step of measuring the surface shape of the glass substrate prior to processing, a step of processing the surface of the substrate by changing a processing condition for each site (first processing step), and a step of finish-polishing the surface of the glass substrate that has been subjected to the first processing step (second processing step).
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: March 20, 2012
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Hiroshi Kojima, Masabumi Ito
  • Patent number: 8138096
    Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: March 20, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 8133325
    Abstract: This dry cleaning method for a plasma processing apparatus is a dry cleaning method for a plasma processing apparatus that includes: a vacuum container provided with a dielectric member; a planar electrode and a high-frequency antenna that are provided outside the dielectric member; and a high-frequency power source that supplies high-frequency power to both the high-frequency antenna and the planar electrode, to thereby introduce high-frequency power into the vacuum container via the dielectric member and produce an inductively-coupled plasma, the method comprising the steps of: introducing a gas including fluorine into the vacuum container and also introducing high-frequency power into the vacuum container from the high-frequency power source, to thereby produce an inductively-coupled plasma in the gas including fluorine; and by use of the inductively-coupled plasma, removing a product including at least one of a precious metal and a ferroelectric that is adhered to the dielectric member.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 13, 2012
    Assignee: ULVAC, Inc.
    Inventors: Masahisa Ueda, Yutaka Kokaze, Mitsuhiro Endou, Koukou Suu
  • Patent number: 8124541
    Abstract: An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF3 and at least one oxidizing agent, such as at least one of oxygen, ozone, nitrous oxide, nitric oxide and hydrogen peroxide. The etchant gas provides a method of uniformly removing the late transition metal structure or a portion thereof. Moreover, the etchant gas facilitates removing a late transition metal structure with an increased etch rate and at a decreased etch temperature. A method of removing a late transition metal without removing more reactive materials proximate the late transition metal and exposed to the etchant gas is also disclosed.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Patent number: 8088297
    Abstract: The present invention relates firstly to HF/fluoride-free etching and doping media which are suitable both for the etching of silicon dioxide layers and also for the doping of underlying silicon layers. The present invention also relates secondly to a process in which these media are employed.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: January 3, 2012
    Assignee: Merck Patent GmbH
    Inventors: Armin Kuebelbeck, Werner Stockum
  • Patent number: 8057690
    Abstract: Methods for creating at least one micro-electromechanical (MEMS) structure in a silicon-on-insulator (SOI) wafer. The SOI wafer with an extra layer of oxide is etched according to a predefined pattern. A layer of oxide is deposited over exposed surfaces. An etchant selectively removes the oxide to expose the SOI wafer substrate. A portion of the SOI substrate under at least one MEMS structure is removed, thereby releasing the MEMS structure to be used in the formation of an accelerometer.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: November 15, 2011
    Assignee: Honeywell International Inc.
    Inventor: Lianzhong Yu
  • Patent number: 8048322
    Abstract: A method for manufacturing a thermal interface material includes the following steps: providing a carbon nanotube array formed on a substrate, the carbon nanotube array having a number of carbon nanotubes and a number of interstices between the adjacent carbon nanotubes; filling a liquid state first base material into the interstices; curing the first base material, thereby achieving a carbon nanotube/first base material composite; dripping a liquid state second base material onto the surface of the carbon nanotube/first base material composite, the first base material melting and flowing out of the carbon nanotube/first base material composite, until the carbon nanotube array being substantially submerged in the second base material; and curing the second base material, thereby achieving a thermal interface material.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: November 1, 2011
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yuan Yao, Chang-Hong Liu
  • Patent number: 8048325
    Abstract: A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: November 1, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Vaidyanathan Balasubramaniam, Koichiro Inazawa, Rie Inazawa, Rich Wise, Arpan Mahorawala, Siddhartha Panda
  • Patent number: 8043659
    Abstract: A substrate processing method capable of controlling the internal pressure of a processing chamber to a high pressure and exhausting gases within the processing chamber at a high rate. The substrate processing method is for use in a substrate processing apparatus having a processing chamber, a supply unit supplying a processing gas into the processing chamber, a first pipe connected to the processing chamber at one end thereof, a turbo molecular pump disposed in the first pipe, a first shutoff valve disposed between the processing chamber and the turbo molecular pump in the first pipe, a second pipe connected to the processing chamber at one end thereof, a pressure control valve disposed in the second pipe, and a dry pump connected to the other end of the first pipe and to the other end of the second pipe.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: October 25, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Eiji Takahashi, Norihiko Amikura
  • Patent number: 8043518
    Abstract: The method of manufacturing a nozzle plate which includes a nozzle having a tapered section and a linear section includes the steps of: forming an etching stopper layer for stopping dry etching of a silicon substrate, on a first surface of the silicon substrate; forming a mask layer on a second surface of the silicon substrate reverse to the first surface; performing a first patterning process with respect to the mask layer so that an opening section is formed in the mask layer; carrying out the dry etching of the silicon substrate through the opening section in the mask layer so that the tapered section of the nozzle is formed in the silicon substrate; carrying out dry etching of the etching stopper layer through the opening section in the mask layer so that at least a part of the linear section of the nozzle is formed in the etching stopper layer; and removing the mask layer.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: October 25, 2011
    Assignee: Fujifilm Corporation
    Inventor: Shuji Takahashi
  • Patent number: 8012879
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: September 6, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 7988873
    Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-Soo Kim, Sang-Hyeop Lee
  • Patent number: 7981308
    Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Robert Bosch GmbH
    Inventor: Gary Yama
  • Patent number: 7959819
    Abstract: The present invention provides a method and an apparatus for reducing aspect ratio dependent etching that is observed when plasma etching deep trenches in a semiconductor substrate through an alternating deposition/etch process. A plurality of different sized features on the substrate are monitored in real time during the alternating deposition/etch process. Then, based on the information received from the monitor, at least one process parameter is adjusted in the alternating deposition/etch process to achieve equivalent etch depths of at least two different sized features on the substrate.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: June 14, 2011
    Inventors: Shouliang Lai, David Johnson, Russell Westerman
  • Patent number: 7938973
    Abstract: By incorporating a material exhibiting a high adhesion on chamber walls of a process chamber during sputter etching, the defect rate in a patterning sequence on the basis of an ARC layer may be significantly reduced, since the adhesion material may be reliably exposed during a sputter preclean process. The corresponding adhesion layer may be positioned within the ARC layer stack so as to be reliably consumed, at least partially, while nevertheless providing the required optical characteristics. Hence, a low defect rate in combination with a high process efficiency may be achieved.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: May 10, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Joerg Hohage, Martin Mazur
  • Publication number: 20110073562
    Abstract: The present invention provides a method of fabricating at least one single layer hexagonal boron nitride (h-BN). In an exemplary embodiment, the method includes (1) suspending at least one multilayer boron nitride across a gap of a support structure and (2) performing a reactive ion etch upon the multilayer boron nitride to produce the single layer hexagonal boron nitride suspended across the gap of the support structure. The present invention also provides a method of fabricating single layer hexagonal boron nitride. In an exemplary embodiment, the method includes (1) providing multilayer boron nitride suspended across a gap of a support structure and (2) performing a reactive ion etch upon the multilayer boron nitride to produce the single layer hexagonal boron nitride suspended across the gap of the support structure.
    Type: Application
    Filed: September 30, 2010
    Publication date: March 31, 2011
    Applicant: The Regents of the University of California
    Inventor: Alexander K. Zettl
  • Publication number: 20110049103
    Abstract: Methods of manufacturing a honeycomb extrusion die comprise the steps of coating at least a portion of a die body with a layer of conductive material and modifying the die body with an electrical discharge machining technique. The method then further includes the step of chemically removing the layer of conductive material, wherein the residual material from the electrical discharge machining technique is released from the die body.
    Type: Application
    Filed: August 25, 2009
    Publication date: March 3, 2011
    Inventor: Mark Lee Humphrey
  • Patent number: 7892445
    Abstract: A method of dechucking a wafer, with a low-k dielectric layer, held onto an electrostatic chuck by an electrostatic charge in a plasma chamber is provided. The electrostatic clamping voltage is removed. An essentially argon free dechucking gas is provided into the plasma chamber. A dechucking plasma is formed from the dechucking gas in the plasma chamber. The dechucking plasma is stopped.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: February 22, 2011
    Assignee: Lam Research Corporation
    Inventors: David Wei, Howard Dang, Masahiro Watanabe, Sean Kang, Kenji Takeshita, Mayumi Block, Stephen Sirard, Eric Hudson
  • Patent number: 7887711
    Abstract: A system and method for patterning metal oxide materials in a semiconductor structure. The method comprises a first step of depositing a layer of metal oxide material over a substrate. Then, a patterned mask layer is formed over the metal oxide layer leaving one or more first regions of the metal oxide layer exposed. The exposed first regions of the metal oxide layer are then subjected to an energetic particle bombardment process to thereby damage the first regions of the metal oxide layer. The exposed and damaged first regions of the metal oxide layer are then removed by a chemical etch. Advantageously, the system and method is implemented to provide high-k dielectric materials in small-scale semiconductor devices. Besides using the ion implantation damage (I/I damage) plus wet etch technique to metal oxides (including metal oxides not previously etchable by wet methods), other damage methods including lower energy, plasma-based ion bombardment, may be implemented.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: February 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Douglas A. Buchanan, Eduard A. Cartier, Evgeni Gousev, Harald Okorn-Schmidt, Katherine L. Saenger
  • Patent number: 7846843
    Abstract: A process for manufacturing a semiconductor device using a spacer as an etch mask for forming a fine pattern is described. The process includes forming a hard mask layer over a target layer that is desired to be etched. A sacrificial layer pattern is subsequently formed over the hard mask layer. Spacers are formed on the sidewalls of the sacrificial layer pattern. The protective layer is formed on the hard mask layer portions between the sacrificial patterns formed with the spacer. The sacrificial layer pattern and the protective layer are then later removed, respectively. The hard mask layer is etched using the spacer as an etching mask. After etching, the spacer is removed. Finally, the target layer is etched using the etched hard mask as an etching mask.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chai O Chung, Jong Min Lee, Chan Bae Kim, Hyeon Ju An, Hyo Seok Lee, Sung Kyu Min
  • Patent number: 7842618
    Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: November 30, 2010
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Unsoon Kim, Angela T. Hui, Yider Wu, Kuo-Tung Chang, Hiroyuki Kinoshita
  • Patent number: 7833388
    Abstract: A method for manufacturing a magnetic layer with a magnetic anisotropy. The method includes an endpoint detection process for determining an end point to carefully control the final thickness of the magnetic layer. The method includes depositing a magnetic layer and then depositing a sacrificial layer over the magnetic layer. A low power angled ion milling is then performed until the magnetic layer has been reached. The angled ion milling can be performed at an angle relative to normal and without rotation in order to form an anisotropic surface texture that induces a magnetic anisotropy in the magnetic layer. An indicator layer may be included between the magnetic layer and the sacrificial layer in order to further improve endpoint detection.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: November 16, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Matthew Joseph Carey, Jeffrey Robinson Childress, Stefan Maat
  • Patent number: 7807061
    Abstract: A method of producing a structure by three-dimensionally processing a flat member includes a preparing, a first forming and a second forming. In the preparing, a substrate is prepared. In the first forming, an etching mask is formed on the substrate. The etching mask has at least two openings, and areas of the two openings are different from each other. In the second forming, at least a part of a three-dimension surface shape of the structure is formed on a surface of the substrate by a dry-etching on the substrate in accordance with the area of the opening of the etching mask.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 5, 2010
    Assignee: DENSO CORPORATION
    Inventors: Hiroyuki Wado, Kazuhiko Kanoh
  • Patent number: 7794617
    Abstract: A plasma etching method includes the step of: etching a silicon layer of a target object by using a plasma generated from a processing gas containing a fluorocarbon gas, a hydrofluorocarbon gas, a rare gas and an O2 gas and by employing a patterned resist film as a mask. The target object includes the silicon layer whose main component is silicon and the patterned resist film formed over the silicon layer.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: September 14, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Akihiro Kikuchi, Takashi Tsunoda, Yuichiro Sakamoto
  • Patent number: 7771541
    Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla
  • Patent number: 7749396
    Abstract: A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: July 6, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, William S. Wong, Michael Chabinyc, Ana Claudia Arias
  • Patent number: 7744769
    Abstract: The invention relates to a gas for removing deposits by a gas-solid reaction. This gas includes a hypofluorite that is defined as being a compound having at least one OF group in the molecule. Various deposits can be removed by the gas, and the gas can easily be made unharmful on the global environment after the removal of the deposits, due to the use of a hypofluorite. The gas may be a cleaning gas for cleaning, for example, the inside of an apparatus for producing semiconductor devices. This cleaning gas comprises 1-100 volume % of the hypofluorite. Alternatively, the gas of the invention may be an etching gas for removing an unwanted portion of a film deposited on a substrate. The unwanted portion can be removed by this etching gas as precisely as originally designed, due to the use of a hypofluorite. The invention further relates to a method for removing a deposit by the gas.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: June 29, 2010
    Assignee: Central Glass Company, Limited
    Inventors: Isamu Mouri, Tetsuya Tamura, Mitsuya Ohashi
  • Patent number: 7732339
    Abstract: An organic/inorganic hybrid film represented by SiCx- HyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Kenshi Kanegae, Shinichi Imai, Hideo Nakagawa
  • Patent number: 7704402
    Abstract: An optical element manufacturing method includes: disposing a light-shielding layer (14) that includes at least an Si layer as an uppermost layer, on a substrate (12) used as a base member, forming an optical aperture (14a) at the light-shielding layer (14) and forming a fine recession/projection structure (MR) at a surface of the uppermost layer through dry etching.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: April 27, 2010
    Assignee: Nikon Corporation
    Inventors: Yutaka Hamamura, Kiyoshi Kadomatsu, Noboru Amemiya
  • Patent number: 7674389
    Abstract: Methods of shape modifying a nanodevice by contacting it with a low-energy focused electron beam are disclosed here. In one embodiment, a nanodevice may be permanently reformed to a different geometry through an application of a deforming force and a low-energy focused electron beam. With the addition of an assist gas, material may be removed from the nanodevice through application of the low-energy focused electron beam. The independent methods of shape modification and material removal may be used either individually or simultaneously. Precision cuts with accuracies as high as 10 nm may be achieved through the use of precision low-energy Scanning Electron Microscope scan beams. These methods may be used in an automated system to produce nanodevices of very precise dimensions. These methods may be used to produce nanodevices of carbon-based, silicon-based, or other compositions by varying the assist gas.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: March 9, 2010
    Assignee: The Regents of the University of California
    Inventors: Alex Zettl, Thomas David Yuzvinsky, Adam Fennimore
  • Patent number: 7622051
    Abstract: A method of etching a substrate in a plasma processing chamber is disclosed. The method includes introducing the substrate having thereon an underlying layer, an anti-reflective layer above the underlying layer, and a photo-resist layer above the anti-reflective layer into the chamber. The method also includes flowing a gas mixture into the chamber, the gas mixture includes a flow of a hydrofluorocarbon gas, a flow of fluorocarbon gas, a flow of a halogen-containing gas other than the hydrofluorocarbon gas, and a flow of oxygen gas. The method further includes striking a plasma from the gas mixture. The method additionally includes etching at least through the anti-reflective layer with the plasma.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: November 24, 2009
    Assignee: Lam Research Corporation
    Inventors: David M. Schaefer, Gowri P. Kota
  • Patent number: 7608196
    Abstract: A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 sccm and 40 sccm for CHF3 and between about 10 sccm and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: October 27, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, David S. Becker
  • Patent number: 7601643
    Abstract: An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: October 13, 2009
    Assignee: LSI Logic Corporation
    Inventor: Charles E. May
  • Patent number: 7547636
    Abstract: A method for selectively etching an ultra high aspect ratio feature dielectric layer through a carbon based mask in an etch chamber is provided. A flow of an etch gas is provided, comprising a fluorocarbon containing molecule and an oxygen containing molecule to the etch chamber. A pulsed bias RF signal is provided. An energizing RF signal is provided to transform the etch gas to a plasma.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: June 16, 2009
    Assignee: Lam Research Corporation
    Inventors: Kyeong-Koo Chi, Erik A. Edelberg
  • Patent number: 7544622
    Abstract: A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define “best fit” lines on that graph.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: June 9, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Satish Bedge
  • Patent number: 7524768
    Abstract: A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 28, 2009
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Eugene M. Chow, William S. Wong, Michael Chabinyc, Jeng Ping Lu, Ana Claudia Arias
  • Patent number: 7501071
    Abstract: A method of producing a patterned mirror on a transparent conductive substrate comprises the steps of; coating a layer of conductive material onto a substrate, coating a layer of metal onto the layer of conductive material, coating a layer of photoresist onto the layer of metal, curing the layer of photoresist, exposing a desired pattern of transparent conductors through a first mask onto the layer of photoresist, developing the photoresist and simultaneously etching the layer of the conductive material and the layer of metal, exposing a desired pattern of metal conductors through a second mask onto the remaining layer of photoresist, developing the photoresist and etching the layer of metal.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: March 10, 2009
    Assignee: Eastman Kodak Company
    Inventors: John R. Fyson, Christopher B. Rider
  • Patent number: 7497960
    Abstract: A method for manufacturing a filter is provided which can easily manufacture the filter that has both excellent anti-corrosion properties and anti-abrasion properties. In the method, a first substrate is produced that has a plurality of holes, a ceramic layer will be formed by depositing extremely small particles of ceramic material on one side of the first substrate, and a filter having a plurality of holes will be obtained. The manufactured filter is composed of ceramic material, and has excellent anti-abrasion and anti-corrosion properties.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: March 3, 2009
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroto Sugahara
  • Publication number: 20090035523
    Abstract: A member having high non-electrostatic properties and high hydrophilicity and preventing an adhesion of contaminants, a surface-treating process and an apparatus for the surface-treating process are provided. A surface-treatment apparatus comprises a water vapor-generating unit 1, a superheating unit 5 for superheating a water vapor to generate a superheated water vapor, and a processing unit 11 for spraying the superheated water vapor to a member 14 to be treated (a ceramic, a metal) or for exposing the member to the superheated water vapor. Treating the untreated member with a superheated water vapor having a temperature 300 to 1000° C., hydrophilicity and antistatic properties are imparted to the member. The untreated member may be a member (a window member) contacting with a processing space in a vapor phase surface process apparatus (e.g., a chamber) for the surface process of a substrate by a vapor phase method such as a PVD, a CVD, or a dry etching.
    Type: Application
    Filed: June 15, 2006
    Publication date: February 5, 2009
    Applicants: Asahi Tech Co., Ltd., SEKISUI CHEMICAL CO., LTD.
    Inventors: Koichiro Takayanagi, Shigeru Nomura, Takamaro Kakehi, Kenji Yamauchi, Takahiro Oomura, Miki Inaoka
  • Patent number: 7465404
    Abstract: An ink-jet printhead includes a substrate on which an ink chamber to be supplied with ink to be ejected is formed on a front surface of the substrate, a manifold for supplying ink to the ink chamber is formed on a rear surface of the substrate, and an ink passage in communication with the ink chamber and the manifold is formed parallel to the front surface of the substrate, a nozzle plate formed on the front surface of the substrate, a nozzle formed through the nozzle plate through which ink is ejected from the ink chamber, a heater formed on the nozzle plate, and an electrode electrically connected to the heater for applying current to the heater.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seog-soon Baek, Yong-soo Oh, Keon Kuk, Ki-deok Bae, Seung-ju Shin, Su-ho Shin
  • Publication number: 20080197111
    Abstract: A method for fabricating a nonvolatile memory device includes forming a gate stack over a substrate, the gate stack including an aluminum oxide layer as a dielectric layer, and etching the aluminum oxide layer of the gate stack using a gas containing silicon.
    Type: Application
    Filed: December 6, 2007
    Publication date: August 21, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Tae-Woo JUNG
  • Patent number: 7405162
    Abstract: An etching method forms an opening with a substantially vertical profile extending to a stopper layer by performing an etching with a plasma of an etching gas acting on an object to be processed loaded in an evacuable processing vessel, wherein the object has a mask layer of a predetermined pattern, a silicon layer to be etched formed below the mask layer and the stopper layer formed below the silicon layer. The etching method includes a first etching process for forming an opening with a tapered wall surface in the silicon layer by using a first etching gas including a fluorine-containing gas and O2 but not HBr; and a second etching process for etching the opening by using a second etching gas including a fluorine-containing gas, O2 and HBr.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: July 29, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Koji Maruyama, Yusuke Hirayama, Nozomi Hirai, Takanori Mimura
  • Patent number: 7402255
    Abstract: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. The mirror can include a top flange and a bottom flange joined by a web, wherein the top and the bottom flanges form the top and the bottom surfaces, respectively. The rotational comb teeth can have a tapered shape. Stationary comb teeth can be interdigitated with the rotational comb teeth either in-plane or out-of-plane. Steady or oscillating voltage difference between the rotational and the stationary comb teeth can be used to oscillate or tune the mirror.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: July 22, 2008
    Assignee: Advanced NuMicro Systems, Inc.
    Inventor: Yee-Chung Fu