Etching Inorganic Substrate Patents (Class 216/74)
- Etching of substrate containing at least one compound having at least one oxygen atom and at least one metal atom (Class 216/76)
- Etching of substrate containing elemental aluminum, or an alloy or compound thereof (Class 216/77)
- Etching of substrate containing elemental copper, or an alloy or compound thereof (Class 216/78)
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Publication number: 20020025478Abstract: A phase shift mask blank includes a transparent substrate and a phase shift film composed primarily of a metal and silicon. The substrate has an etch rate A and the phase shift film has an etch rate B when the blank is patterned by reactive ion etching, such that the etch selectivity B/A is at least 5.0. When a phase shift mask is manufactured from the blank, the substrate is less prone to overetching, providing good controllability and in-plane uniformity of the phase shift in patterned areas. The phase shift mask can be used to fabricate semiconductor integrated circuits to a smaller minimum feature size and a higher level of integration.Type: ApplicationFiled: July 12, 2001Publication date: February 28, 2002Applicant: Shin-Etsu Shemical Co., Ltd.Inventors: Yukio Inazuki, Tamotsu Maruyama, Mikio Kojima, Hideo Kaneko, Masataka Watanabe, Satoshi Okazaki
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Publication number: 20020023894Abstract: A method for producing periodic nanometer-scale arrays of metal or semiconductor junctions on a clean semiconductor substrate surface is provided comprising the steps of: etching the substrate surface to make it hydrophilic, forming, under an inert atmosphere, a crystalline colloid layer on the substrate surface, depositing a metal or semiconductor material through the colloid layer onto the surface of the substrate, and removing the colloid from the substrate surface. The colloid layer is grown on the clean semiconductor surface by withdrawing the semiconductor substrate from a sol of colloid particles.Type: ApplicationFiled: August 3, 2001Publication date: February 28, 2002Inventor: Robert Rossi
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Patent number: 6342428Abstract: For use with a sub-micron semiconductor process, a trench isolation process improves the etch profile of trenches among dense and isolated lines. In an example embodiment, a process forms a dielectric stack of silicon dioxide, silicon nitride and silicon oxynitride on a silicon substrate. Photolithography and etch define trench regions in the silicon substrate through the dielectric stack. Silicon oxynitride acts as a hard mask reducing differences in the sidewall slope among dense areas of the semiconductor device and the sparse areas of the semiconductor device.Type: GrantFiled: October 4, 1999Date of Patent: January 29, 2002Assignee: Philips Electronics North America Corp.Inventors: Tammy Zheng, Calvin Todd Gabriel, Edward K. Yeh
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Patent number: 6342165Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.Type: GrantFiled: July 19, 2000Date of Patent: January 29, 2002Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, David S. Becker
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Patent number: 6340435Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: June 9, 1999Date of Patent: January 22, 2002Assignee: Applied Materials, Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Publication number: 20010035357Abstract: Provided are a method of forming a magnetic layer pattern and a method of manufacturing a thin film magnetic head, which can reduce the number of manufacturing steps and thus reduce the manufacturing time. A precursory nonmagnetic layer and a precursory bottom pole layer are formed in this sequence so as to cover a frame pattern formed on an underlayer (a top shield layer) and having an opening. Then, the precursory nonmagnetic layer and the precursory bottom pole layer are patterned by polishing the overall surface by CMP until at least the frame pattern is exposed, and thus a nonmagnetic layer and a bottom pole are selectively formed. The number of manufacturing steps can be reduced and thus the manufacturing time can be reduced, as compared to the case of forming the nonmagnetic layer and the bottom pole without forming the frame pattern.Type: ApplicationFiled: April 18, 2001Publication date: November 1, 2001Applicant: TDK CORPORATIONInventor: Yoshitaka Sasaki
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Publication number: 20010030172Abstract: A sputtering target is provided which provides early stabilization of the film-deposition rate of the sputtering target from its initial stage of use. The sputtering target surface subjected to erosion is formed with a surface-deformed layer. The surface-deformed layer is reduced by precision machining and removed by etching. The extent of etching is controlled so that the surface roughness (Ra) is in a range between 0.1% and 10% of the mean crystal grain diameter of the material constituting the target. The surface roughness (Ra) is defined as the mean roughness on the center line of the surface.Type: ApplicationFiled: May 24, 2001Publication date: October 18, 2001Inventors: Hideyuki Takahashi, Tateo Ohhashi, Kazuhiro Seki
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Publication number: 20010013505Abstract: Provided is a method of manufacturing a thin film magnetic head which enables dimensional control of a pole width and enables reducing the time required to form the pole width. After a top pole chip precursory layer made of iron nitride is formed by sputtering, a surface of the top pole chip precursory layer is polished and flattened. A first mask precursory layer and a photoresist film are formed in sequence on the flattened top pole chip precursory layer. A photoresist pattern having an opening is formed by selectively exposing and patterning the photoresist film by photolithography. The surface of the top pole chip precursory layer is polished and flattened, and thus a surface of the first mask precursory layer formed over the top pole chip precursory layer is also flat. Thus, pattern deformation resulting from light reflected from an underlayer during exposure is prevented, and therefore the opening of the photoresist pattern can be formed with high accuracy.Type: ApplicationFiled: February 12, 2001Publication date: August 16, 2001Applicant: TDK CORPORATIONInventor: Yoshitaka Sasaki
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Patent number: 6271498Abstract: A vaporizing apparatus has a vaporizing container into which a liquid raw material is introduced and which is made of metal, a heater for heating the vaporizing container to vaporize liquid introduced into the vaporizing container and a metal nozzle (an electrode) disposed in the vaporizing container in such a manner that the nozzle is electrically insulated from the vaporizing container. Moreover, the vaporizing apparatus has a cleaning-solution supply apparatus for supplying, to the inside portion of the vaporizing container, a cleaning solution for solving residues generated in the vaporizing container and a plasma generating power source for supplying high-frequency electric power to a position between the nozzle and the vaporizing container to generate plasma in the vaporizing container by using the vaporized cleaning solution.Type: GrantFiled: June 22, 1998Date of Patent: August 7, 2001Assignee: Nissin Electric Co., LTDInventors: Koji Miyake, Hajime Kuwahara, Tsukasa Hayashi
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Publication number: 20010010360Abstract: An infrared photosensitive area is constituted by an infrared ray absorbing part that is heated by infrared rays, a thermal detector that detects the temperature change of the infrared ray absorbing part, and electrodes that are electrically connected to the thermal detector. The infrared photosensitive area is held up above one surface of a substrate by supports. The electrodes of the infrared photosensitive area are electrically connected to contact pads on the substrate by wiring material that constitutes the support. A shield projects from portions of the infrared ray absorbing part other than portions that correspond to the electrodes. The contact pads of the substrate and the surfaces of the electrodes and the supports that are directed away from the substrate are covered by the shield with an interposed space. This configuration enables an increase in the fill factor of the picture elements of the thermal infrared detector and enables greater absorption of infrared light.Type: ApplicationFiled: January 30, 2001Publication date: August 2, 2001Inventor: Naoki Oda
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Patent number: 6231776Abstract: The present invention provides a technique, including a method and apparatus, for etching a substrate in the manufacture of a device. The apparatus includes a chamber and a substrate holder disposed in the chamber. The substrate holder has a selected thermal mass to facilitate changing the temperature of the substrate to be etched during etching processes. That is, the selected thermal mass of the substrate holder allows for a change from a first temperature to a second temperature within a characteristic time period to process a film. The present technique can, for example, provide different processing temperatures during an etching process or the like.Type: GrantFiled: September 10, 1998Date of Patent: May 15, 2001Inventor: Daniel L. Flamm
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Patent number: 6165375Abstract: The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus.Type: GrantFiled: September 23, 1997Date of Patent: December 26, 2000Assignee: Cypress Semiconductor CorporationInventors: Chan-lon Yang, Usha Raghuram, Kimberley A. Kaufman, Daniel Arnzen, James Nulty
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Patent number: 6156243Abstract: (1) Alignment mark transfer portion(s) is/are formed on the transfer molding surface of a mold that is used for press-molding a optical element fixing member and having alignment marks; (2) alignment mark(s) is/are formed on the mold material by dry-etching, and the mold material is worked using the alignment mark(s) as a reference to form the transfer molding surface constituted by a plurality of transfer patterns, in order to obtain a mold for press-molding; and (3) the transfer patterns are formed by dry-etching, or a transfer molding bare surface for transfer patterns is formed by dry-etching and a mold release film is formed thereon to reflect the shape of the transfer molding base surface, in order to obtain a mold for press-molding.Type: GrantFiled: April 22, 1998Date of Patent: December 5, 2000Assignee: Hoya CorporationInventors: Hiroyuki Kosuga, Yoshiatsu Yokoo
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Patent number: 6114044Abstract: A method of fabricating a micromachine includes the step of constructing a low surface energy film on the micromachine. The micromachine is then rinsed with a rinse liquid that has a high surface energy, relative to the low surface energy film, to produce a contact angle of greater than 90.degree. between the low surface energy film and the rinse liquid. This relatively large contact angle causes any rinse liquid on the micromachine to be displaced from the micromachine when the micromachine is removed from the rinse liquid. In other words, the micromachine is dried by dewetting from a liquid-based process. Thus, a separate evaporative drying step is not required, as the micromachine is removed from the liquid-based process in a dry state. The relatively large contact angle also operates to prevent attractive capillary forces between micromachine components, thereby preventing contact and adhesion between adjacent microstructure surfaces.Type: GrantFiled: May 30, 1997Date of Patent: September 5, 2000Assignee: Regents of the University of CaliforniaInventors: Michael R. Houston, Roger T. Howe, Roya Maboudian, Uthara Srinivasan
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Patent number: 6103630Abstract: A new method of etching metal lines using SF.sub.6 gas during the overetch step to prevent undercutting of the anti-reflective coating layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A barrier metal layer is deposited overlying the insulating layer. A metal layer is deposited overlying the barrier metal layer. A silicon oxide layer is deposited overlying the metal layer. The silicon oxide layer is covered with a layer of photoresist which is exposed, developed, and patterned to form the desired photoresist mask. The silicon oxide layer is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The metal layer is etched away where it is not covered by the patterned hard mask to form metal lines. Overetching is performed to remove the barrier layer where it is not covered by the hard mask wherein SF.sub.Type: GrantFiled: February 9, 1998Date of Patent: August 15, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Hua Lee, Chia-Shiung Tsai
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Patent number: 6093331Abstract: A method for the precise removal of the backside silicon on face down semiconductor devices to obtain a planar surface to allow electron beam microprobe analysis of the semiconductor device. The backside silicon is removed by plasma etching in a fluorocarbon based chemical plasma. The epitaxial layer in a CMOS device acts as an etch stop and the buried oxide layer in an SOI device acts as an etch stop.Type: GrantFiled: December 11, 1997Date of Patent: July 25, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Donald L. Wollesen
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Patent number: 6090717Abstract: A method in a plasma processing chamber for etching through a selected portion of a metallization layer of a wafer's layer stack. The method includes the step of etching at least partially through the metallization layer of the layer stack with an etchant source gas that consists essentially of chlorine and nitrogen. In another embodiment, the metallization layer comprises aluminum, and the flow ratio of the chlorine to the nitrogen ranges from about 1:1 to about 10:1. More preferably, the flow ratio of the chlorine to the nitrogen ranges from about 1:1 to about 4:1 and preferably ranges from about 1:1 to about 2:1.Type: GrantFiled: March 26, 1996Date of Patent: July 18, 2000Assignee: Lam Research CorporationInventors: Stephen F. Powell, Jeffrey V. Musser, Robert Guerra, Timothy R. Webb
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Patent number: 6083363Abstract: An apparatus and method for processing the surface of a substrate with a plasma formed from a process gas comprises a processing chamber defining a plasma source region and a processing region wherein electrical energy is coupled into the source region to form and sustain a plasma therein, and an ion extraction mechanism positioned between the source region and processing region for extracting ions from the plasma and directing extracted ions and neutral particles into the processing region to process a biased substrate therein. A gas-dispersing element in the processing space disperses a process gas to intersect paths of the extracted ions and to produce charge exchange collisions to create a large number of high-energy neutral particles for processing the workpiece.Type: GrantFiled: July 2, 1997Date of Patent: July 4, 2000Assignee: Tokyo Electron LimitedInventors: Kaihan Abidi Ashtiani, James Anthony Seirmarco
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Patent number: 6083771Abstract: A method and system for manufacturing theft-deterrent computer components is disclosed. Initially, computer components are grouped in a single batch. Each of the computer components are then provided with multiple indelible indicia during manufacturing. All of the indelible indicia on each component have a common value that is different than that assigned to any other computer component.Type: GrantFiled: February 17, 1998Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: James Peter Ward, Richard Mark Flanagan, James Andrew McNee, Brian John Walsh
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Patent number: 6071353Abstract: The present invention is a method for cleaning a process chamber without damaging the process kit by coating the process kit with another consumable material that protects the process kit during the etch that removes buildup from the processing chamber. First, a polysilicon layer is deposited on at least one inner surface of the processing chamber. Next, a silicon nitride layer deposition is performed on at least one semiconductor substrate in the processing chamber. The semiconductor substrate having said nitride layer thereon is then removed from the processing chamber. An etch is then performed to remove the nitride layer buildup from the inner surface of the processing chamber that has the polysilicon layer thereon.Type: GrantFiled: October 31, 1997Date of Patent: June 6, 2000Assignee: Applied Materials, Inc.Inventor: Peter Gallagher
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Patent number: 6063711Abstract: A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.Type: GrantFiled: April 28, 1998Date of Patent: May 16, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Li-Chih Chao, Chia-Shiung Tsai, Chu-Yun Fu, Jhon-Jhy Liaw
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Patent number: 6056887Abstract: A process for fabricating a feeler member for a micromechanical probe, in particular for an atomic force microscope, consists in creating a "positive" first mold by isotropically or anisotropically undercutting a silicon substrate. The resulting tip is precursor of the hard material (preferably diamond) tip to be obtained. The precursor has a small angle at the apex, for example in the order of 10.degree. to 20.degree., or less. The positive mold is then used to fabricate a "negative" mold having an imprint whose shape is that of the tip precursor. The negative mold is filled with a layer of hard material and the tip is then uncovered. The hard material tip therefore also has a small angle at the apex, equal to that of the precursor. The resolution that can be achieved with the probe is therefore higher than that assured by prior art probes.Type: GrantFiled: June 4, 1998Date of Patent: May 2, 2000Assignee: C.S.E.M. - Centre Suisse d'Electronique et de Microtechniques S.A.Inventors: Philipp Niedermann, Cynthia Beuret, Sylvain Jeanneret
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Patent number: 6036877Abstract: A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.Type: GrantFiled: May 13, 1996Date of Patent: March 14, 2000Assignee: Applied Materials, Inc.Inventors: Kenneth S. Collins, Michael Rice, David W. Groechel, Gerald Zheyao Yin, Jon Mohn, Craig A. Roderick, Douglas Buchberger, Chan-Lon Yang, Yuen-Kui Wong, Jeffrey Marks, Peter Keswick
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Patent number: 6030514Abstract: A target for sputtering is subjected to a surface treatment process and special packaging after target manufacture for improved sputtering performance and process and yield by reducing particulates. The sputtering target is first surface treated to remove oxides, impurities and contaminants. The surface treated target is then covered with a metallic enclosure and, optionally, a passivating barrier layer. The metallic enclosure protects the target surface from direct contact with subsequently employed packaging material such as plastic bags, thereby eliminating sources of organic materials during sputtering operations. The surface treatment of the target removes deformed material, smearing, twins, or burrs and the like from the target surface, reducing "burn-in" or sputter conditioning time prior to production sputtering of thin films.Type: GrantFiled: May 2, 1997Date of Patent: February 29, 2000Assignees: Sony Corporation, Materials Research CorporationInventors: John A. Dunlop, Michael Goldstein, Gerald B. Feldewerth, Cari Shim, Stephan Schittny
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Patent number: 6024885Abstract: A process of patterning magnetic multilayer films including the steps of successively depositing a plurality of magnetic multilayer films on a supporting substrate, selectively removing portions of the plurality of magnetic multilayer films using a reactive plasma etch including chlorine gas, and passivating in situ, or an adjacent evacuated chamber, remaining portions of the plurality of magnetic multilayer films, i.e. the memory elements, in a post-etch fluorinated plasma.Type: GrantFiled: December 8, 1997Date of Patent: February 15, 2000Assignee: Motorola, Inc.Inventors: Sandeep Pendharkar, Douglas J. Resnick
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Patent number: 6019906Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.Type: GrantFiled: May 29, 1998Date of Patent: February 1, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Syun-Ming Jang, Ming-Hsin Huang
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Patent number: 6013582Abstract: The present disclosure pertains to a method for plasma etching a semiconductor patterning stack. The patterning stack includes at least one layer comprising either a dielectric-comprising antireflective material or an oxygen-comprising material. In many instances the dielectric-comprising antireflective material will be an oxygen-comprising material, but it need not be limited to such materials. In one preferred embodiment of the method, the chemistry enables the plasma etching of both a layer of the dielectric-comprising antireflective material or oxygen-comprising material and an adjacent or underlying layer of material. In another preferred embodiment of the method, the layer of dielectric-comprising antireflective material or oxygen-comprising material is etched using one chemistry, while the adjacent or underlying layer is etched using another chemistry, but in the same process chamber.Type: GrantFiled: December 8, 1997Date of Patent: January 11, 2000Assignee: Applied Materials, Inc.Inventors: Pavel Ionov, Sung Ho Kim, Dean Li
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Patent number: 6009830Abstract: A plasma etch reactor having independent gas feeds above the wafer and either at the sides or below the wafer. Preferably, a carrier gas such as argon is supplied from a showerhead electrode above the wafer while an etching gas is supplied from below. In the case of selectively etching an oxide over a non-oxide layer, the etchant gas should include one or more fluorocarbons.Type: GrantFiled: November 21, 1997Date of Patent: January 4, 2000Assignee: Applied Materials Inc.Inventors: Haojiang Li, Robert W. Wu
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Patent number: 6001268Abstract: The invention is a method of patterning the air bearing surface of a ceramic slider preferably including alumina and titanium carbide. The method includes the steps of forming an etch pattern by depositing and developing a photoresist on the ceramic slider, and reactive ion etching the slider air bearing surface using an etchant gas of argon, sulfur hexafluoride, and methyltrifluoride flowing at a rate which provides a smooth patterned surface on the slider air bearing surface.Type: GrantFiled: June 5, 1997Date of Patent: December 14, 1999Assignee: International Business Machines CorporationInventors: Son Van Nguyen, Diana Perez, Andrew Chiuyan Ting, Cherngye Hwang, Martin Straub, Gerd Dworschak
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Patent number: 5994227Abstract: An improved etching method allowing the formation of a silicon nitride film with an adequate film thickness at the sidewall portion of a pattern is disclosed. A silicon nitride film formed to cover a stepped pattern is dry-etched, employing plasma of mixed gases containing CH.sub.2 F.sub.2 and O.sub.2. As a result, a sidewall spacer of the silicon nitride film is formed at the sidewall of the pattern in a self-aligned manner.Type: GrantFiled: July 20, 1998Date of Patent: November 30, 1999Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering CorporationInventors: Hiroshi Matsuo, Takuji Oda, Yuichi Yokoyama, Kiyoshi Maeda, Shinya Inoue, Yuji Yamamoto
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Patent number: 5993679Abstract: A method of cleaning metallic films built up within a thin film deposition apparatus is disclosed. The method includes an oxidation step to oxidize the metallic film and produce a film of the oxide thereof, a complexing step to complex the oxide film and produce a complex thereof, and a sublimation step to sublimate the complex. The conditions of these cleaning steps are set so that the oxidation step is the rate-determining step.Type: GrantFiled: May 5, 1998Date of Patent: November 30, 1999Assignee: Anelva CorporationInventors: Tomoaki Koide, Akiko Kobayashi, Ko Sang Tae, Atsushi Sekiguchi, Osamu Okada
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Patent number: 5980766Abstract: A method of designing a reactor 10. The present reactor design method includes steps of providing a first plasma etching apparatus 10 having a substrate 21 therein. The substrate includes a top surface and a film overlying the top surface, and the film having a top film surface. The present reactor design method also includes chemical etching the top film surface to define a profile 27 on the film, and defining etch rate data from the profile region. A step of extracting a reaction rate constant from the etch rate data, and a step of using the reaction rate constant in designing a second plasma etching apparatus is also included.Type: GrantFiled: October 2, 1997Date of Patent: November 9, 1999Assignee: Daniel L. FlammInventors: Daniel L. Flamm, John P. Verboncoeur
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Patent number: 5965035Abstract: An oxide etch process that is highly selective to nitride, thereby being beneficial for a self-aligned contact etch of silicon dioxide to an underlying thin layer of silicon nitride. The process uses difluoromethane (CH.sub.2 F.sub.2) for its strong polymer forming and a greater amount of trifluoromethane (CHF.sub.3) for its strong etching, and with a high diluent fraction of argon (Ar). The etch process is performed at a low pressure of about 20 milliTorr in a high-density plasma etching chamber.Type: GrantFiled: October 23, 1997Date of Patent: October 12, 1999Assignee: Applied Materials, Inc.Inventors: Raymond Hung, Jian Ding, Joseph P. Caulfield, Gerald Z. Yin
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Patent number: 5902493Abstract: A method for forming accurate micro patterns having a micro dimension smaller than the resolution of a stepper used on a semiconductor substrate, thereby achieving an improvement in the integration degree of the semiconductor device which is ultimately produced.Type: GrantFiled: November 22, 1996Date of Patent: May 11, 1999Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Sang Man Bae
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Patent number: 5891351Abstract: A method for forming a pattern on a surface of a steel substrate includes the formation of a patterned mask on the surface of the steel substrate. The entire surface having the patterned mask is etched by reactive ion etching such the a pattern is formed on the surface of the steel substrate. The reactive ion etching is brought about by a plasma which is produced in an atmosphere of a chlorine-containing compound, under pressure of 1-100 mTorr, and with a radio frequency power of 100-600 W.Type: GrantFiled: August 13, 1997Date of Patent: April 6, 1999Assignee: National Science CouncilInventors: Chih-Kung Lee, Hong-Zong Liao, Shey-Shi Lu, Nien-Show Ho
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Patent number: 5874011Abstract: Techniques and apparatus for the laser induced etching of a reactive material, or of a multilayer substrate or wafer comprising layers of materials of different etching characteristics and reactivities, are disclosed. Short wavelength laser radiation and control of the process ambient equalize etch rates of the layers of a multilayer substrate or wafer and allow high-resolution etching. A suppressant gas introduced into a halogen-containing ambient suppresses explosive reactions between the ambient and reactive materials or layers. For less reactive layers or materials, reduced-pressure air is a suitable ambient. The techniques and apparatus disclosed herein are particularly useful in the manufacture of magnetic data transfer heads.Type: GrantFiled: August 1, 1996Date of Patent: February 23, 1999Assignee: Revise, Inc.Inventor: Daniel Ehrlich
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Patent number: 5863706Abstract: A processing method is described which has a first step of depositing on a substrate a specimen film which may be any one of a semiconductor, a metal and a insulator.In a second step, the surface of the specimen film deposited in the first step, is irradiated with an ion beam to produce a physical damage on the surface, next, in a third step, the damaged specimen film surface is selectively irradiated with the light to partially cause a photochemical reaction so that a mask pattern, which depends on the desired device structure, is formed on the film surface. Finally, in a fourth step, photoetching is performed using the mask pattern formed in the third step as a shielding member.Type: GrantFiled: April 25, 1995Date of Patent: January 26, 1999Assignee: Canon Kabushiki KaishaInventors: Toshiyuki Komatsu, Yasue Sato, Shin-Ichi Kawate
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Patent number: 5849207Abstract: A method for the plasma etching of a ferrodielectric perovskite oxide thin film such as PZT which comprises providing a resist pattern from on a perovskite oxide thin film as an etching mask, and subjecting the thin film to plasma etching using an etching gas which includes a compound having at least carboxyl group in the molecule, so that the carbonyl group formed by dissociation of the compound having at least carboxyl group in the molecule reacts with constituent metals of the perovskite oxide to efficiently form a reaction product in the form of a metal complex, enabling one to effect plasma etching at a practical etching rate while ensuring good anisotropic processing.Type: GrantFiled: July 1, 1996Date of Patent: December 15, 1998Assignee: Sony CorporationInventor: Junichi Sato
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Planar waveguides made by use of photosensitive changes to the refractive index of a deposited layer
Patent number: 5841928Abstract: Planar waveguides are produced by using radiation to write path regions into a photosensitive layer. Originally, the photosensitive layer had the same refractive index as the confining regions, e.g., it consists of silica doped with oxides of Ge and B. Composite path regions are produced by depositing a glass soot onto a partial region. On sintering the soot melts to fill up the empty spaces and thereby create a composite layer.Type: GrantFiled: March 7, 1997Date of Patent: November 24, 1998Assignee: British Telecommunications public limited companyInventors: Graeme Douglas Maxwell, Benjamin James Ainslie -
Patent number: 5814239Abstract: A gas-phase etchant is provided. The gas-phase etchant includes at least one halogen in gaseous form and/or at least one halogen halide in gaseous form. A Group III-nitride crystal is heated to a temperature in the range of 500.degree.-900.degree. C. and is etched in a flow of the gas-phase etchant. The gas-phase etchant may additionally include hydrogen. The gas-phase etchant may alternatively be diluted with inert gas, and the Group III-nitride crystal may be etched in a flow of the gas-phase etchant diluted with the inert gas.Type: GrantFiled: July 19, 1996Date of Patent: September 29, 1998Assignee: Hewlett-Packard CompanyInventors: Yawara Kaneko, Norihide Yamada
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Patent number: 5804314Abstract: A flexible and efficient bulk micromachining method for fabricating a novel microstructure that is bounded by substantially planar surfaces meeting only at substantially right angle corner features. The novel microstructure of the present invention is useful as a spacer in assembly processes where high accuracy is required, such as precise positioning of optical fibers or conductors. In the preferred embodiment, the microstructure of the present invention includes a shelf feature disposed along a height dimension of the microstructure, which is required for some applications. The bulk micromachining method of the present invention includes providing a first substrate having a top planar surface and an opposing planar surface. The opposing surface of the substrate is anisotropically etched to provide a first thinned region. The top surface of the first substrate is anisotropically etched so that a first recessed feature having a vertical side is made integral with the first thinned region.Type: GrantFiled: March 22, 1994Date of Patent: September 8, 1998Assignee: Hewlett-Packard CompanyInventors: Leslie A. Field, Phillip W. Barth
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Patent number: 5783493Abstract: The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.Type: GrantFiled: January 27, 1997Date of Patent: July 21, 1998Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Rann Shyan Yeh, Chao-Hsin Chang, Hsien-Wen Chang
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Patent number: 5783101Abstract: The plasma source power frequency in a plasma etch reactor is reduced to a low RF frequency such as about 2 MHz. It is a discovery of this invention that at this low frequency, capacitive coupling from the plasma power source is reduced, and the plasma source power level may be increased beyond 750 Watts to reduce capacitive coupling and provide a high density inductively coupled plasma without appreciably increasing the ion bombardment energy. Moreover, under these conditions the etchant (e.g., chlorine) concentration in the plasma may be increased to about 80 percent without decreasing etch uniformity to provide a very high metal alloy etch rate with complete residue removal, no profile microloading, and no etch rate microloading, the process being applicable over a wide window of metal alloy compositions.Type: GrantFiled: September 16, 1994Date of Patent: July 21, 1998Assignee: Applied Materials, Inc.Inventors: Diana Xiaobing Ma, Gerald Zheyao Yin, Hiroji Hanawa
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Patent number: 5783100Abstract: An improved method of high density plasma etching for etching substrates such as semiconductor wafers is provided. The method includes controlling the ratio of ions to neutrals in a high density plasma using an ion filter located in the flow path of the plasma. The ion filter is adapted to interrupt and deflect ions in the plasma while allowing neutrals to pass through to the substrate unaffected. This helps to prevent notching because a more favorable ion/neutral ratio is present at the substrate. At the same time etch selectivity is high, particularly for etching polysilicon to oxide, because current density can remain high.Type: GrantFiled: November 19, 1996Date of Patent: July 21, 1998Assignee: Micron Display Technology, Inc.Inventors: Guy Blalock, Kevin Donohoe
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Patent number: 5770099Abstract: The invention is embodied in a method of operating a plasma etch reactor, consisting of introducing a gas into the reactor which disassociates as a plasma into an etch species which etches oxide films on a work piece in the reactor and a non-etching species combinable with the etch species into an etch-preventing polymer condensable onto the work piece below a characteristic deposition temperature, providing an interior wall comprising a material which scavenges the etching species, and maintaining a temperature of the interior wall above the deposition temperature.Type: GrantFiled: July 18, 1995Date of Patent: June 23, 1998Assignee: Applied Materials, Inc.Inventors: Michael Rice, Jeffrey Marks, David W. Groechel, Nicolas J. Bright
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Patent number: 5741431Abstract: Effective etching of several materials, including gallium nitride and gallium arsenide, without post etch surface damage has been achieved by using a mix of equal proportions of chlorine and methane. A sample is first cooled to a temperature of around 140.degree. K and is then irradiated by a series of pulses from a UV laser (for example a 193 nm ArF excimer laser). Using fluences of about 400 mJ/cm.sup.2 per pulse at repetition rates of about 10 pulses/second, an etch rate for gallium nitride of about 0.7 Angstroms per pulse was achieved. Typical pressure for the chlorine methane mix was about 2 mtorr. To achieve selective etching a number of approaches are possible including contact masking, projection printing, raster scanning, and moveable shadow masking with collimated laser light.Type: GrantFiled: May 15, 1997Date of Patent: April 21, 1998Assignee: Industrial Technology Research InstituteInventor: Ming-Chang Shih
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Patent number: 5719068Abstract: In producing a semiconductor device having GOLD structure, a conductive film containing mainly silicon, tungsten, or/and molybdenum is etched by anisotropic etching using halogen fluoride (such as ClF, ClF.sub.3, BrF, BrF.sub.3, IF, and IF.sub.3) as an etching gas, without producing plasma. In this anisotropic etching, a chamber is maintained to obtain a high vacuum state. Molecular beams of halogen fluoride generated by an evaporator is irradiated into the substrate in a vertical direction (right angle) substantially to the substrate, in order to increase the degree of vertical etching to the substrate than that of horizontal etching. The halogen fluoride are excited by using the RF coil and the RF power source to promote etching.Type: GrantFiled: November 22, 1995Date of Patent: February 17, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Shunpei Yamazaki, Yasuhiko Takemura
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Patent number: 5691117Abstract: It has been discovered that organic photoresists may be quickly, conveniently, and completely stripped using a hot hydrogen atmosphere. The substrates are preferably exposed to such atmosphere utilizing a hydrogen conveyor furnace. The gases from the furnace are burned to carbon dioxide and water thereby eliminating the need to dispose of a stripping agent.Type: GrantFiled: January 17, 1995Date of Patent: November 25, 1997Assignee: International Business Machines CorporationInventors: Rebecca Christine Lutsic, James Richard Murray, David William Sissenstein, Jr.
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Patent number: 5674409Abstract: A nanolithographic method for forming fine features is disclosed. A carrier layer, such as a photoresist, is deposited on a substrate. A relatively large pattern is imposed on the carrier layer by means of conventional photolithographic methods. The carrier layer is then exposed to a maskless etch, such as by ashing in oxygen, such that non-volatile materials within the carrier layer aggregate along the center line of the pattern, forming a residual pattern of significantly reduced width when compared to the original carrier layer pattern.Type: GrantFiled: March 16, 1995Date of Patent: October 7, 1997Assignee: International Business Machines CorporationInventor: K. Paul Ludwig Muller
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Patent number: 5665253Abstract: A tunneling tip sensor and a method of photolithographically fabricating a unitary structure sensor on a semiconductor substrate are disclosed. A cantilever electrode is formed on the substrate with one end suspended above the substrate at a distance from a tunneling electrode so that a tunneling current flows through the cantilever and tunneling electrodes in response to an applied bias voltage. The cantilever and tunneling electrodes form a circuit that produces an output signal. A force applied to the sensor urges the cantilever electrode to deflect relative to the tunneling electrode to modulate the output signal. In the preferred embodiment, the output signal is a control voltage that is applied between the cantilever electrode and a control electrode to maintain a constant tunneling current. In an alternative embodiment, a lateral control electrode is fabricated to produce a lateral motion of the cantilever electrode such that the sensor detects a rotation.Type: GrantFiled: May 31, 1995Date of Patent: September 9, 1997Assignee: Hughes ElectronicsInventors: Randall L. Kubena, Gary M. Atkinson