Etching Inorganic Substrate Patents (Class 216/74)
- Etching of substrate containing at least one compound having at least one oxygen atom and at least one metal atom (Class 216/76)
- Etching of substrate containing elemental aluminum, or an alloy or compound thereof (Class 216/77)
- Etching of substrate containing elemental copper, or an alloy or compound thereof (Class 216/78)
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Patent number: 6887396Abstract: A method is provided for making a micromirror unit which includes a frame, a mirror forming base, and bridges connecting the frame to the mirror forming base. The method includes the following steps. First, a first mask pattern is formed on a substrate for masking portions of the substrate which are processed into the frame and the mirror forming base. Then, a second mask pattern is formed on the substrate for masking portions of the substrate which are processed into the bridges. Then, the substrate is subjected to a first etching process with the first and the second mask patterns present as masking means. Then, the second mask pattern is removed selectively. Then, the substrate is subjected to a second etching process with the first mask pattern present as masking means. Finally, the first mask pattern is removed.Type: GrantFiled: September 13, 2001Date of Patent: May 3, 2005Assignees: Fijitsu Limited, Fujitsu Media Devices LimitedInventors: Osamu Tsuboi, Satoshi Ueda, Yoshihiro Mizuno, Ippei Sawaki, Fumio Yamagishi
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Patent number: 6869879Abstract: A method is provided for forming a conductive interconnect in a semiconductor device. The method comprises forming a dielectric layer above a structure layer, forming a cap layer above the dielectric layer, forming a photoresist layer above the cap layer, and forming an opening in the photoresist layer. A first anisotropic etch is performed into a region of the cap layer underlying the opening in the photoresist layer to form an etched region in the cap layer, leaving a portion of the cap layer in the etched region. The pattern in the photoresist is transferred into the cap layer. The photoresist layer is removed from above the cap layer while the remaining portion of the cap layer in the etched region protects the dielectric layer from damage by the photoresist removal process. A second anisotropic etch is performed to form an opening in the dielectric layer, the opening in the dielectric layer having a sidewall.Type: GrantFiled: November 3, 2000Date of Patent: March 22, 2005Assignee: AdvancedMicro Devices, Inc.Inventor: Errol Todd Ryan
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Patent number: 6858264Abstract: A chemical vapor deposition chamber has a vacuum exhaust line extending therefrom. Material is deposited over a first plurality of substrates within the deposition chamber under conditions effective to deposit effluent product over internal walls of the vacuum exhaust line. At least a portion of the vacuum exhaust line is isolated from the deposition chamber. While isolating, a cleaning fluid is flowed to the vacuum exhaust line effective to at least reduce thickness of the effluent product over the internal walls within the vacuum exhaust line from what it was prior to initiating said flowing. After said flowing, the portion of the vacuum exhaust line and the deposition chamber are provided in fluid communication with one another and material is deposited over a second plurality of substrates within the deposition chamber under conditions effective to deposit effluent product over internal walls of the vacuum exhaust line.Type: GrantFiled: April 24, 2002Date of Patent: February 22, 2005Assignee: Micron Technology, Inc.Inventors: Ross S. Dando, Philip H. Campbell, Craig M. Carpenter, Allen P. Mardian
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Patent number: 6852240Abstract: A ferroelectric capacitor configuration is configured with at least two different coercitive voltages. A first electrode structure having a surface which forms at least two levels is firstly produced. A layer of ferroelectric material of varying thickness is deposited over the first electrode by spin coating. A second electrode structure is subsequently formed on the layer of ferroelectric material.Type: GrantFiled: February 26, 2001Date of Patent: February 8, 2005Assignee: Infineon Technologies AGInventors: Walter Hartner, Günther Schindler, Volker Weinrich, Igor Kasko
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Patent number: 6846427Abstract: A dry etching step during the manufacturing of a substrate for a liquid crystal display (LCD) device is improved by placing the substrate at a predetermined distance away from the lower electrode to prevent damage of the substrate due to electrostatic formed therebetween. An insulating tape attached on the lower electrode provides electrostatic protection between the substrate and the lower electrode, so that the substrate is properly lifted off the lower electrode via the lifting pins of the lower electrode without electrostatic interference.Type: GrantFiled: December 27, 2000Date of Patent: January 25, 2005Assignee: LG. Philips LCD Co., Ltd.Inventor: Byung-Yong Ahn
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Publication number: 20040262264Abstract: A photomask is formed by depositing an opaque layer on a transparent substrate. A resist is formed on the opaque layer and selectively patterned to expose the portions of the opaque layer that are to be etched out. During the dry etching step, the photomask is exposed to an etchant gas mixture which exhibits a selectivity equal to or higher than 1.2:1 between the opaque layer and the resist layer. Due to the selectivity of the gas mixture, a thinner resist film can be used, thereby increasing resolution and accuracy of the opaque layer pattern. Also, due to reduced susceptibility to both a macro-loading effect and a pattern density effect, overetching of the resist and underetching of the opaque layer are significantly reduced, thereby achieving improved etching uniformity and consequently improved CD uniformity.Type: ApplicationFiled: October 28, 2003Publication date: December 30, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shaun B. Crawford, Timothy J. Dalton, Thomas B. Faure, Cuc K. Huynh, Michelle L. Steen, Thomas M. Wagner
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Patent number: 6821450Abstract: A method of forming an opening through a substrate having a first side and a second side opposite the first side includes forming a trench in the first side of the substrate, forming a mask layer within the trench, forming at least one hole in the mask layer, filling the trench and the at least one hole, forming a first portion of the opening in the substrate from the second side of the substrate to the mask layer, and forming a second portion of the opening in the substrate from the second side of the substrate through the at least one hole in the mask layer to the first side of the substrate.Type: GrantFiled: January 21, 2003Date of Patent: November 23, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Martha A. Truninger, Charles C. Haluzak, Michael Monroe
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Patent number: 6810577Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.Type: GrantFiled: February 25, 2003Date of Patent: November 2, 2004Assignee: Murata Manufacturing Co. Ltd.Inventor: Toshikazu Takeda
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Publication number: 20040209172Abstract: In order to enable the correction of clear defects, opaque defects, and Levenson mask glass projection defects using one species of gas, by changing gas pressure and probe current and scanning conditions of the ion beam 2, the diacetone acrylamide is capable of forming a light-blocking film 17 correcting clear defects on a glass substrate 16 and a chrome pattern 15, is capable of removing chrome and glass at a high etching rate, and is capable of eliminating opaque defect regions 18 and eliminating glass projection defect regions 19. It is therefore possible to carry out correction by changing gas supplying conditions and ion beam irradiation conditions according to whether the correction is clear defect correction, opaque defect correction, or Levenson mask glass projection defect correction.Type: ApplicationFiled: March 25, 2004Publication date: October 21, 2004Inventors: Osamu Takaoka, Kazuo Aita, Fumio Aramaki
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Patent number: 6800213Abstract: An oxide etching recipe including a heavy hydrogen-free fluorocarbon having F/C ratios less than 2, preferably C4F6, an oxygen-containing gas such as O2 or CO, a lighter fluorocarbon or hydrofluorocarbon, and a noble diluent gas such as Ar or Xe. The amounts of the first three gases are chosen such that the ratio (F—H)/(C—O) is at least 1.5 and no more than 2. Alternatively, the gas mixture may include the heavy fluorocarbon, carbon tetrafluoride, and the diluent with the ratio of the first two chosen such the ratio F/C is between 1.5 and 2.Type: GrantFiled: June 7, 2002Date of Patent: October 5, 2004Inventors: Ji Ding, Hidehiro Kojiri, Yoshio Ishikawa, Keiji Horioka, Ruiping Wang, Robert W. Wu, Hoiman (Raymond) Hung
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Patent number: 6787054Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.Type: GrantFiled: February 3, 2003Date of Patent: September 7, 2004Inventors: Xikun Wang, Scott Williams, Shaoher X. Pan
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Patent number: 6773616Abstract: Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality.Type: GrantFiled: December 26, 2001Date of Patent: August 10, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yong Chen, Douglas A. A. Ohlberg, Theodore I. Kamins, R. Stanley Williams
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Publication number: 20040146810Abstract: The present invention describes a processes that builds an acoustic cavity, a chamber, and vent openings for acoustically connecting the chamber with the acoustic cavity. The dry etch processes may include reactive ion etches, which include traditional parallel plate RIE dry etch processes, advanced deep and inductively coupled plasma RIE processes. Three embodiments for connecting the chamber to the cavity from the top side of the substrate, e.g. by using pilot openings formed using at least a portion of the mesh as an etch mask, by forming the vent openings using at least a portion of the mesh as an etch mask, or by having the chamber intersect the vent openings as the chamber is being formed, illustrate how the disclosed process may be modified. By forming the cavity on the back side of the substrate, the depth of the vent holes is decreased. Additionally, using at least a portion of the micro-machined mesh as an etch mask for the vent holes makes the process self-aligning.Type: ApplicationFiled: January 23, 2003Publication date: July 29, 2004Inventors: Kaigham J. Gabriel, Xu Zhu
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Patent number: 6764606Abstract: In a plasma processing apparatus according to the present invention, a gas inlet port and a discharge port are provided on a chamber for introducing and discharging gas into and from the chamber respectively. A sample to be etched is placed on an electrode part, so that a high-frequency power source applies a high-frequency bias to the sample. An electromagnet provided on the periphery of a plasma generation area generates a magnetic field while a waveguide connected to an upper potion of the chamber introduces a microwave into the plasma generation area through a microwave introduction window. Electron cyclotron resonance is excited for the gas for generating plasma. At least a surface of the microwave introduction window exposed to the plasma generation area is made of quartz, while the gas contains fluorine. The apparatus having the aforementioned structure can remove a material adhering to the surface of the microwave introduction window when the sample is etched.Type: GrantFiled: February 27, 2001Date of Patent: July 20, 2004Assignee: Tokyo Electron LimitedInventor: Toshihiro Yanase
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Patent number: 6746616Abstract: In one illustrative embodiment, a system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.Type: GrantFiled: March 27, 2001Date of Patent: June 8, 2004Assignee: Advanced Micro Devices, Inc.Inventors: H. Jim Fulford, Jeremy Lansford
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Patent number: 6706465Abstract: A substrate with a negative type photoresist applied rotates and is continuously subjected to surface exposure, heating, and developing/etching/removing the resist each in a dry process. As a result, signal projections are formed onto the surface, which is machined to a stamper size.Type: GrantFiled: August 3, 2000Date of Patent: March 16, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuhiko Sano
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Patent number: 6699399Abstract: A process for etching a substrate 25 in an etching chamber 30, and simultaneously cleaning a thin, non-homogeneous, etch residue deposited on the surfaces of the walls 45 and components of the etching chamber 30. In the etching step, process gas comprising etchant gas is used to etch a substrate 25 in the etching chamber 30 thereby depositing etch residue inside the chamber 30. Cleaning gas is added to the process gas for a sufficient time and in a volumetric flow ratio that is sufficiently high, to react with and remove substantially all the etch residue deposited by the process gas. The present method advantageously cleans the etch residue in the chamber 30, during the etching process, and without use of separate cleaning, conditioning, and seasoning process steps.Type: GrantFiled: September 8, 2000Date of Patent: March 2, 2004Assignee: Applied Materials, IncInventors: Xue-Yu Qian, Zhi-Wen Sun, Weinan Jiang, Arthur Y. Chen, Gerald Zheyao Yin, Ming-Hsun Yang, Ming-Hsun Kuo, David S. L. Mui, Jeffrey Chinn, Shaoher X. Pan, Xikun Wang
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Patent number: 6685848Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing half-tone phase-shift film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a half-tone phase-shift photomask by forming patterns to be transferred to a wafer on a photomask blank for a chromium-containing half-tone phase-shift mask. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.Type: GrantFiled: July 27, 1999Date of Patent: February 3, 2004Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Takaei Sasaki, Noriyuki Harashima, Satoshi Aoyama, Shouichi Sakamoto
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Patent number: 6669858Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: GrantFiled: November 5, 2001Date of Patent: December 30, 2003Assignee: Applied Materials Inc.Inventors: Claes H. Bjorkman, Min Melissa Yu, Hongquing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 6660406Abstract: There are provided an electrodeposited copper foil with carrier that can be used for manufacturing a printed wiring board that excels in the finished accuracy of the resistor circuit in comparison with a conventional printed wiring board with resistor circuits, and a method for manufacturing such a printed wiring board with resistor circuits.Type: GrantFiled: June 20, 2001Date of Patent: December 9, 2003Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Takuya Yamamoto, Takashi Kataoka, Naotomi Takahashi
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Patent number: 6660174Abstract: A method of manufacturing a microstrip termination is provided, the microstrip termination containing a transmission line, a tapered edge ground and a thin film resistor connecting a transmission line to the tapered edge ground. Circuits are manufactured by first cutting holes in a substrate forming alignment holes for dicing the substrate into separate circuits. A saw is then used to cut tapered grooves along the alignment holes for forming tapered edges. The substrate is then plated and etched to form the transmission lines, thin film resistors, and ground planes. Finally, the substrate is diced into the separate termination circuits.Type: GrantFiled: September 21, 2001Date of Patent: December 9, 2003Assignee: Anritsu CompanyInventor: William W. Oldfield
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Patent number: 6656376Abstract: A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.Type: GrantFiled: July 26, 1999Date of Patent: December 2, 2003Assignee: Siemens AktiengesellschaftInventors: Elke Fritsch, Christine Dehm, Hermann Wendt, Volker Weinrich
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Publication number: 20030205553Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Patent number: 6613243Abstract: A method of producing surface features in a substrate includes steps of forming a film having a composition that varies in the direction of its thickness on the substrate, forming a mask on the heterogeneous film, etching the film to thereby pattern the film, and etching the structure that includes the patterned film to erode the film and correspondingly shape the substrate as the film is so being eroded. In this way, the pattern of the film is transferred to the substrate in a manner dependent on the selectivity of one or both of the etching processes as well as the thickness of the discrete mask layers, or in the case of a continuously graded film, the “slope” of the stoichiometric change with respect to position in the overall thickness of the film.Type: GrantFiled: July 25, 2001Date of Patent: September 2, 2003Assignee: Shipley Company, L.L.C.Inventor: Neal Ricks
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Patent number: 6610212Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.Type: GrantFiled: January 29, 2002Date of Patent: August 26, 2003Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, David S. Becker
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Publication number: 20030136758Abstract: There is provided a grating fabrication device and method to form gratings on a semiconductor substrate. The substrate is loaded into a reactor filled with an etchant solution, and an array of parallel light of interference light with different periods is projected onto the substrate to etch the portion of the substrate that is exposed to the light via an oxidation-reduction reaction. At the same time, the inclination angle of the substrate is selectively varied to obtain the different grating periods.Type: ApplicationFiled: January 9, 2003Publication date: July 24, 2003Inventor: Dong-Soo Bang
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Patent number: 6592771Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.Type: GrantFiled: April 7, 2000Date of Patent: July 15, 2003Assignee: Sony CorporationInventors: Hideo Yamanaka, Kikuo Kaise
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Publication number: 20030127422Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.Type: ApplicationFiled: October 30, 2002Publication date: July 10, 2003Inventor: Kazuo Tsuchiya
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Patent number: 6585906Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.Type: GrantFiled: November 26, 2001Date of Patent: July 1, 2003Assignee: International Business Machines CorporationInventors: Dirk Hammel, Holger Roehl, Theo Schmitz, Johannes Windeln
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Patent number: 6585904Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.Type: GrantFiled: February 15, 2001Date of Patent: July 1, 2003Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
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Patent number: 6576151Abstract: The present invention discloses a method for removing silicon nitride from a substrate, characterised in that it comprises contacting said substrate with a molten halogen salt.Type: GrantFiled: September 8, 2000Date of Patent: June 10, 2003Assignee: Internuiversitair Microelektronica CentrumInventors: Guy Vereecke, Marc Meuris
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Patent number: 6576152Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.Type: GrantFiled: July 6, 2001Date of Patent: June 10, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tetsuya Matsutani
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Patent number: 6568067Abstract: The present invention provides a method of efficiently manufacturing a dielectric waveguide with high reliability and precision. In the method, a resist material is formed on the outer surface of a green compact provided with a removal inhibiting layer, and predetermined portion of the green compact defined by the resist material is removed by the sand blasting method using the resist material as a mask, until the removal inhibiting layer is exposed to obtain a shaped green compact structure. The thus-obtained structure is fired to obtain a sintered body which comprises a dielectric strip and a wing.Type: GrantFiled: February 9, 2001Date of Patent: May 27, 2003Assignee: Murata Manufacturing Co., Ltd.Inventor: Toshikazu Takeda
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Patent number: 6547977Abstract: The present disclosure pertains to a method for plasma etching of low k materials, particularly polymeric-based low k materials. Preferably the polymeric-based materials are organic-based materials. The method employs an etchant plasma where the major etchant species are generated from a halogen other than fluorine and oxygen. The preferred halogen is chlorine. The volumetric (flow rate) ratio of the halogen:oxygen in the plasma source gas ranges from about 1:20 to about 20:1. The atomic ratio of the halogen:oxygen preferably falls within the range from about 1:20 to about 20:1. When the halogen is chlorine, the preferred atomic ratio of chlorine:oxygen ranges from about 1:10 to about 5:1. When this atomic ratio of chlorine:oxygen is used, the etch selectivity for the low k material over adjacent oxygen-comprising or nitrogen-comprising layers is advantageous, typically in excess of about 10:1.Type: GrantFiled: July 5, 2000Date of Patent: April 15, 2003Assignee: Applied Materials Inc.Inventors: Chun Yan, Gary C. Hsueh, Yan Ye, Diana Xiaobing Ma
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Publication number: 20030057177Abstract: A method of forming three-dimensional structures on a substrate by a single reactive ion each run whereby a mask is formed on said substrate before a series of iterations are carried out, each iteration including a mask etch and a substrate etch, so that successive iterations give life to reduction in the mask area and exposure of further areas of substrate.Type: ApplicationFiled: July 7, 1998Publication date: March 27, 2003Inventors: DAVID T DUTTON, ANTHONY B DEAN
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Patent number: 6513538Abstract: A method for removing contaminants from an integrated circuit substrate include treating the substrate with a hydrogen peroxide cleaning solution containing a chelating agent, and treating the substrate with hydrogen gas and fluorine-containing gas, and annealing the substrate. Cleaning solutions includes ammonium, hydrogen peroxide, deionized water, and chelating agent. The chelating agent includes one to three compounds selected from the group consisting of carboxylic acid compounds, phosphonic acid compounds, and hydroxyl aromatic compounds. The fluorine-containing gas is a gas selected from the group consisting of nitrogen trifluoride (NF3), hexafluorosulphur (SF6), and trifluorochlorine (ClF3).Type: GrantFiled: May 22, 2001Date of Patent: February 4, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-pil Chung, Kyu-hwan Chang, Young-min Kwon, Sang-lock Hah
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Patent number: 6494959Abstract: A low pressure-high hydrogen flow rate process of cleaning a silicon wafer surface is described. The combination of process pressures below about 1 Torr with hydrogen flow rates up to about 3 SLM has been found to remove substantially all oxygen contamination from the silicon wafer surface at process temperatures less than about 800° C. without the use of a reactive gas. After processing at such process pressures and flow rates, even lower levels of oxygen contamination may be achieved by then increasing the process pressure, the hydrogen flow rate, and the process temperature, though the process temperature still remains less than 800° C. The combination of low pressure and high hydrogen flow rate can be achieved using a vacuum pumping speed of at least 30 cubic meters per hour. The present invention also describes an apparatus for cleaning a silicon wafer surface in which the processes of the present invention and other processes can be practiced.Type: GrantFiled: January 28, 2000Date of Patent: December 17, 2002Assignee: Applied Materials, Inc.Inventors: Arkadii V. Samoilov, Dale R. DuBois, Bradley M. Curelop, David R. Carlson, Paul B. Comita
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Patent number: 6488862Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed “enhanced physical bombardment”. Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.Type: GrantFiled: October 27, 1999Date of Patent: December 3, 2002Assignee: Applied Materials Inc.Inventors: Yan Ye, Diana Xiaobing Ma, Gerald Yin
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Publication number: 20020175141Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.Type: ApplicationFiled: May 22, 2002Publication date: November 28, 2002Inventor: Aaron R. Wilson
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Patent number: 6453914Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.Type: GrantFiled: June 29, 1999Date of Patent: September 24, 2002Assignee: Micron Technology, Inc.Inventors: Kevin J. Torek, Donald L. Yates
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Patent number: 6419845Abstract: It is an object to provide a method of etching which enables measurement control of the micro width of a magnetic layer while shortening the time required for the etching procedure. An inorganic insulating film made of alumina which is the same material as the write gap layer is formed on a top pole layer by, for example, sputtering method. A photoresist film (first mask) is formed on the inorganic insulating film by photolithography. Next, an inorganic insulating mask (second mask) is formed by selectively etching the inorganic insulating film by reactive ion etching (RIE) using gas etchant such as CF4 (carbon ride), BCl3(boron trichloride), Cl2 (chlorine), SF6 (sulfur hexafluoride) and so on using the photoresist film as a mask. The top layer is selectively removed by, for example, ion milling with Ar (argon) using the inorganic insulating mask.Type: GrantFiled: May 24, 1999Date of Patent: July 16, 2002Assignee: TDK CorporationInventor: Yoshitaka Sasaki
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Publication number: 20020084247Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.Type: ApplicationFiled: November 26, 2001Publication date: July 4, 2002Applicant: International Business Machines CorporationInventors: Dirk Hammel, Holger Roehl, Theo Schmitz, Johannes Windeln
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Publication number: 20020084257Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: ApplicationFiled: November 5, 2001Publication date: July 4, 2002Applicant: Applied Materials, Inc.Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Publication number: 20020074309Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.Type: ApplicationFiled: November 5, 2001Publication date: June 20, 2002Applicant: Applied Materials, Inc.Inventors: Claes H. Bjorkman, Melissa Min Yu, Hongqing Shan, David W. Cheung, Wai-Fan Yau, Kuowei Liu, Nasreen Gazala Chapra, Gerald Yin, Farhad K. Moghadam, Judy H. Huang, Dennis Yost, Betty Tang, Yunsang Kim
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Patent number: 6401316Abstract: A method for splitting a piezoelectric device used in substitution for dicing for shortening the processing time as compared to a case of using the dicing to improve productivity to enable the shape of the piezoelectric device more suited to the emission shape of a solution to be achieved, and a method for manufacturing a printer device whereby a narrower nozzle pitch may be achieved. A resist 201 is formed at a pre-set position on a major surface of the piezoelectric device 43 bonded to a vibrating plate. Using this resist 201 as a mask, powders or particles are sprayed onto the piezoelectric device 43 for removing the portion of the piezoelectric device 43 not carrying the resist 201 to form the piezoelectric device 35 of a desired shape at a pre-set position.Type: GrantFiled: February 26, 1998Date of Patent: June 11, 2002Assignee: Sony CorporationInventor: Koichiro Kishima
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Patent number: 6393685Abstract: A wafer level interconnecting mechanism for assembling and packaging multiple MEMS devices (modules), using microfabricated, interlocking, mechanical joints to interconnect different modules and to create miniature devices. Various devices can be fabricated using these joints, including fiber-optic switches, xyz translational stages, push-n-lock locking mechanisms, slide-n-lock locking mechanisms, t-locking joints, fluidic interconnects, on/off valves, optical fiber couplers with xy adjustments, specimen holders, and membrane stops.Type: GrantFiled: June 9, 1998Date of Patent: May 28, 2002Assignee: The Regents of the University of CaliforniaInventor: Scott D. Collins
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Patent number: 6391216Abstract: The invention provides a method for reactive-ion etching a magnetic material with a plasma of a mixed gas of carbon monoxide and a nitrogen-containing compound, the method comprising a step, in which a multilayered film comprising a magnetic material thin film having thereon a resist film formed on a substrate is exposed to an electron beam and then developed, to form a pattern on the resist film, a step, in which a mask material is vacuum deposited, a step, in which the resist is dissolved, to form a mask, and a step, in which a part of the magnetic material thin film that is not covered with the mask is removed by reactive ion etching with a plasma of a mixed gas of carbon monoxide and a nitrogen-containing compound, to form a pattern on the magnetic material thin film, and thus obtaining the magnetic material thin film finely worked.Type: GrantFiled: September 21, 1998Date of Patent: May 21, 2002Assignees: National Research Institute for Metals, Japan Science and Technology CorporationInventor: Isao Nakatani
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Patent number: 6368978Abstract: The present invention is a method for hydrogen-free plasma etching of indium tin oxide using a plasma generated from an etchant gas containing chlorine as a major constituent (i.e., chlorine comprises at least 20 atomic %, preferably at least 50 atomic %, of the etchant gas). Etching is performed at a substrate temperature of 100° C. or lower. The chlorine-comprising gas is preferably Cl2. The etchant gas may further comprise a non-reactive gas, which is used to provide ion bombardment of the surface being etched, and which is preferably argon. The present invention provides a clean, fast method for plasma etching indium tin oxide. The method of the invention is particularly useful for etching a semiconductor device film stack which includes at least one layer of a material that would be adversely affected by exposure to hydrogen, such as N- or P-doped silicon.Type: GrantFiled: March 4, 1999Date of Patent: April 9, 2002Assignee: Applied Materials, Inc.Inventors: Ajay Kumar, Padmapani Nallan, Jeffrey D. Chinn
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Publication number: 20020028359Abstract: A dry etching is performed using a mask made of a titanium nitride under a reaction gas of a carbon monoxide with an additive of a nitrogen containing compound gas.Type: ApplicationFiled: March 26, 2001Publication date: March 7, 2002Applicant: TDK CORPORATIONInventors: Kazuhiro Hattori, Kenji Uchiyama
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Patent number: 6352081Abstract: The present invention is a method for removing deposited etch byproducts from surfaces of a semiconductor processing chamber after a copper etch process. The method of the invention comprises the following general steps: (a) an oxidation step, in which interior surfaces of the processing chamber are contacted with an oxidizing plasma; (b) a first non-plasma cleaning step, in which interior surfaces of the processing chamber are contacted with an H+hfac-comprising gas; and (c) a second cleaning step, in which interior surfaces of the processing chamber are contacted with a plasma containing reactive fluorine species, whereby at least a portion of the copper etch byproducts remaining after step (b) are volatilized into gaseous species, which are removed from the processing chamber. The method of the invention is preferably performed at a chamber wall temperature of at least 150° C.Type: GrantFiled: July 9, 1999Date of Patent: March 5, 2002Assignee: Applied Materials, Inc.Inventors: Danny Chien Lu, Allen Zhao, Peter Hsieh, Hong Shih, Li Xu, Yan Ye