Etching Inorganic Substrate Patents (Class 216/74)
  • Patent number: 7399423
    Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer of a fuel cell so as to be capable of stably producing high purity hydrogen gas.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: July 15, 2008
    Assignee: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Hiroshi Yagi, Takanori Maeda, Yoshinori Oota, Yasuhiro Uchida
  • Patent number: 7396477
    Abstract: An exemplary method for manufacturing a thermal interface material includes the steps of: providing a first substrate having a first surface and an opposite second substrate having an opposite second surface spaced apart a predetermined distance; forming a number of carbon nanotubes from one of the first the second surfaces; forming a composite material by filling interstices between the carbon nanotubes with a liquid state base material; curing the liquid state base material filled in the interstices between the carbon nanotubes; and removing the first and the second substrates from the composite material.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: July 8, 2008
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Bor-Yuan Hsiao
  • Patent number: 7368062
    Abstract: Undoped layers are introduced in the passive waveguide section of a butt-joined passive waveguide connected to an active structure. This reduces the parasitic capacitance of the structure.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 6, 2008
    Assignee: Avago Technologies Fiber IP Pte Ltd
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7365016
    Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: April 29, 2008
    Assignee: DALSA Semiconductor Inc.
    Inventors: Luc Ouellet, Ghislain Migneault, Jun Li
  • Patent number: 7365012
    Abstract: An etching method of subjecting a base material to an etching process using an etching agent containing hydrogen fluoride and ozone is disclosed. The base material has a first region constituted from silicon as a main material and a second region constituted from SiO2 as a main material. The etching method includes the steps of: preparing the base material; and supplying the etching agent onto the base material to form a step between the first and second regions using a feature that an etching rate of silicon by the etching agent is higher than an etching rate of SiO2 by the etching agent, so that the height of the surface of the first region is lower than the height of the surface of the second region.
    Type: Grant
    Filed: August 10, 2005
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Hiroyuki Matsuo, Toshiki Nakajima, Kunihiro Miyazaki
  • Publication number: 20080087633
    Abstract: A method for forming a metal line includes sequentially depositing a low-resistivity metal layer having aluminum on a base substrate and an upper layer having molybdenum on the low-resistivity metal layer, forming a photoresist pattern having a linear shape on the upper layer, etching the upper layer via a mixed gas using the photoresist pattern as a mask, the mixed gas including a chlorine based gas mixed with an additional gas having at least one of nitrogen gas, argon gas, helium gas and sulfur hexafluoride gas, and etching the low-resistivity metal layer using the photoresist pattern as the mask thereby removing any stringer that may be caused by a residue of the low-resistivity metal layer.
    Type: Application
    Filed: October 11, 2007
    Publication date: April 17, 2008
    Inventors: Min-Seok OH, Sang-Gab Kim, Yu-Gwang Jeong, Seung-Ha Choi, Hong-Kee Chin, Shin-II Choi
  • Patent number: 7358192
    Abstract: Embodiments of a cluster tool, processing chamber and method for processing a film stack are provided. In one embodiment, a method for in-situ etching of silicon and metal layers of a film stack is provided that includes the steps of etching an upper metal layer of the film stack in a processing chamber to expose a portion of an underlying silicon layer, and etching a trench in the silicon layer without removing the substrate from the processing chamber. The invention is particularly useful for thin film transistor fabrication for flat panel displays.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: April 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Walter R. Merry, Quanyuan Shang, John M. White
  • Publication number: 20080083701
    Abstract: Methods and apparatus for operating plasmas are described. The vessel receives an oxygen containing plasma to clean and/or condition the vessel.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 10, 2008
    Applicant: MKS Instruments, Inc.
    Inventors: Shou-Qian Shao, Jack Jerome Schuss, John Thomas Summerson, William M. Holber
  • Publication number: 20080067145
    Abstract: A method of recycling dummy wafer is provided. The dummy wafer has at least one low-k dielectric material layer formed thereon. A treatment process is performed to the low-k dielectric material layer on the dummy wafer so that a component or impurity in the low-k dielectric material layer reacts to form a volatile substance. A wet etching process is performed to remove the low-k dielectric material layer.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 20, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chun Wang, Chia-Pin Lee, Chun-Yuan Wu, Hsien-Che Teng, Hsin-Hsing Chen, Yu-Cheng Lin
  • Publication number: 20080050922
    Abstract: A chamber dry cleaning process particularly useful after a dielectric plasma etch process which exposes an underlying copper metallization. After the dielectric etch process, the production wafer is removed from the chamber and a cleaning gas is excited into a plasma to clean the chamber walls and recover the dielectric etching characteristic of the chamber. Preferably, the cleaning gas is reducing such as hydrogen gas with the addition of nitrogen gas. Alternatively, the cleaning gas may an oxidizing gas. If the wafer pedestal is vacant during the cleaning, it is not electrically biased. If a dummy wafer is placed on the pedestal during cleaning, the pedestal is biased. The cleaning process is advantageously performed every wafer cycle.
    Type: Application
    Filed: August 23, 2006
    Publication date: February 28, 2008
    Applicant: Applied Materials, Inc.
    Inventors: Hairong Tang, Xiaoye Zhao, Keiji Horioka, Jeremiah T. P. Pender
  • Publication number: 20080029481
    Abstract: Provided herein are methods for preventing the formation and accumulation of surface-associated charges, and deleterious effects associated therewith, during the manufacture of a MEMS device. In some embodiments, methods provided herein comprise etching a sacrificial material in the presence of an ionized gas, wherein the ionized gas neutralizes charged species produced during the etching process and allows for their removal along with other etching byproducts. Also disclosed are microelectromechanical devices formed by methods of the invention, and visual display devices incorporating such devices.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 7, 2008
    Inventors: Manish Kothari, Jeffrey B. Sampsell
  • Patent number: 7326442
    Abstract: An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1?x?2; 1?y?5; 1?0; m>0; n>0; R is a chromophore, M is a metal selected from Group IIIB to Group VIB, lanthanides, Group IIIA, Group IVA except silicon; and L is an optional ligand. The invention is also directed to a process of making a lithographic structure including a silicon-metal oxide, antireflective material.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: February 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Katherina E. Babich, Sean D. Burns, Elbert E. Huang, Arpan P. Mahorowala, Dirk Pfeiffer, Karen Temple
  • Publication number: 20080017612
    Abstract: The present invention provides a method of fabricating a hinge. First, a wafer is provided, and a hinge region and at least two through regions are defined on the wafer. The wafer in the hinge region is partially removed from a bottom surface of the wafer. Subsequently, the wafer in the through regions is completely removed from a top surface of the wafer, and the hinge is formed. Thereafter, a wafer level test is performed on the hinge of the wafer. Next, an etching process is performed to adjust the shape of the hinge. According to the method of the present invention, the thickness of the hinge is no longer limited by the thickness of the wafer, and the hinge can accept the wafer level test.
    Type: Application
    Filed: November 7, 2006
    Publication date: January 24, 2008
    Inventor: Hsien-Lung Ho
  • Patent number: 7311109
    Abstract: A method for cleaning a processing chamber and manufacturing a semiconductor device by removing impurities from a substrate in the processing chamber with a plasma of a first gas including hydrogen gas. After the substrate is removed from the processing chamber, the processing chamber is etched with the plasma of a non-hydrogenous second gas. Thus, the etching selectivity can be improved and the particles are prevented from depositing and/or forming on the substrate.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 25, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-wook Kim, Hyeon-Deok Lee, Jin-Gi Hong, Ji-Soon Park, Eung-Joon Lee
  • Patent number: 7309448
    Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 18, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hee Yeop Chae, Jeremiah T. P. Pender, Gerardo A. Delgadino, Xiaoye Zhao, Yan Ye
  • Publication number: 20070278181
    Abstract: A manufacturing method of a silicon nozzle plate, having; a film forming process to provide the film representing an etching mask for etching the silicon substrate on a surface of the silicon substrate; a pattern film forming to form a pattern film by partially removing the film based on a nozzle hole forming patter and an outer shape forming pattern; a silicon substrate etching process to form nozzle holes based on the nozzle hole forming pattern representing the etching mask, and to form a half etching portion at least in a part of the silicon substrate based on the outer shape forming patter; and a silicon substrate separating process to separate the silicon substrate by splitting along the half etching portion.
    Type: Application
    Filed: May 25, 2007
    Publication date: December 6, 2007
    Inventors: Kazuhiko Tsuboi, Tohru Hirai
  • Patent number: 7300597
    Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: November 27, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hee Yeop Chae, Jeremiah T. P. Pender, Gerardo A. Delgadino, Xiaoye Zhao, Yan Ye
  • Patent number: 7279108
    Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: October 9, 2007
    Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
  • Publication number: 20070221617
    Abstract: The method of manufacturing a nozzle plate which includes a nozzle having a tapered section and a linear section includes the steps of: forming an etching stopper layer for stopping dry etching of a silicon substrate, on a first surface of the silicon substrate; forming a mask layer on a second surface of the silicon substrate reverse to the first surface; performing a first patterning process with respect to the mask layer so that an opening section is formed in the mask layer; carrying out the dry etching of the silicon substrate through the opening section in the mask layer so that the tapered section of the nozzle is formed in the silicon substrate; carrying out dry etching of the etching stopper layer through the opening section in the mask layer so that at least a part of the linear section of the nozzle is formed in the etching stopper layer; and removing the mask layer.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 27, 2007
    Inventor: Shuji Takahashi
  • Patent number: 7241396
    Abstract: In a through hole closing process, a metal plate is attached to one surface of a conductive base member having a plurality of through holes by the use of a magnet, in a copper plating process, a copper plating layer is formed on the conductive base member and the metal plate exposed within the through holes, from the side of the conductive base member where the metal plate is not attached, thereby to fill up the through holes, in a film forming process, a Pd alloy film is formed by plating on the surface of the conductive base member after removal of the metal plate, and in a removal process, the copper plating layer is removed by selective etching, thereby to produce a hydrogen production filter that is used in a reformer of a fuel cell so as to be capable of stably producing high purity hydrogen gas.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: July 10, 2007
    Assignee: Dai Nippon Insatsu Kabushiki Kaisha
    Inventors: Hiroshi Yagi, Takanori Maeda, Yoshinori Oota, Yasuhiro Uchida
  • Patent number: 7204935
    Abstract: A method of etching a metallic film on a substrate. This method operates to inject an oxidizing agent through the use of a carrier gas to etch a source metal in the presence of a reducing agent such that the rate of etching can be controlled by controlling the flow rate of the carrier gas, the substrate temperature, the pulse widths of the oxidizing and reducing agents, and the number of etching phases.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: April 17, 2007
    Assignee: Oregon Health & Science University
    Inventors: Rajendra Solanki, Balu Pathangey
  • Patent number: 7198727
    Abstract: The present invention provides an optical microbench having intersecting structures etched into a substrate. In particular, microbenches in accordance with the present invention include structures having a planar surfaces formed along selected crystallographic planes of a single crystal substrate. Two of the structures provided are an etch-stop pit and an anisotropically etched feature disposed adjacent the etch-stop pit. At the point of intersection between the etch-stop pit and the anisotropically etched feature the orientation of the crystallographic planes is maintained. The present invention also provides a method for micromachining a substrate to form an optical microbench. The method comprises the steps of forming an etch-stop pit and forming an anisotropically etched feature adjacent the etch-stop pit. The method may also comprise coating the surfaces of the etch-stop pit with an etch-stop layer.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: April 3, 2007
    Assignee: Shipley Company, L.L.C.
    Inventors: Dan A. Steinberg, Larry J. Rasnake
  • Patent number: 7189334
    Abstract: A method of fabricating a plurality of nozzle arrangements for an inkjet printhead chip includes fabricating drive circuitry layers on a substrate with a CMOS fabrication process; depositing a first sacrificial layer on the substrate; depositing a heater layer for forming one or more heating circuits on the first sacrificial layer and etching the heater layer to form the heating circuits; depositing a resiliently flexible layer of dielectric material on the substrate to cover the heater layer and etching the dielectric layer to form one or more actuators and one or more ink ejection members; depositing a second sacrificial layer on the substrate to cover the actuators and the ink ejection members and etching the sacrificial layer to define deposition zones for one or more nozzle chamber walls and one or more roof walls; depositing a layer of a structural material on the second sacrificial layer to form the nozzle chamber walls and the roof walls; and etching away the sacrificial layers.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: March 13, 2007
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7163641
    Abstract: A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 and 40 sccm for CHF3 and between about 10 and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: January 16, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Donohoe, David S. Becker
  • Patent number: 7140374
    Abstract: A method for cleaning a processing chamber that includes heating an inner surface of the processing chamber to a first temperature. The first temperature can be sufficient to cause a first species to become volatile. The first species can be one of several species deposited on the inner surface. A cleaning chemistry is injected into the processing chamber. The cleaning chemistry can be reactive with a second one of the species to convert the second species to the first species. The volatilized first species can also be output from the processing chamber. A system for cleaning the process chamber is also described.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: November 28, 2006
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Shrikant P. Lohokare, Arthur M. Howald, Yunsang Kim
  • Patent number: 7118679
    Abstract: A method of fabricating a sharp protrusion on an underlayer is disclosed. A tip layer is deposited on an underlayer and then a mask layer is deposited on the tip layer. The mask layer is patterned with a beam-and-hat pattern that is used to form a beam-and-hat mask in the mask layer. Portions of the tip layer that are not covered by the beam-and-hat mask are isotropically etched to form a tip including a vertex. Beam portions of the beam-and-hat mask support the hat portion and prevent a release of the hat portion during the isotropic etching process. An anisotropic etch process can be used prior to the isotropic etching process to change a character of the tip. The underlayer can be patterned and etched to form a cantilever that includes the sharp protrusion extending outward of a surface of the cantilever.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: October 10, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Peter G. Hartwell, Uija Yoon
  • Patent number: 7111629
    Abstract: There is provided a surface cleaning apparatus and method using plasma to remove a native oxide layer, a chemical oxide layer, and a damaged portion from a silicon substrate surface, and contaminants from a metal surface. A mixture of H2 and N2 gas is used as a first processing gas. By absorbing potential in a grounded grid or baffle between a plasma generator and a substrate, only radicals are passed to the substrate, and HF gas is used as a second processing gas. Thus a native oxide layer, a chemical oxide layer, or a damaged portion formed on the silicon substrate during etching is removed in annealing step with H2 flow. The environment of a chamber is maintained constant by introducing a conditioning gas after each wafer process. Therefore, process repeatability is improved.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: September 26, 2006
    Assignee: APL Co., Ltd.
    Inventors: Jeong-Ho Kim, Gil-Gwang Lee
  • Patent number: 7105099
    Abstract: A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: September 12, 2006
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Henry Chung, Ming-Chung Liang, An-Chi Wei, Shin-Yi Tsai, Kuo-Liang Wei
  • Patent number: 7098137
    Abstract: A method of making a micro corner cube array includes the steps of: providing a substrate, at least a surface portion of which consists of cubic single crystals and which has a surface that is substantially parallel to {111} planes of the crystals; and dry-etching the surface of the substrate anisotropically with an etching gas that is reactive with the substrate, thereby forming a plurality of unit elements of the micro corner cube array on the surface of the substrate. Each of the unit elements is made up of a number of crystal planes that have been etched at a lower etch rate than the {111} planes of the crystals.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: August 29, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Ihara, Kiyoshi Minoura, Yutaka Sawayama
  • Patent number: 7097776
    Abstract: A low cost method for fabricating microneedles is provided. According to one embodiment, the fabrication method includes the steps of: providing a substrate; forming a metal-containing seed layer on the top surface of the substrate; forming a nonconductive pattern on a portion of the seed layer; plating a first metal on the seed layer and over the edge of the nonconductive pattern to create a micromold with an opening that exposes a portion of the nonconductive pattern, the opening having a tapered sidewall surface; plating a second metal onto the micromold to form a microneedle in the opening; separating the micromold with the microneedle formed therein from the seed layer and the nonconductive pattern; and selectively etching the micromold so as to release the microneedle.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: August 29, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ramesh Govinda Raju
  • Patent number: 7083740
    Abstract: A piezoelectric member and an electrode are formed over a silicon substrate. The piezoelectric member and the electrode are patterned by photolithography. The silicon substrate is etched to form a body. A protective film is formed on at least one surface of the body. Another surface having no protective film thereon is etched to obtain a resonant device. The body is etched in its thickness direction accurately while a resonance frequency of the body is measured. The manufacturing processes allow the resonance frequency and a gap frequency of the resonant device to be adjusted to predetermined values.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: August 1, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Nakatani, Hirofumi Tajika
  • Patent number: 7084072
    Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of the substrate, depositing a nitride spacer layer on the buffer oxide layer, depositing an oxide spacer layer on the nitride spacer layer, forming an oxide spacer at the peripheral region of the substrate, and removing the oxide spacer layer remaining in the cell region. The annealing step is additionally carried out after depositing the buffer oxide layer so as to improve the interfacial surface characteristic and film quality, so that oxide etchant is prevented from penetrating into the silicon substrate during the wet dip process. Unnecessary voids are prevented from being created in the silicon substrate.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: August 1, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Sang Ho Woo, Chang Rock Song, Dong Su Park, Tae Hyeok Lee
  • Patent number: 7071114
    Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: July 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takao Kumihashi, Kazunori Tsujimoto, Shinichi Tachi
  • Patent number: 7060193
    Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: June 13, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Pradeep Yelehanka, Sanford Chu, Chit Hwei Ng, Jia Zhen, Purakh Verma
  • Patent number: 7059335
    Abstract: In a process for treating moulds or mould halves (3) for the production of ophthalmic lenses, in particular contact lenses, the moulds or mould halves (3) are exposed to a plasma at least in the area of their shaping surfaces (310).
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: June 13, 2006
    Assignee: Novartis AG
    Inventor: Michael Rothaug
  • Patent number: 7052622
    Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: May 30, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Robert Z. Bachrach
  • Patent number: 7049051
    Abstract: The present invention describes a processes that builds an acoustic cavity, a chamber, and vent openings for acoustically connecting the chamber with the acoustic cavity. The dry etch processes may include reactive ion etches, which include traditional parallel plate RIE dry etch processes, advanced deep and inductively coupled plasma RIE processes. Three embodiments for connecting the chamber to the cavity from the top side of the substrate, e.g. by using pilot openings formed using at least a portion of the mesh as an etch mask, by forming the vent openings using at least a portion of the mesh as an etch mask, or by having the chamber intersect the vent openings as the chamber is being formed, illustrate how the disclosed process may be modified. By forming the cavity on the back side of the substrate, the depth of the vent holes is decreased. Additionally, using at least a portion of the micro-machined mesh as an etch mask for the vent holes makes the process self-aligning.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: May 23, 2006
    Assignee: Akustica, Inc.
    Inventors: Kaigham J. Gabriel, Xu Zhu
  • Patent number: 7045070
    Abstract: The electrode configuration includes at least one structured layer. A mask is produced on the layer to be structured and the layer is dry etched. The mask is at least slightly etchable by dry etching. The mask contains a metal silicide, a metal nitride or a metal oxide.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventors: Volker Weinrich, Manfred Engelhardt, Werner Pamler, Hermann Wendt
  • Patent number: 7041224
    Abstract: The etching of a material in a vapor phase etchant is disclosed where a vapor phase etchant is provided to an etching chamber at a total gas pressure of 10 Torr or more, preferably 20 Torr or even 200 Torr or more. The vapor phase etchant can be gaseous acid etchant, a noble gas halide or an interhalogen. The sample/workpiece that is etched can be, for example, a semiconductor device or MEMS device, etc. The material that is etched/removed by the vapor phase etchant is preferably silicon and the vapor phase etchant is preferably provided along with one or more diluents. Another feature of the etching system includes the ability to accurately determine the end point of the etch step, such as by creating an impedance at the exit of the etching chamber (or downstream thereof) so that when the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the end point of the removal process can be determined.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: May 9, 2006
    Assignee: Reflectivity, Inc.
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi, Andrew G. Huibers, Peter Heureux
  • Patent number: 7033665
    Abstract: A precision mask for deposition is provided that includes a first brace having a plurlaity of sections placed in parallel to each other at given intervals. The first brace forms portions that define a plurality of first openings. The precision mask for deposition also includes at least one second brace that is placed on the first brace so as to intersect with the first brace. The second brace forms portions that define a plurality of second openings. The second brace is joined to the first brace at a point where the second brace intersects with the first brace.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: April 25, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Shinichi Yotsuya, Takayuki Kuwahara
  • Patent number: 7033515
    Abstract: A method is for manufacturing a microstructure having a thin-walled portion with use of a material substrate. The material substrate has a laminated structure which includes a first conductor layer 101, a second conductor layer 102, a third conductor layer 103, a first insulating layer 104 interposed between the first conductor layer and the second conductor layer, and a second insulating layer 105 interposed between the second conductor layer and the third conductor layer. The first insulating layer is patterned to have a first masking part for covering a thin-wall forming region of the second conductor layer. The second insulating layer is patterned to have a second masking part for covering the thin-wall forming region of the second conductor layer.
    Type: Grant
    Filed: October 17, 2003
    Date of Patent: April 25, 2006
    Assignees: Fujitsu Limited, Fujitsu Media Devices Limited
    Inventors: Norinao Kouma, Yoshihiro Mizuno, Osamu Tsuboi, Hisao Okuda, Hiromitsu Soneda, Satoshi Ueda, Ippei Sawaki, Yoshitaka Nakamura
  • Patent number: 7025896
    Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: April 11, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
  • Patent number: 7008547
    Abstract: Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a single substrate.
    Type: Grant
    Filed: March 7, 2003
    Date of Patent: March 7, 2006
    Assignee: Sarnoff Corporation
    Inventors: Jia Ming Chen, Yongchi Tian, Zilan Shen, Pradyumna Swain
  • Patent number: 6994884
    Abstract: A method of fabricating a support electrode for a solid oxide fuel cell includes (a) providing a solid support electrode having an upper surface, the solid electrode comprising an electronically non-conductive material and an electronically conductive material; (b) applying a mask over the upper surface to create a desired unmasked pattern on the top surface; (c) removing the desired amount of material(s) from the unmasked pattern to a predetermined depth of the support electrode; and (d) removing the mask.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: February 7, 2006
    Assignee: General Electric Company
    Inventors: Jie Guan, Dacong Weng, Vishal Agarwal, Xiwang Qi
  • Patent number: 6995094
    Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.
    Type: Grant
    Filed: October 13, 2003
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Mahender Kumar, Brian Messenger, Michael D. Steigerwalt
  • Patent number: 6984436
    Abstract: In homogeneous materials, etching characteristics depend on properties inherent in these materials regardless of whether they are isotropic or anisotropic, and there have been limitations in realizing various desired shapes. A subject for the invention is to provide a gradient material which eliminates these limitations. A gradient material is provided in which the rate of etching with a specific chemical substance changes continuously or by steps from the outermost surface to an inner part thereof. This gradient material is made of a main material which contains an additive capable of changing the etching rate of the main material so that the concentration of the additive changes continuously or by steps. Especially when a glass material containing SiO2 as the main component is used as the main material and fluorine is used as the additive, then a gradient material in which the rate of etching with an aqueous solution of hydrofluoric acid changes in the depth direction can be obtained.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: January 10, 2006
    Assignees: National Institute of Advanced Industrial Science and Technology, Nippon Sheet Glass Co., Ltd.
    Inventors: Junji Nishii, Tadashi Koyama, Jun Yamaguchi
  • Patent number: 6926843
    Abstract: Lines are fabricated by patterning a hard mask to provide a line segment, the line segment having a first dimension measured across the line segment; reacting a surface layer of the line segment to form a layer of a reaction product on a remaining portion of the line segment; and removing the reaction product without attacking the remaining portion of the line segment and without attacking the substrate to form the line segment with a dimension across the line segment that is smaller than the first dimension.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: August 9, 2005
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, Wesley Natzle, Steven M. Ruegsegger
  • Patent number: 6913704
    Abstract: A magnetic head including a dual layer induction coil. Following the deposition of a first magnetic pole (P1) a first induction coil is fabricated. Following a chemical mechanical polishing (CMP) step a layer of etchable insulation material is deposited followed by the fabrication of a second induction coil etching mask. A reactive ion etch process is then conducted to etch the second induction coil trenches into the second etchable insulation material layer. The etching depth is controlled by the width of the trenches in an aspect ratio dependent etching process step. The second induction coil is next fabricated into the second induction coil trenches, preferably utilizing electrodeposition techniques. Thereafter, an insulation layer is deposited upon the second induction coil, followed by the fabrication of a second magnetic pole (P2) upon the insulation layer.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: July 5, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Richard Hsiao, Yiping Hsiao
  • Patent number: RE39273
    Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresists layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Syun-Ming Jang, Ming-Hsin Huang
  • Patent number: RE40264
    Abstract: The present invention provides a technique, including a method and apparatus, for etching a substrate in the manufacture of a device. The apparatus includes a chamber and a substrate holder disposed in the chamber. The substrate holder has a selected thermal mass to facilitate changing the temperature of the substrate to be etched during etching processes. That is, the selected thermal mass of the substrate holder allows for a change from a first temperature to a second temperature within a characteristic time period to process a film. The present technique can, for example, provide different processing temperatures during an etching process or the like.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: April 29, 2008
    Inventor: Daniel L. Flamm