Abstract: A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: According to one embodiment, a power semiconductor device includes an IGBT region, first and second electrodes, and a first conductivity-type second semiconductor layer. The region functions as an IGBT element. The first electrode is formed in a surface of a second conductivity-type collector layer opposite to a first conductivity-type first semiconductor layer in the region. The second electrode is connected onto a first conductivity-type emitter layer and a second conductivity-type base layer in a surface of the first conductivity-type base layer and insulated from a gate electrode in the region. The first conductivity-type second semiconductor layer extends from the surface of the first conductivity-type base layer to the first conductivity-type first semiconductor layer around the IGBT region, and connected to the first electrode.

Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.

Abstract: Electronic device structures that compensate for non-uniform etching on a semiconductor wafer and methods of fabricating the same are disclosed. In one embodiment, the electronic device includes a number of layers including a semiconductor base layer of a first doping type formed of a desired semiconductor material, a semiconductor buffer layer on the base layer that is also formed of the desired semiconductor material, and one or more contact layers of a second doping type on the buffer layer. The one or more contact layers are etched to form a second contact region of the electronic device. The buffer layer reduces damage to the semiconductor base layer during fabrication of the electronic device. Preferably, a thickness of the semiconductor buffer layer is selected to compensate for over-etching due to non-uniform etching on a semiconductor wafer on which the electronic device is fabricated.

Abstract: Electronic device structures including semiconductor ledge layers for surface passivation and methods of manufacturing the same are disclosed. In one embodiment, the electronic device includes a number of semiconductor layers of a desired semiconductor material having alternating doping types. The semiconductor layers include a base layer of a first doping type that includes a highly doped well forming a first contact region of the electronic device and one or more contact layers of a second doping type on the base layer that have been etched to form a second contact region of the electronic device. The etching of the one or more contact layers causes substantial crystalline damage, and thus interface charge, on the surface of the base layer. In order to passivate the surface of the base layer, a semiconductor ledge layer of the semiconductor material is epitaxially grown on at least the surface of the base layer.

Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract: A housing for a semiconductor device is disclosed. In an exemplary embodiment of the present invention, the housing comprises a semiconductor substrate that is arranged between two contact elements, one contact element forming an anode contact element and another contact element forming a cathode contact element, the semiconductor substrate having, on at least one surface, a gate electrode that is contacted by a gate contact element, the first contact element forming a surface arranged across from the gate electrode and at a distance from the gate electrode. Also included is at least one driver unit for generating a gate current, the driver unit comprising a first terminal that is contacted with the gate contact element, and a second terminal that is contacted with a first of the two contact elements.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

Abstract: Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.

Abstract: A semiconductor device includes a first trench and a second trench extending into a semiconductor body from a surface. A body region of a first conductivity type adjoins a first sidewall of the first trench and a first sidewall of the second trench, the body region including a channel portion adjoining to a source structure and being configured to be controlled in its conductivity by a gate structure. The channel portion is formed at the first sidewall of the second trench and is not formed at the first sidewall of the first trench. An electrically floating semiconductor zone of the first conductivity type adjoins the first trench and has a bottom side located deeper within the semiconductor body than the bottom side of the body region.

Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.

Abstract: An electronic device includes a wide bandgap thyristor having an anode, a cathode, and a gate terminal, and a wide bandgap bipolar transistor having a base, a collector, and an emitter terminal. The emitter terminal of the bipolar transistor is directly coupled to the anode terminal of the thyristor such that the bipolar transistor and the thyristor are connected in series. The bipolar transistor and the thyristor define a wide bandgap bipolar power switching device that is configured to switch between a nonconducting state and a conducting state that allows current flow between a first main terminal corresponding to the collector terminal of the bipolar transistor and a second main terminal corresponding to the cathode terminal of the thyristor responsive to application of a first control signal to the base terminal of the bipolar transistor and responsive to application of a second control signal to the gate terminal of the thyristor. Related control circuits are also discussed.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: In a base region of a first conductivity type, at least one emitter region of a second conductivity type and at least one sense region of the second conductivity type, spaced away from the emitter region, are selectively formed. The emitter region and the sense region are located so as to be aligned in a second direction perpendicular to a first direction going from a collector region of the first conductivity type, which is formed so as to be spaced away from the base region, toward the base region. The width of the sense region, the width of the emitter region, the width of a part of the base region that is adjacent to the sense region, and the width of a part of the base region that is adjacent to the emitter region in the second direction are set in such a manner that a sense ratio varies in a desired manner in accordance with variation in collector current.

Abstract: An insulated gate type thyristor includes: a first current terminal semiconductor region of a first conductivity type having a high impurity concentration; a first base semiconductor region of a second conductivity type opposite to the first conductivity type having a low impurity concentration and formed on the first current terminal semiconductor region; a second base semiconductor region of the first conductivity type having a low impurity concentration and formed on the first base semiconductor region; a second current terminal semiconductor region of the second conductivity type having a high impurity concentration and formed on the second base semiconductor region; a trench passing through the second current terminal semiconductor region and entering the second base semiconductor region leaving some depth thereof, along a direction from a surface of the second current terminal semiconductor region toward the first base semiconductor region; and an insulated gate electrode structure formed in the trench.

Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.

Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: The invention relates to a semiconductor diode, an electronic component and to a voltage source converter. According to the invention, the semiconductor diode having at least one pn-transition can be switched between a first state and a second state. In comparison to the first state, the second state has a greater on-state resistance and a smaller accumulated charge, and the pn-transition is capable of blocking both in the first state as well as in the second state with at least one predetermined blocking ability. An MOS-controlled diode is hereby obtained in which the transition from the on-state to the blocking state is simplified and is thus not critical with regard to the temporal sequence of the control pulses.

Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.

Abstract: An embodiment of an integrated circuit includes a semiconductor layer, a well, first and second source/drain regions, and a guard region. The semiconductor layer has a first conductivity, and the well is disposed in the layer and has a second conductivity. The first source/drain region is formed in the well and has the first conductivity, and the second source/drain region is formed in the layer outside of the well and has the second conductivity. The guard region is disposed in the layer between the well and the second source/drain region and has the second conductivity. The guard region may prevent latch up by inhibiting the triggering of a silicon-controlled rectifier (SCR) having one of the first and second source/drain regions as an anode and the other of the first and second source/drain regions as a cathode.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising.

Abstract: A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.

Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.

Abstract: High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.

Abstract: A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region of a second conductivity type in the substrate is located proximate to and on a side of the cathode region of the first conductivity type opposite from the anode region. A drift region in the semiconductor substrate extends between the anode region and the cathode region of the first conductivity type. An insulated gate is operatively coupled to the cathode region of the first conductivity type and is located on a side of the cathode region of the first conductivity type opposite from the anode region. An insulating spacer overlies the cathode region of the second conductivity type.

Abstract: An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturing the device in which the vertically oriented portion of each L-shaped diffused region is formed by directing dopants at an angle toward a sidewall of a trench to form the vertically oriented portion using the edge of the opposing sidewall of the trench as a mask.

Abstract: A sensor includes a first gate electrode, a second gate electrode, a semiconductor layer, a gate-insulating layer, a source electrode, a drain electrode, and a sensing portion including an accommodating part and a receiving layer. The first and second gate electrodes are opposed to each other with the sensing portion, the semiconductor layer, and the gate-insulating layer therebetween. One surface of the semiconductor layer is in contact with a surface of the sensing portion, and another surface of the semiconductor layer is in contact with the gate-insulating layer. A surface of the gate-insulating layer is in contact with the second gate electrode. The first gate electrode and the receiving layer are opposed to each other with the accommodating part therebetween. The source and drain electrodes are in contact with the semiconductor layer.

Abstract: A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails.

Abstract: A field-effect transistor includes a channel layer formed of a III-V compound semiconductor excluding aluminum; a gate contact layer formed of a III-V compound semiconductor and provided on the channel layer, the III-V compound semiconductor having a dopant concentration equal to or less than 1×1016 cm?3, containing aluminum, and having a large band gap energy; a gate buried layer of a III-V compound semiconductor and provided on the gate contact layer; and a gate electrode buried in the gate buried layer and in contact with the gate contact layer. A recess in the gate buried layer is opposed to an upper side wall of the gate electrode with a gap therebetween and a part of the gate buried layer, and where a contact with a lower side wall of the gate electrode is established, part of the gate buried layer remains without being removed.

Abstract: An electrostatic discharge protection element and a protection resistor, which are formed on an N-drain region with a field oxide film interposed therebetween for the purpose of preventing electrical breakdown of a field effect transistor, are composed as a stacked bidirectional Zener diode of one or a plurality of N+ polycrystalline silicon regions of a first layer and a P+ polycrystalline silicon region of a second layer, and a stacked resistor of one or a plurality of N+ resistor layers of the first layer and an N+ resistor layer of the second layer, respectively. One end of the plurality of N+ polycrystalline silicon regions of the first layer is connected to an external gate electrode terminal, and the other end is connected to a source electrode. One end of the plurality of N+ resistor layers of the first layer is connected to a gate electrode, and the other end is connected to the external gate electrode terminal.

Abstract: A finger length a1 of a transistor P11 is longer than a finger length A1 of a transistor P1, and a finger length b1 of a transistor N11 is longer than a finger length B1 of a transistor N1. The finger length b1 of the transistor N11 is shorter than the finger length A1 of the transistor P1, and the relation: a1>A1>b1>B1 is established. In a relation between an I/O section and a logic circuit section, as for MOS transistor of the same conductive type, a finger length of a MOS transistor constituting the logic circuit section is set so as to be longer than a finger length of a MOS transistor constituting the I/O section.

Abstract: A display substrate includes a plurality of pixel parts, each including a first and second gate lines, a source line, first, second, and third transistors, and a pumping capacitor. A display device includes a display panel, a gate driving part, a source driving part, and an output selecting part. Each pixel part of a display panel includes a transmissive part, a reflective part, and an adjusting part. The adjusting part adjusts the transmission voltage charged in the reflective part to a reflection voltage based on a control voltage. Thus, transmission voltage applied to the transmissive part is adjusted to reflection voltage to be applied to the reflective part. Therefore, optical reflectivity and optical transmissivity versus voltage are matched with each other, while embodying a single cell-gap and applying a single voltage.

Abstract: A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element.

Abstract: A semiconductor wafer to be diced into individual SBDs, HEMTs or MESFETs has a substrate with a main semiconductor region and counter semiconductor region formed on its opposite surfaces. The main semiconductor region is configured to provide the desired semiconductor devices. In order to counterbalance the warping effect of the main semiconductor region on the substrate, as well as to enhance the voltage strength of the devices made from the wafer, the counter semiconductor region is made similar in configuration to the main semiconductor region. The main semiconductor region and counter semiconductor region are arranged in bilateral symmetry as viewed in a cross-sectional plane at right angles with the substrate surfaces.

Abstract: A semiconductor element includes a first semiconductor layer of a first conductivity type including a non-deposition region and a deposition region. The first semiconductor layer has a first upper surface on the non-deposition region. The semiconductor element also includes a second semiconductor layer of a second conductivity type on the deposition region of the first semiconductor layer. The second semiconductor layer has a second upper surface. The semiconductor element includes first and second electrode layers on the first and second semiconductor layers, respectively, which define an inclined surface for continuous connection therebetween. The semiconductor element includes an insulating layer on the inclined surface, spaced from at least either one of the first and second electrode layers. At least either one of the first and second semiconductor layers includes a recessed portion between the respective one of the first and second electrode layers and the insulating layer.

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.

Abstract: Fabrication processes for manufacturing and connecting a semiconductor switching device are disclosed, including an embodiment for dicing a wafer into individual circuit die by sawing the interface between adjacent die with a saw blade that has an angled configuration across its width, preferably in a generally V-shape so that the adjacent die are severed from one another while simultaneously providing a beveled surface on the sides of each separated die. Another embodiment relates to the manner in which damage to a beveled side surface of the individual die can be smoothed by a chemical etching process.

Abstract: The invention relates to a semiconductor circuit (20) having an electrically programmable switching element (10), an “antifuse”, which includes a substrate electrode (2), produced in a substrate (1) which can be electrically biased with a substrate potential (Vo), and an opposing electrode (5) which is isolated from the substrate electrode (2) by an insulating layer (8), where the substrate electrode (2) includes at least one highly doped substrate region (3), and where the opposing electrode (5) can be connected to an external first electrical potential (V+) which can be provided outside of the semiconductor circuit (20). In line with the invention, the substrate electrode (2) can be connected to a second electrical potential (V?), which is provided inside the circuit and which, together with the external first potential (V+), produces a higher programming voltage (V) than the external first potential (V?) together with the substrate potential (Vo).

Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

Abstract: A family of emitter controlled thyristors employ plurality of control schemes for turning the thyristor an and off. In a first embodiment of the present invention a family of thyristors are disclosed all of which comprise a pair of MOS transistors, the first of which is connected in series with the thyristor and a second which provides a negative feedback to the thyristor gate. A negative voltage applied to the gate of the first MOS transistor causes the thyristor to turn on to conduct high currents. A zero to positive voltage applied to the first MOS gate causes the thyristor to turn off. The negative feedback insures that the thyristor only operates at its breakover boundaries of the latching condition with the NPN transistor portion of the thyristor operating in the active region. Under this condition, the anode voltage VA continues to increase without significant anode current increase.

Abstract: The RBSOA of a device is improved. A gate electrode (10) is linked to a p base layer (4) which is formed in a cell region (CR), and a p semiconductor layer (13) is formed to surround the cell region (CR). An emitter electrode (11) is connected to a top surface of a side diffusion region (SD) of the p semiconductor layer (13) and to a top surface of a margin region (MR) which is adjacent to the side diffusion region (SD), through a contact hole (CH). Further, in these regions, an n+ emitter layer (5) is not formed. Most of avalanche holes (H) which are created in the vicinity of the side diffusion region (SD) when a high voltage is applied pass through the side diffusion region (SD), while some of the avalanche holes (H) pass through the margin region (MR) and are then ejected to the emitter electrode (11). Since there is no n+ emitter layer (5) in these paths, a flow of the holes (H) does not conduct a parasitic bipolar transistor. As a result of this, the RBSOA is improved.