Abstract: To provide thermal relief, particularly of the edge of disk-shaped gate-turn-off GTO thyristors (GTO) as are used in converters in power electronics, at least one cooling segment which is isolated from a GTO cathode metallization of the GTO thyristor segment (GTO) by a gate electrode metallization of a gate electrode is arranged on the edge and laterally adjacent to the GTO thyristor segment (GTO). An insulation layer is provided between a cooling segment metallization and the gate electrode metallization. Cooling segments in an lo outer annular zone can be alternately arranged with GTO thyristor segments (GTO) or offset towards the outside in the radial direction or perpendicular direction thereto. Instead of cooling segments, a p.sup.+ -type GTO emitter layer of the GTO thyristor segments (GTO) can be shortened at the edge in the outer annular zone.

Abstract: In order to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance, an n buffer layer (12) is locally exposed on a lower surface of a semiconductor substrate (160), while a polysilicon additional resistive layer (104) is formed to cover the exposed surface. An anode electrode (101) covering the lower surface of the semiconductor substrate (160) is connected to a p emitter layer (11) and the additional resistive layer (104). Thus, the n buffer layer (12) and the anode electrode (101) are connected with each other through the additional resistive layer (104), whereby a gate trigger current is reduced. Thus, turnon loss is reduced and di/dt resistance is increased. At the same time, the withstand voltage and the ON-state resistance are excellent due to provision of the n buffer layer (12).

Abstract: A gate turn-off thyristor including: an n-type emitter semiconductor layer divided into a plurality of n-type areas; a p-type base semiconductor layer which cooperates with the n-type emitter semiconductor layer to form a first main circular surface; an n-type base semiconductor layer; and a p-type emitter semiconductor layer cooperating with the n-type base semiconductor layer to form a second main circular surface. An outer diameter of the p-type emitter semiconductor layer is smaller than that of the n-type emitter semiconductor layer. A first main electrode put in low resistance contact with the n-type emitter semiconductor layer is formed on the first main surface. A second main electrode put in low resistance contact with the p-type emitter layer and the n-type base semiconductor layer is formed on the second main surface. A control electrode is formed in the p-type base semiconductor on the first main surface.

Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Abstract: In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited.

Abstract: An Insulated Gate Bipolar Transistor (IGBT) having a new structure capable of performing a low on-voltage and a high-speed turn-off is provided. A P-type collector region 1 of IGBT is not formed on the entire reverse surface of an N-type base region 2, but formed only on its part, and a metal collector electrode 9 is electrically connected only with the surface to which the P-type collector region 1 exposes. An area of a diffusion window in a collector region is relatively reduced, whereby the impurity concentration of the entire collector region is set at a lower value and hole injection efficiency is decreased. At the same time it is possible to obtain high surface concentration with deep diffusion depth of the collector region required to form a favorable ohmic contact.

Abstract: A semiconductor switching device includes a plurality of adjacent and parallel-connected switching cells in a semiconductor substrate. Each cell includes a thyristor having a floating emitter region and a trench-gate field effect transistor (TFET) for providing turn-on and turn-off control of the thyristor. In one embodiment of the switching device, parasitic thyristor latch-up is suppressed by using a dual-channel TFET which forms both inversion-layer and accumulation-layer channel connections in series between respective floating emitter regions and the cathode contact. In another embodiment, parasitic thyristor latch-up is prevented by joining floating emitter regions of a pair of adjacent cells to thereby eliminate a parasitic P-N-P-N path between the anode and cathode contacts.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.

Abstract: A gate turn-off thyristor having a p-emitter layer in the anode side, an n-base layer, a p-base layer and an n-emitter layer in the cathode side. The n-base layer is composed of a first layer portion adjacent to the p-emitter layer, a second layer portion adjacent to the p-base layer and having a lower impurity concentration than the first layer portion, and is constituted by a structure which alters a travelling path of positive holes injected from the p-emitter layer.

Abstract: An n-buffer layer and an n.sup.- -base layer are formed on a p.sup.+ -anode layer. A p-base layer is formed on the n.sup.- -base layer. The p-base layer has a p-type impurity layer protruding into n.sup.- -base layer. An n-cathode layer, an n.sup.+ -cathode layer and a P+-impurity layer are formed on p-base layer. First trenches are formed through p.sup.+ -impurity later, n-cathode layer and p-base layer. On-gates are formed in the first trenches. Second trenches are formed through p.sup.+ -impurity layer and n-cathode layer with their bottom surfaces located in p-type impurity layer. Off-gates are formed in the second trenches. First and second trenches are preferably formed alternately. Thereby, a voltage-driven thyristor has improved turn-on and turn-off characteristics and a high reliability.

Abstract: High performance GaAs and AlGaAs-based devices and a process enabling the manufacture of new III-V compound technologies are disclosed. The GaAs devices are particularly useful as VLSICs by possessing a high degree of electrical insulation, both vertical and lateral, between closely packed active devices. Essentially, the GaAs devices include a substrate on which is formed, preferably by epitaxial growth or by ion implantation, an active GaAs, or AlGaAs region incorporating, by appropriate doping, the simultaneously therein formed active segments. The active segments are electrically shielded by providing insulating stratums in the active GaAs, AlGaAs region surrounding the active segments. Preferably, the insulating stratums are formed therein by implanting arsenic ions therein so as to form arsenic precipitates. Preferably, a passivated surface layer also is formed in part of the surface of the GaAs, AlGaAs active layer, also preferably by implanting arsenic ions therein.

Abstract: A latch-up free insulated gate transistor includes an anode region electrically connected to an anode contact, a first base region on the anode region, a second base region on the first base region, connected to a cathode contact, an insulating region on the second base region and a field effect transistor on the insulating region, electrically connected between the cathode contact and the first base region. The field effect transistor provides an electrical connection between the first base region and the cathode contact in response to a turn-on bias signal. The insulating region prevents electrical conduction between the second base region and the field effect transistor and, in particular, suppresses minority carrier injection from the second base region to the source of the field effect transistor which is electrically connected to the cathode contact.

Abstract: There is disclosed a semiconductor device wherein a p layer (7) is formed in an isolating portion (Z) and portions (1a, 1b) of an n-type base layer (1) lie on opposite sides of the p layer (7), the upper surfaces of the p layer (7) and the portions (1a, 1b) lying in the same plane as the upper surface of a p layer (3). The presence of the p layer (7) provides for high resistance to breakdown and high formation accuracy of the p layers (2, 3, 7) as compared with a structure in which the isolating portion (Z) lies in the bottom of a the recess, whereby the semiconductor device is less susceptible to short-circuit between the p-type base layer (2) and the p layer (3).

Abstract: A general object of the present invention is to make a maximum controllable current large without exerting adverse effect on other characteristics. In a surface of an n.sup.- layer 2 formed on a p.sup.+ substrate 1, p diffusion regions 3a, 3b and 3c are formed separated by n.sup.+ diffusion regions 4a, 4b and an oxidation film 9. Above the p diffusion regions 3b and 3c, gate electrodes 5a and 5b are formed insulated from the surrounding by an oxidation film 6. An Al-Si electrode 7 is in contact with the p diffusion region 3a and the n.sup.+ diffusion region 4a while a metal electrode 8 is in contact with the p.sup.+ substrate 1. By virtue of interposition of the oxidation film 9, a thyristor consisting of the n.sup.+ diffusion region 4a, p diffusion region 3a, n.sup.- layer 2 and p.sup.+ substrate 1 is prevented from being actuated.

Abstract: The semiconductor substrate of a GTO-Thyristor is structured at a cathode-side such that the cathode electrode lies in a first uppermost level of and in a second level lying there below. A gate contact lies in a third lowest level. Passivation layers extend only over the second and third levels. The cathode electrode also contacts the cathode emitter zone in the second level. It is overlapped there by the passivation layers.

Abstract: A readily manufacturable field controlled thyristor with a first semiconductor region of n-type conductivity, a second semiconductor region of p-type in contact with said first region, a void penetrating through said first and second semiconductor regions, a fourth semiconductor region of n-type forming a channel adjacent to said void, a fifth semiconductor region, of p-type, in contact with said third region. The device has a large tolerance for deviations in process parameter precision and accuracy, which enables the device to be produced at a low cost.

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: An insulated gate thyristor (IGTH) (40,80) that is built on IGBT technology rather than SCR or thyristor technology. The device provides the low on-resistance of a thyristor with the gate turn-on and turn-off capability of an IGBT. The device may be fabricated in a somewhat modified IGBT process, in a cellular (40) or stripe (80) configuration. First the process is modified (by reduced doping) in order to promote (rather than inhibit) latch-up. Second, certain regions (52) are formed without source diffusions to create a lateral MOSFET (T.sub.5) that can turn off the latched IGBT.

Abstract: A four-region semiconductor device (that is a p-n-p-n or n-p-n-p device) including at least one further region utilizes integral FET structure for diverting carriers away from an interior region of the device and shunting them to a main current-carrying electrode of the device, whereby the device is provided with a turn-off capability. The device requires only a small amount of energy for its turn-off control gate, and utilizes a high percentage of its semiconductor body for carrying current through the device. High speed turn-off is achieved in a particular embodiment of the device.

Abstract: To avoid peripheral current-density overshoots in a turn-off power semiconductor device, in particular an MOS-controlled thyristor MCT having a multiplicity of separate MCT cells ((M1, . . . , M3), the unit cells (here: MCT cells (M1, . . . , M3)) are combined in groups to form segments (SE) and are surrounded peripherally by peripheral short-circuit regions (10, 15) which are embedded in the semiconductor substrate (1) from the cathode side and are directly connected to the cathode contact (2). At the same time, the peripheral short-circuit regions (10) are of the same conductivity type as the anode-side emitter layer (8).

Abstract: In a turn off type semiconductor device, an n-type emitter layer is divided into a plurality of elements by trenches. A silicide layer of a high melting point metal is provided on a p-type layer adjacent to the individual elements of the n-type emitter layer on a bottom of each of the trenches. A gate electrode is provided on the associated silicide layer so as to surround the plurality of elements of the n-type emitter layer obtained by the division of the emitter layer. An insulator is filled in each of the trenches dividing the n-type emitter layer surrounded by the gate electrode. A cathode electrode is provided on both the insulators and the n-type emitter layer.

Abstract: An improved insulated gate semiconductor device comprises a high-concentration p-type semiconductor region formed widely enough to protrude over n-type emitter regions without reaching an n-type epitaxial layer over a p-type base region only in first regions wherein the n-type emitter regions are wider than second regions as viewed from the top of the device. A gate threshold voltage V.sub.GE (th) has a relatively high level V.sub.GE (th-High) in the first regions, so that a low collector-emitter saturation voltage V.sub.CE (sat) and a low saturation current I.sub.CE (sat) are achieved. This provides for a high short-circuit tolerance as well as a high latch-up tolerance with low losses.

Abstract: An emitter switched thyristor structure providing on-state current saturation capability is disclosed herein. The thyristor structure includes anode and cathode electrodes, and a remote electrode connected to the cathode electrode. A multi-layer body of semiconductor material has a first surface and includes regenerative and non-regenerative portions each operatively coupled between the anode and cathode electrodes. The regenerative portion includes adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series, wherein the remote electrode is in electrical contact with the second region and the anode electrode is in electrical contact with the fourth region. The emitter-switched thyristor is turned on by applying an enabling voltage to an insulated gate electrode disposed adjacent the first surface such that a conductive channel is created in the non-regenerative portion via modulation of the conductivity therein.

Abstract: An emitter-switched thyristor structure includes a remote turn-off electrode for reducing turn-off time and increasing maximum controllable operating current. The switched thyristor structure further includes anode and cathode electrodes, with the remote electrode being connected to the cathode electrode. A multi-layer body of semiconductor material has a first surface, as well as regenerative and non-regenerative portions each operatively coupled between the anode and cathode electrodes. The regenerative portion includes adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series. Electrical contacts exist between the remote electrode and the second region, as well as between the anode electrode and the fourth region. The thyristor is turned on by applying an enabling voltage to an insulated gate electrode disposed adjacent the first surface such that a conductive channel is created in the regenerative portion via modulation of the conductivity therein.

Abstract: An emitter switched thyristor with buried dielectric layer includes a contiguous P-N-P-N series of semiconductor regions between an anode contact and cathode contact. These regions correspond to an anode region of second conductivity type, a first base region of first conductivity type, a second base region of second conductivity type on the first base region, and a floating emitter region contacting the second base region and forming a P-N junction therewith. In addition, a field effect transistor is also provided between the cathode contact and the floating emitter for controlling turn-on and turn-off. An insulating region is also provided between the cathode region and the second base region and prevents the formation of a parasitic thyristor between the cathode contact and the anode contact. The insulating region preferably includes a buried dielectric layer selected from the group consisting of SiO.sub.2, Si.sub.3 N.sub.4, Al.sub.2 O.sub.3 and MgAl.sub.2 O.sub.4.

Abstract: An MCT (MOS controlled thyristor) including a first outer layer of a first conductivity type whose surface contacts a first major electrode, and a second outer layer at which an MOS structure is disposed, and whose surface contacts a second major electrode. The MCT is provided with a second conductivity type region formed in the first outer layer in such a manner that it contacts the first major electrode, but does not contact an inner layer adjacent to the first layer. The MCT has a low on-resistance, a small turn-off loss, and can prevent a negative resistance phenomenon from occurring.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of an top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: An insulated gate control thyristor including an n-type base region, an insulating layer, gates formed on the insulating layer, first and second windows formed in the insulating layer, p-type emitter layers and n-type cathode layers diffused into the base region from the first windows, and p-type collector layers diffused into the base region from the second windows. The emitter layer and the collector layer are disposed in close proximity to each other under the gate so that a channel is formed which is conducted when the thyristor is turned off. The turn-off of the thyristor speeds up and becomes reliable, and the quality control of the process steps for fabricating the thyristor becomes easier.

Abstract: When bypassing a high voltage surge by externally installing a diode between a collector and a gate and protecting a circuit by turning on an IGBT, it is difficult to select a withstand voltage of the diode, because the withstand voltage of the IGBT must be higher with a certain margin. In the present invention, regions of an inverse conductivity type are formed in a high resistivity layer of an IGBT as in base region, and a transistor is formed together with a collector layer of an inverse conductivity type, which is connected between the collectors of an IGBT to be utilized as a clamping transistor. The breakdown voltage of this transistor is made lower than the breakdown voltage of a bipolar transistor of the IGBT main body. Then when the transistor breaks down, the gate-emitter capacity of the IGBT is charged and the IGBT is turned on, thus absorbing the high energy produced by an abnormal voltage into the chip and increasing the withstand capacity.

Abstract: According to this invention, there is disclosed an insulated gate GTO thyristor comprising a pnpn structure including a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. The thyristor has a first gate electrode contacting the p-type base layer and a second gate electrode formed on a channel region of the p-type base layer through a gate insulating film. An n+-type layer of the n-type emitter layer immediately below a cathode electrode and an n--type layer of the n-type emitter layer contacting the channel region are formed in different manufacturing steps, and an emitter breakdown voltage and the threshold voltage of the second gate electrode are optimally set.

Abstract: A semiconductor device including a semiconductive substrate having first and second opposite surfaces; a thyristor formed on the substrate and including a base layer formed in the first surface of the substrate, a first emitter layer formed in the base layer, a conductive layer electrically connected to the emitter layer to serve as a cathode electrode, a first gate electrode connected to the base layer, a second emitter layer formed in the second surface of the substrate, a drain layer formed in the second emitter layer, a conductive layer for electrically connecting the second emitter layer with said drain layer and for serving as an anode electrode of said thyristor. A metal oxide semiconductor field effect transistor is provided to accelerate the flow of carriers in said thyristor to the anode electrode to turn off said thyristor.