Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first pad, and a second pad. A first opening and a second opening are formed in a first main surface of the first semiconductor layer. The second semiconductor layer is stacked on the first semiconductor layer. The first pad for wire bonding is disposed in the first opening. The second pad on which an alignment mark is formed is disposed in the second opening. A third opening and a fourth opening penetrate the second semiconductor layer. The first opening overlaps the third opening. The second opening overlaps the fourth opening.

Abstract: An object of the present invention is to provide an anisotropic conductive bonding member capable of achieving excellent conduction reliability and insulation reliability, a semiconductor device using the same, a semiconductor package, and a semiconductor device production method. An anisotropic conductive bonding member of the present invention includes an insulating base which is made of an inorganic material, a plurality of conductive paths which are made of a conductive member, penetrate the insulating base in a thickness direction thereof, and are provided in a mutually insulated state, and a pressure sensitive adhesive layer which is provided on a surface of the insulating base, in which each of the conductive paths has a protrusion protruding from the surface of the insulating base, the protrusion of each of the conductive paths is buried in the pressure sensitive adhesive layer, and the pressure sensitive adhesive layer contains a polymer material and an antioxidant material.

Abstract: A method of the present invention includes preparing a substrate having a surface on which a electrode pad is formed, forming a resist layer on the substrate, the resist layer having an opening on the electrode pad, filling conductive paste in the opening of the resist layer; sintering the conductive paste in the opening to form a conductive layer which covers a side wall of the resist layer and a surface of the electrode pad in the opening, a space on the conductive layer leading to the upper end of the opening being formed, filling solder in the space on the conductive layer and removing the resist layer.

Abstract: A touch panel includes a substrate, at least a connecting pad and at least a strengthening sheet. The substrate has a display area and a periphery area around the display area. The connecting pad is disposed in the periphery area. The strengthening sheet is disposed in the periphery area and at an edge of the connecting pad.

Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Abstract: A wafer level package that includes a first wafer; a second wafer facing the first wafer; a plurality of chips between the first wafer and the second wafer and arranged in an array; a plurality of sealing frames at predetermined intervals and surrounding each of the plurality of chips to seal the chips; and a coupling portion which couples opposed corners of respective sealing frames.

Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.

Abstract: A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first portion of the helmet layer. An etch stop layer is deposited on a second portion the helmet layer.

Abstract: The present embodiments provides a chip, including a carrier, a redistribution structure, and multiple packaging function modules, where the multiple packaging function modules each have at least a part wrapped by a colloid, and are fastened to the redistribution structure side by side; the redistribution structure is fastened to the carrier, and the redistribution structure includes one or more redistribution metal layers; the redistribution metal layer communicatively connects the multiple packaging function modules and the carrier. The redistribution structure further includes one or more interconnect metal layers, and the interconnect metal layer is communicatively connected to at least two packaging function modules so as to provide a signal path between the at least two packaging function modules. In the chip, two packaging function modules are placed on the carrier side by side, and a signal path is established between the two packaging function modules by using the redistribution structure.

Abstract: A printed wiring board includes a build-up layer including an insulating layer and a first conductor layer including a component mounting pad, a covering layer formed on the build-up layer such that the covering layer is covering the insulating layer and has opening exposing the pad, a reinforcement layer formed on the covering layer and having cavity exposing the pad and the covering layer, a conductor layer formed on the reinforcement layer such that the conductor layer is on the opposite side of the covering layer on the build-up layer, and a via conductor formed in the reinforcement layer such that the via conductor electrically connects the first conductor layer and conductor layer on the reinforcement layer. The first conductor layer is embedded in the insulating layer forming a surface of the build-up layer such that the first conductor layer has surface exposed on the surface of the build-up layer.

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.

Abstract: A process of forming a semiconductor apparatus is disclosed. The process includes steps of: depositing a first metal layer containing Ni in a back surface of a substrate, plating the back surface of the substrate so as to expose the first metal layer in a portion of the scribe line, depositing a third metal layer on the whole back surface of the substrate, and selectively removing the third metal layer in the portion of the scribe line so as to leave the first metal layer in the scribe line.

Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Abstract: A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer.

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

Abstract: The present disclosure provides methods for fabricating multi-layered electronic architectures in silicon and/or germanium. In particular the disclosure provides an advanced marker design and a methodology for aligning devices on multiple layers of a multi-layered electronic architecture. The disclosure also provides a process for growing a semiconductor material with high quality surfaces.

Abstract: A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.

Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.

Abstract: An apparatus for outputting an internal state of a memory apparatus and a memory system using the apparatus are provided. The apparatus includes a state signal generating circuit that generates a first signal indicating an internal operation state of the memory apparatus, and a state signal output control circuit that receives the first signal and outputs a second signal to an output pad based on a chip enable signal or an initially set function command, or both. The first signal indicates one state from among two states and the second signal indicates one state from among three states.

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Abstract: A fixing method for fixing a terminal to a conductive pattern with a brazing filler metal disposed therebetween includes: a first step of disposing the brazing filler metal on the conductive pattern; a second step of bringing the terminal into contact with the brazing filler metal; and a third step of forming a penetrating hole in the terminal by irradiating a laser beam onto the terminal. In the third step, the laser beam is irradiated onto the terminal in such a manner that the penetrating hole is filled with the brazing filler metal melted by the irradiation of the laser beam.

Abstract: Provided are a semiconductor device including an interposer having a relatively thin thickness without a through silicon via and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an interposer including a redistribution layer and a dielectric layer on a dummy substrate, connecting a semiconductor die to the redistribution layer facing an upper portion of the interposer, encapsulating the semiconductor die by using an encapsulation, removing the dummy substrate from the interposer, and connecting a bump to the redistribution layer facing a lower portion of the interposer.

Abstract: In one embodiment, an implantable biosensor includes a sense antenna comprising a silicon carbide substrate and a radiating electrode formed on the substrate.

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.

Abstract: A semiconductor structure includes a conductive feature on a substrate. A plurality of first dielectric layers are disposed on the conductive feature, and stress directions of at least two of the first dielectric layers are different from one another. A first hole penetrates through the plurality of the first dielectric layers to expose the conductive feature. A first conductive plug conformally covers the first hole and is electrically connected to the conductive feature. A first insulating plug on the first conductive plug fills the first hole.

Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.

Abstract: A film type semiconductor package includes a film substrate; a metal pattern extending a first length in a first direction on the film substrate, having a first width in a second direction perpendicular to the first direction the first length being larger than the first width, and includes a plurality of through holes spaced apart from each other in the first direction; a semiconductor chip including a plurality of pads; and a plurality of bumps spaced apart from each other in the first direction, bonded with the metal pattern, and overlapping the plurality of through holes and connected to the pads of the semiconductor chip.

Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10? to 100?.

Abstract: A semiconductor package includes a substrate, a first electronic component, a film and a package body. The first electronic component is disposed on the substrate and has an upper surface. The film is disposed on the upper surface of the first electronic component. The package body encapsulates the first electronic component and the film.

Abstract: A light emitting device includes a substrate, a light emitting element, a plurality of bumps and a cover member. The bumps are disposed between the substrate and the light emitting element to mount the light emitting element on the substrate. The bumps include a plurality of first bumps bonded to a first electrode of the light emitting element, and a plurality of second bumps bonded to a second electrode of the light emitting element. The first bumps are spaced apart from exposed portions of a first semiconductor layer of the light emitting element. The first bumps include a plurality of large bumps and a plurality of small bumps each having a smaller surface area than each of the large bumps in a plan view. The cover member covers the light emitting element, the bumps, and the substrate.

Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Abstract: In various aspects of the disclosure, a semiconductor device including at least one semiconductor die; a dielectric layer adjoining the semiconductor die; geometric structures formed in the dielectric layer; and a conductive layer deposited over the dielectric layer, wherein the conductive layer is at least partially located over the geometric structures.

Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.

Abstract: An electronic system is provided, including an integrated circuit die having at least 2 bond pads, and a redistribution layer having at least one solder pad including 2 portions separated from each other and configured to provide an electrical connection between each of the 2 portions by a solder ball disposed on the solder pad, and to electrically isolate the 2 portions in an absence of the solder ball on the solder pad, and at least 2 redistribution wires, each connecting a different one of the portions to a different one of the bond pads, a second bond pad being connected via a second redistribution wire to a second portion being dedicated to die testing; and a grounded printed circuit board track, wherein the solder ball is disposed between the solder pad and the track, and neither of the redistribution wires traverses a separation space between the 2 portions.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: A chip packaging method includes forming a first redistribution layer and a first dielectric layer on a first temporary carrier to generate a plurality of first conductive interfaces close to the first temporary carrier, each pair of neighboring first conductive interfaces having a first pitch; forming a second dielectric layer on a first portion of the first redistribution layer and the first dielectric layer so as to cover the first portion of the first redistribution layer and expose a second portion; and forming a second redistribution layer and a third dielectric layer over the second dielectric layer to generate a plurality of second conductive interfaces. A circuitry being formed by at least the first redistribution layer and the second redistribution layer and each pair of neighboring second conductive interfaces has a second pitch larger than the first pitch.

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Abstract: A semiconductor device includes a substrate provided with an electronic device, an interlayer dielectric (ILD) layer formed over the electronic device, a wiring pattern formed on the ILD layer and a contact formed in the ILD layer and physically and electrically connecting the wiring pattern to a conductive region of the electronic device. An insulating liner layer is provided on sidewalls of the contact between the contact and the ILD layer. A height of the insulating liner layer measured from a top of the conductive region of the electronic device is less than 90% of a height of the contact measured between the top of the conductive region and a level of an interface between the ILD layer and the wiring pattern.

Abstract: A method comprises depositing a first dielectric layer over a first chip comprising a plurality of first active circuits and a first connection pad, patterning the first dielectric layer to form a first opening, filling the first opening to form a connector in contact with the first connection pad, depositing a second dielectric layer over the first dielectric layer, patterning the second dielectric layer to form a second opening over the connector, filling the second opening to form a first bonding pad in contact with the connector, stacking a second chip on the first chip, wherein the second chip comprises a plurality of second active circuits and a second bonding pad and bonding the first chip and a second chip together to form a stacked semiconductor device through applying a hybrid bonding process to the first bonding pad and the second bonding pad.

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

Abstract: The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.

Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Abstract: A module, comprising an electronic component having a first electrode, a mounting board having a second electrode, a solder-bump configured to connect the first electrode and the second electrode, and a thermoplastic resin member configured to contact both the first electrode and the second electrode and cover the solder-bump, so as to form a space between the electronic component and the mounting board.

Abstract: Provided is a highly conductive crystalline multilayer structure including a corundum-structured crystalline oxide thin film whose resistance has not increased even after annealing (heating). The crystalline multilayer structure includes a base substrate and the corundum-structured crystalline oxide thin film disposed directly on the base substrate or with another layer therebetween. The crystalline oxide thin film is 1 ?m or more in a thickness and 80 m?cm or less in an electrical resistivity. A semiconductor device includes the crystalline multilayer structure.

Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.