Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

Abstract: A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.

Abstract: A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted on a top surface and a bottom surface of the main PCB. Each of the first and second semiconductor packages has a surface on which connection pads corresponding to a package ball map are disposed. The package ball map includes cells arranged in a plurality of rows and a plurality of columns, and one signal corresponds to each of the cells of the package ball map. The package ball map includes first signals corresponding to at least some of cells included in a selected reference column from among the plurality of columns, and at least one pair of second signals respectively corresponding to cells that are symmetrical to each other with respect to the reference column. The pair of second signals are swappable signals, and the first signals are not swappable signals.

Abstract: Integrated circuit dies are provide with a passivation layer having a plurality of differently sized openings exposing bond pads for bonding. The sizes of the bond pads vary in a manner that at least partially compensates for stresses during bonding, such as flip chip thermocompression bonding, due to asymmetric distribution of bond pads.

Abstract: A liquid election head includes a recording element substrate, an electrical wiring substrate configured to supply an electrical signal to the recording element substrate, a plurality of wires electrically connecting a plurality of electrode terminals on the recording element substrate with a plurality of connection terminals on the electrical wiring substrate, and a sealant sealing an electrical connection portion. The plurality of wires form a wire array. At least one of the plurality of wires positioned at one end of the wire array in a wire array direction is shorter than the other wires in the wire array.

Abstract: An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

Abstract: A flame retardant filler having brominated silica particles, for example, imparts flame retardancy to manufactured articles such as printed circuit boards (PCBs), connectors, and other articles of manufacture that employ thermosetting plastics or thermoplastics. In this example, brominated silica particles serve both as a filler for rheology control (viscosity, flow, etc.) and a flame retardant. In an exemplary application, a PCB laminate stack-up includes conductive planes separated from each other by a dielectric material that includes a flame retardant filler comprised of brominated silica particles. In an exemplary method of synthesizing the brominated silica particles, a monomer having a brominated aromatic functional group is reacted with functionalized silica particles (e.g., isocyanate, vinyl, amine, or epoxy functionalized silica particles).

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.

Abstract: A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate and a source/drain region in the semiconductor substrate on each side of the dummy gate structure. The top surface of the dummy gate structure is leveled with the top surface of the first dielectric layer. The method then includes forming an etch stop sidewall in the first dielectric layer on each side of the dummy gate structure, forming a first trench by removing the dummy gate structure, and forming a metal gate structure to partially fill the first trench. The top portion of the first trench becomes a second trench. Further, the method also includes forming an etch stop layer by filling the second trench, and then forming a contact plug in the first dielectric layer to electrically connect to each source/drain region.

Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.

Abstract: A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.

Abstract: Provided is a tape for electronic devices with lead crack and a method of manufacturing the tape. According to the present invention, by forming a cutting portion on a narrow circuit pattern to be connected from an inner lead to an outer lead and further forming the cutting portion within a resin application portion, the problem of occurrence of cracks along a width of a narrow wiring can be avoided. The tape may include a first lead and a second lead formed on a dielectric substrate and a cutting portion formed on one of the first lead and the second lead wherein the cutting portion is formed within a resin application portion.

Abstract: A surface-mountable optoelectronic component has a radiation passage face, an optoelectronic semiconductor chip and a chip carrier. A cavity is formed in the chip carrier and the semiconductor chip is arranged in the cavity. A molding surrounds the chip carrier at least in places. The chip carrier extends completely through the molding in a vertical direction perpendicular to the radiation passage face.

Abstract: An integrated sense resistor within an integrated circuit (IC) may be surroundingly positioned near and coupled to a connection such as a pin or ball. The integrated sense resistor may be shaped such that more surface area of the integrated sense resistor is coupled to be positioned closer or in actual contact with the pin or ball than conventional straight layered integrated sense resistor solutions. The integrated sense resistor may be a non-straight shape that entirely surrounds or wraps around a connection to the pin or ball, such as a circular or oval shape, a box or rectangular shape, a triangular shape, or a polygonal shape. The integrated sense resistor may be a non-straight shape that partially surrounds a connection to the pin or ball, such as an open-circular or semi-circular shape, an open-sided box or rectangular shape, an open-sided triangular shape, an angular shape, or an open curved shape.

Abstract: Personal diagnostic devices including diagnostic patches (bio-patches) and interactive medical bracelets (bio-bracelets) are provided with a skin/patch interface, at least one analysis layer, a signal processing layer, and a user output interface. Embodiments of the interactive diagnostic devices may include micro-fluidic circuits with reaction chambers, analysis chambers, mixing cambers, and various pre-disposed chemistries or reagents for performing a wide verity of tests by transdermal transport of blood or perspiration. Sample collection chambers for the fluidic circuit may include minimally invasive tubules that penetrate the skin surface to acquire blood samples from capillaries near the epidermis. Alternate implementations of the personal diagnostic device may be equipped with logic processing, input/output devices, acoustic microphones, cryogenic circuits, embedded processors, electrical control circuitry, and battery current sources or photovoltaic sources of electrical power.

Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride based transistor arranged on a front surface of the substrate, and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the substrate, and conductive material extending from the front surface to the rear surface of the substrate. The via tapers from the front surface to the rear surface of the substrate.

Abstract: A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.

Abstract: A system of producing metal cored solder structures on a substrate includes: a decal having a plurality of apertures, the apertures being tapered from a top surface to a bottom surface of the decal; a carrier configured for positioning beneath the bottom of the decal, the carrier having cavities in a top surface and the cavities located in alignment with the apertures of the decal; the decal being configured for positioning on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities, the feature cavities being shaped to receive a plurality of metal elements therein, the feature cavities configured for receiving molten solder being cooled in the cavities, the decal being separable from the carrier to partially expose metal core solder contacts; and receiving elements of a substrate being configured to receive the metal core solder contacts thereon, and the metal core solder contacts being exposed and pos

Abstract: A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires and applying an electrical field over the population of nanowires, whereby an electrical dipole moment of the nanowires makes them align along the electrical field. Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate. The electrical field can be utilized in the deposition. Pn-junctions or any net charge introduced in the nanowires may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.

Abstract: A transient voltage suppressor (TVS) apparatus includes a plurality of input/output (I/O) pins, a plurality of ground pins, and a substrate. The substrate includes a plurality of division parts and a carrier part. The carrier part carries a chip. The division parts are disposed between each of the I/O pins and the ground pins. The chip is electrically connected to the I/O pins and the ground pins, and the division parts are electrically insulated from the I/O pins and the ground pins.

Abstract: A first sealant for sealing a region under an electrical connection portion and a second sealant for sealing a region on the electrical connection portion are used as sealants for the electrical connection portion for connecting an electric wiring member to an ejection energy generation element of a liquid ejection head, these sealants contain the same base agent and curing agent, and the linear expansion coefficients of the first sealant and the second sealant after curing are adjusted so as to become in a predetermined range.

Abstract: In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.

Abstract: A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

Abstract: The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. The method comprises: Preparing a semiconductor chip 6 with a first electrode layer 21 formed on an element-forming surface 7. Prepared a support member 30 having a conductor 31 formed on a pattern-forming surface 33. The first electrode layer 21 is bonded to the conductor 31 by a solder, and thus the semiconductor chip 6 is fixed on the support member 30. While the semiconductor chip 6 is fixed on the support member 30, the semiconductor chip 6 is coated by the sealing resin 3 to form a sealing structure 46. By removing the support member 30 from the sealing structure 46, the conductor 31 formed on the support member 30 is transferred to the sealing structure 46. The conductor 31 transferred to the sealing structure 46 is an external electrode exposed from the sealing structure 46.

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

Abstract: A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k material having porosity. A damage curing layer is formed on an inner surface of the recess. A barrier pattern is formed on the damage curing layer. A copper structure fills the recess and is disposed on the barrier pattern. The copper structure includes a copper pattern and a copper-manganese capping pattern covering a surface of the copper pattern. A diffusion of metal in a wiring structure of the semiconductor device may be prevented, and thus a resistance of the wiring structure may decrease.

Abstract: A method of making a semiconductor device includes disposing a first hard mask (HM), amorphous silicon, and second HM on a substrate; disposing oxide and neutral layers on the second HM; removing a portion of the oxide and neutral layers to expose a portion of the second HM; forming a guiding pattern by selectively backfilling with a polymer; forming a self-assembled block copolymer (BCP) on the guiding pattern; removing a portion of the BCP to form an etch template; transferring the pattern from said template into the substrate and forming uniform silicon fin arrays with two types of HM stacks with different materials and heights; gap-filling with oxide followed by planarization; selectively removing and replacing the taller HM stack with a third HM material; planarizing the surface and exposing both HM stacks; and selectively removing the shorter HM stack and the silicon fins underneath.

Abstract: A solar cell receiver for use in a concentrating solar system which concentrates the solar energy onto a solar cell for converting solar energy to electricity. The solar cell receiver may include a solar cell mounted on a support and with one or more III-V compound semiconductor layers. An optical element may be positioned over the solar cell and have an optical channel with an inlet that faces away from the solar cell and an outlet that faces towards the solar cell. A frame may be positioned over the support and extend around the solar cell with the frame having an inner side that extends above the support and faces towards the optical element. An encapsulant may be positioned over the support and contained between the optical element and the frame. The encapsulant may have enlarged heights at contact points with the optical element and the frame and a reduced height between the contact points away from the optical element and the frame. The solar cell receiver may be used in a solar cell module.

Abstract: A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD) layer, filling a remaining portion of the trench with a sacrificial material, depositing a buffer layer on the first ILD layer, patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material.

Abstract: A method for fabricating a substrate having an electrical interconnection structure is provided, which includes the steps of: providing a substrate body having a plurality of conductive pads and first and second passivation layers sequentially formed on the substrate body and exposing the conductive pads; forming a seed layer on the second passivation layer and the conductive pads; forming a first metal layer on each of the conductive pads, wherein the first metal layer is embedded in the first and second passivation layers without being protruded from the second passivation layer; and forming on the first metal layer a second metal layer protruded from the second passivation layer. As such, when the seed layer on the second passivation layer is removed by etching using an etchant, the etchant will not erode the first metal layer, thereby preventing an undercut structure from being formed underneath the second metal layer.

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.

Abstract: A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

Abstract: Provided are a positive electrode for a lithium-sulfur secondary battery and a method of forming the same, the positive electrode being capable of maintaining battery characteristics such as a specific capacity and a cycling characteristic while achieving a high rate characteristic in particular when being applied to a lithium-sulfur secondary battery. A positive electrode of a lithium-sulfur secondary battery includes a positive electrode current collector and carbon nanotubes grown on a surface of the positive electrode current collector and oriented in a direction orthogonal to the surface. At least the surface of each of the carbon nanotubes is covered with sulfur with a certain interstice left between neighboring ones of the carbon nanotubes.

Abstract: A thermoelectric device may include a housing that may have a first housing element and a second housing element. The first housing element and the second housing element may each be composed of an electrically conductive material. At least two thermoelectric elements may be arranged between the first housing element and the second housing element. The at least two thermoelectric elements may be arranged at a distance from each other and may be electrically connected via at least one conductor bridge. A first electrical insulator may be arranged between the at least two thermoelectric elements and the first housing element. A second electrical insulator may be arranged between the at least two thermoelectric elements and the second housing element.

Abstract: A semiconductor device includes a first semiconductor chip having a first surface with a semiconductor element and a second surface opposing the first surface. A first metal layer has a third surface supporting the first semiconductor chip and a fourth surface opposing the third surface. The third surface is larger than the second surface. A resin layer has a fifth surface facing the first semiconductor chip and a sixth surface facing the first metal layer. A pad is on the first surface of the first semiconductor chip. A first via contact is within the resin layer on the third surface of the first metal layer. A second via contact is within the resin layer on the pad. The first and second via contacts are connected to first and the second interconnects, respectively.

Abstract: A wafer-level pulling method includes securing a top holder to a plurality of chips; and securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The wafer-level pulling method further includes softening the plurality of solder bumps; and stretching the plurality of softened solder bumps.

Abstract: A method of processing a semiconductor substrate is provided. The method may include forming a film over a first side of a semiconductor substrate, forming at least one separation region in the semiconductor substrate between a first region and a second region of the semiconductor substrate, arranging the semiconductor substrate on a breaking device, wherein the breaking device comprises a breaking edge, and wherein the semiconductor substrate is arranged with the film facing the breaking device and in at least one alignment position with the at least one separation region aligned with the breaking edge, and forcing the semiconductor substrate to bend the first region with respect to the second region over the breaking edge until the film separates between the breaking edge and the at least one separation region.

Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.

Abstract: The present invention provides a method to manufacture nanowires. In various embodiments, a method is provided for producing an oxidized metal layer as a heterogeneous seed layer on arbitrary substrate for controlled nanowire growth is disclosed which comprises depositing a metal layer on a substrate, oxidizing the metal layer in air ambient or in oxidizing agent, and growing nanowires at low temperatures on oxidized metal layers on virtually any substrate.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: The application relates to a method for determining a bonding connection (1) in a component arrangement (2), wherein the method has the following steps: producing a bonding connection (1) between a bonding section (3) of a bonding wire (4) and a metallic contact point (5), structuring a top-side surface of the bonding wire (4) in the region of the bonding section (3) and determining the bonding connection (1), wherein in this case a test voltage is applied to the bonding wire (4) and the bonding connection (1) so that the bonding connection (1) heats up owing to the current flow, generating a thermogram for the heated bonding connection (1) and determining whether the bonding connection (1) has been produced correctly by evaluating the thermogram. Furthermore, the application relates to a test apparatus for determining a bonding connection (1) in a component arrangement (2).

Abstract: An air vent is formed in a substrate of an electronic device such that air in a cavity of a metal mold can be released through the air vent when a resin is molded. Solder resist is disposed on a second surface of the substrate and has an opening portion at a position corresponding to the air vent. As such, the air can be also released from a clearance between a lower mold and the solder resist resulting from a rough surface of the solder resist. The resin can be held in a space provided between the second surface of the substrate and the lower mold. Therefore, the resin having passed through the air vent can be restricted from flowing out, and the air vent can be restricted from losing its function due to the substrate and the metal mold closely contacting with each other.

Abstract: A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

Abstract: A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face the partition block, and first lines extending from the partition block to the first open region. A spacer is formed on sidewalls of the partition to define a second open region overlapping with the first open region and to include second lines on sidewalls of the first lines. The partition may be removed to open a third open region occupied by the partition block and spaces between the second lines. A target pattern is formed to include third lines filling the spaces between the second lines, a first pad block filling the second open region, and a second pad block filling the third open region. Each of the first and second pad blocks is separated into a plurality of pads.

Abstract: According to one embodiment, a semiconductor module comprises a substrate, a first wiring, an electrode pad, a junction, an oscillator, and a detector. The first wiring is disposed on the substrate, and has a characteristic impedance Z0. The electrode pad is connected to the first wiring. The junction is disposed on the electrode pad, and has an impedance Z1. The oscillator is disposed in contact with the first wiring, and oscillates a pulse wave of a voltage toward the junction via the first wiring. The detector is disposed in contact with the first wiring, and detects an output wave of the pulse wave from the junction. The characteristic impedance Z0 and the impedance Z1 satisfy a following relationship (1), ? Z ? ? 0 - Z ? ? 1 Z ? ? 0 ? ? 0.05 .

Abstract: An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

Abstract: A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.