Abstract: A method of removal of a first and second sacrificial layer wherein an O2 plasma or an O2-containing environment is introduced to a cavity and a gap region through a plurality of via holes in a cavity capping material.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.

Abstract: An IR source in the form of a micro-hotplate device including a CMOS metal layer made of at least one layer of embedded on a dielectric membrane supported by a silicon substrate. The device is formed in a CMOS process followed by a back etching step. The IR source also can be in the form of an array of small membranes—closely packed as a result of the use of the deep reactive ion etching technique and having better mechanical stability due to the small size of each membrane while maintaining the same total IR emission level. SOI technology can be used to allow high ambient temperature and allow the integration of a temperature sensor, preferably in the form of a diode or a bipolar transistor right below the IR source.

Abstract: Disclosed herein is an inertial sensor. The inertial sensor includes a sensor unit including a flexible substrate part on which a driving electrode and a sensing electrode are formed, a mass displaceably mounted on the flexible substrate part, and a support body coupled with the flexible substrate part in order to support the mass in a floated state and made of silicon; and a lower cap covering a bottom portion of the mass and made of silicon, wherein the lower cap and the sensor unit are coupled by a silicon direct bonding method, whereby the inertial sensor and the method of manufacturing the same may be obtained to improve the convenience in manufacturing and the reliability of the sensor by bonding the sensor unit and the lower cap by the silicon direct bonding method.

Abstract: An ink jet print head front face or nozzle plate having a textured superoleophobic surface that prevents undesirable drooling, wetting and/or adhesion of the ink on the print head. The textured surface includes a rim formed around the nozzle. Also described are methods for forming the textured superoleophobic ink jet print head front face or nozzle plate from silicon having the textured, oleophobic surface.

Abstract: A magnetic junction usable in a magnetic memory and a method for providing the magnetic memory are described. The method includes providing a pinned layer, providing an engineered nonmagnetic tunneling barrier layer, and providing a free layer. The pinned layer and the free layer each include at least one ferromagnetic layer. The engineered nonmagnetic tunneling barrier layer has a tuned resistance area product. In some aspects, the step of providing the engineered nonmagnetic tunneling barrier layer further includes radio-frequency depositing a first oxide layer, depositing a metal layer, and oxidizing the metal layer to provide a second oxide.

Abstract: A magnetostrictive-piezoelectric multiferroic single- or multi-domain nanomagnet whose magnetization can be rotated through application of an electric field across the piezoelectric layer has a structure that can include either a shape-anisotropic mangnetostrictive nanomagnet with no magnetocrystalline anisotropy or a circular nanomagnet with biaxial magnetocrystalline anisotropy with dimensions of nominal diameter and thickness. This structure can be used to write and store binary bits encoded in the magnetization orientation, thereby functioning as a memory element, or perform both Boolean and non-Boolean computation, or be integrated with existing magnetic tunneling junction (MTJ) technology to perform a read operation by adding a barrier layer for the MTJ having a high coercivity to serve as the hard magnetic layer of the MTJ, and electrical contact layers of a soft material with small Young's modulus.

Abstract: A method of fabricating a MEMS composite transducer includes providing a substrate having a first surface and a second surface opposite the first surface. A transducing material is deposited over the first surface of the substrate. The transducing material is patterned by retaining transducing material in a first region and removing transducing material in a second region. A polymer layer is deposited over the first region and the second region. The polymer layer is patterned by retaining polymer in a third region and removing polymer in a fourth region. A first portion of the third region is coincident with a portion of the first region and a second portion of the third region is coincident with a portion of the second region. A cavity is etched from the second surface to the first surface of the substrate.

Abstract: Fabrication methods are provided for a sensor device packages. An exemplary fabrication method involves bonding a sensor structure and another structure using a sealing structure. The sealing structure surrounds a diaphragm region of the sensor structure and provides an airtight seal between the sensor structure and the other structure to establish a fixed reference pressure on one side of the diaphragm region.

Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.

Abstract: A susceptor for supporting a semiconductor wafer during deposition of a layer on a front side of the semiconductor wafer, the semiconductor wafer having a diameter D and, at its edge, a notch having a depth T, comprising: a ring-shaped placement area having an internal diameter d for the placement of the semiconductor wafer in the edge region of a rear side of the semiconductor wafer, wherein, with the semiconductor wafer having been placed, the relationship (D?d)/2<T is satisfied; and a protrusion of the area for the placement of semiconductor wafer in the region of the notch of the semiconductor wafer extending the placement area inward, and which completely underlays the notch of the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the third dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

Abstract: Disclosed herein is an inertial sensor, which includes a diaphragm having a piezoelectric element or a piezoresistive element formed on one surface thereof, a mass element integrated with the center of the other surface of the diaphragm in which the distal end of the mass element has a larger width than the width of the proximal end in contact with the diaphragm, and a supporter formed along the edge of the other surface of the diaphragm, so that the use of the mass element having the above shape results in decreased spring constant and increased distance from the center of the diaphragm to the center of the mass element, thereby simultaneously realizing a reduction in the size of the inertial sensor and an increase in performance thereof. A method of manufacturing the inertial sensor is also provided.

Abstract: A method of manufacturing a waveguide within a substrate by local modification of material structure under high power density laser radiation applied from the mostly distant side of the substrate.

Abstract: The sensor assembly comprises a substrate (1), such as a flexible printed circuit board, and a sensor chip (2) flip-chip mounted to the substrate (1), with a first side (3) of the sensor chip (2) facing the substrate (1). A sensing area (4) and contact pads (5) are integrated on the first side (3) of the sensor chip (2) and located in a chamber (17) between the substrate (1) and the sensor chip (2). Chamber (17) is bordered along at least two sides by a dam (16). Underfill (18) and/or solder flux is arranged between the sensor chip (2) and the substrate (1), and the dam (16) prevents the underfill from entering the chamber (17). An opening (19) extends from the chamber to the environment and is located between the substrate (1) and the sensor chip (2) or extends through the sensor chip (2).

Abstract: A high quality interface is formed at a low oxygen-carbon density between a substrate and a thin film while preventing heat damage on the substrate and increase of thermal budget. This method includes a step of loading a wafer into a reaction furnace, a step of pretreating the wafer in the reaction furnace, a step of performing a main processing of the pretreated wafer in the reaction furnace, and a step of unloading the wafer from the reaction furnace after the main processing. Hydrogen gas is continuously supplied to the reaction furnace in the period from the end of the pretreating step to the start of the main processing and at least during vacuum-exhausting an interior of the reaction furnace.

Abstract: A MEMS device structure including a lateral electrical via encased in a cap layer and a method for manufacturing the same. The MEMS device structure includes a cap layer positioned on a MEMS device layer. The cap layer covers a MEMS device and one or more MEMS device layer electrodes in the MEMS device layer. The cap layer includes at least one cap layer electrode accessible from the surface of the cap layer. An electrical via is encased in the cap layer extending across a lateral distance from the cap layer electrode to the one or more MEMS device layer electrodes. An isolating layer is positioned around the electrical via to electrically isolate the electrical via from the cap layer.

Abstract: MEMS devices (40) using etched cavities (42) are desirably formed using multiple etching steps. Preliminary cavities (20) formed by locally anisotropic etching to nearly the final depth have irregular (46) sidewalls (44) and steep and/or inconsistent sidewall (44) to bottom (54) intersection angles (48). This leads to less than desired cavity diaphragm (26) burst strengths. Final cavities (42) with smooth sidewalls (50), smaller and consistent sidewall (50) to bottom (54) intersection angles (58), and having more than doubled cavity diaphragm (26) burst strengths are obtained by treating the preliminary cavities (20) with TMAH etchant, preferably relatively dilute TMAH etchant. In a preferred embodiment, a cleaning step is performed between the etching step and the TMAH treatment step to remove any anisotropic etching by-products present on the preliminary cavities' (20) initial sidewalls (44).

Abstract: The present invention discloses a MEMS microphone device and its manufacturing method. The MEMS microphone device includes: a substrate including a first cavity; a MEMS device region above the substrate, wherein the MEMS device region includes a metal layer, a via layer, an insulating material region and a second cavity; a mask layer above the MEMS device region; a first lid having at least one opening communicating with the second cavity, the first lid being fixed above the mask layer; and a second lid fixed under the substrate.

Abstract: A process for fabricating a semiconductor device. The process includes (a) growing an n-channel layer of gallium arsenide (GaAs) on a buffer layer, (b) growing a barrier layer on the re-channel layer, (c) epitaxially growing a first etch-stop layer on the barrier layer, (d) growing a first contact layer of wide band-gap material on the first etch-stop layer, (e) epitaxially growing a second etch-stop layer on the first contact layer, (f) growing a second contact layer on the second etch-stop layer, where the second contact layer is a highly doped material, and (g) selectively etching portions of the first contact layer, the second etch-stop layer, and the second contact layer to form a gate region.

Abstract: A process for fabricating a semiconductor device. The process including (a) growing a channel layer on a buffer layer, (b) growing a barrier layer on the channel layer, (c) epitaxially growing a quaternary etch-stop layer on the barrier layer, (d) growing a first contact layer on the quaternary etch-stop layer, (e) growing a second contact layer on the first contact layer, (f) etching portions of the second contact layer to reveal a first recess surface, and (g) etching portions of the first contact layer to reveal a second recess surface. The second contact layer may be a highly doped contact layer. The second recess surface generally forms a gate region. The first and the second contact layers have a first etch rate and the quaternary etch-stop layer has a second etch rate in a chosen first etch chemistry.

Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.

Abstract: A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second conductor is in electrical communication with the second end so as to form an interface therebetween. A force applying structure is configured to maintain an amount of strain in the piezoelectric member sufficient to generate a desired electrical characteristic in the semiconducting device.

Abstract: A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation.

Abstract: The present invention relates to a metal-oxide/carbon-nanotube composite membrane to be used as a P-type conductive membrane for an organic solar cell, to a method for preparing same, and to an organic solar cell having improved photovoltaic conversion efficiency using the same. More particularly, the present invention relates to a metal-oxide/carbon-nanotube composite membrane to be used as a P-type conductive membrane for an organic solar cell, wherein said composite membrane is prepared by dispersing single-walled carbon nanotubes in an organic solvent, adding metal oxides to the mixed solution, dispersing the mixed solution to obtain a composite solution, and depositing the thus-obtained composite solution onto a substrate.

Abstract: A method for manufacturing an ink jet recording head is employed which has a metal mask formation process for forming a metal mask having a predetermined shape containing a silicide film formed by silicidation of the surface of a flow path forming substrate wafer containing a silicon substrate and a liquid flow path formation process for forming a liquid flow path by anisotropically etching the flow path forming substrate wafer using the metal mask as a mask.

Abstract: Provided are a display device for realizing a multi-view image and a method of fabricating the same. The display device includes: a display panel for displaying an image and a barrier pattern disposed on an outer side of the display panel and for adjusting an optical path in at least two viewing angle directions.

Abstract: A method for manufacturing a micromechanical sound transducer includes depositing successive layers of first and second membrane support material on a first main surface of a substrate arrangement with a first etching rate and a lower second etching rate, respectively. A layer of membrane material is then deposited. A cavity is created in the substrate arrangement from a side of the substrate arrangement opposite to the membrane support materials and the membrane material at least until the cavity extends to the layer of first membrane support material. The layers of first and second membrane support material are etched by applying an etching agent through the cavity in at least one first region located in an extension of the cavity also in a second region surrounding the first region. The etching creates a tapered surface on the layer of second membrane support material in the second region.

Abstract: Various exemplary embodiments relate to an integrated optical device including: a semiconductor waveguide on a substrate; a dielectric waveguide on a substrate optically coupled to the semiconductor waveguide; and a germanium device on the semiconductor waveguide optically coupled to the semiconductor waveguide.

Abstract: The invention relates to thermally contacting a semiconductor component arrangement, wherein at least one of two heat conducting bodies disposed on opposite sides of the semiconductor component arrangement is brought into contact with a contact surface of the semiconductor component arrangement by means of a metal layer under the application of a force, wherein the metal layer melts during solidification of a locking agent, forming an adhesive bond between the two heat transfer bodies over the entire region thereof.

Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer and a laser resonator. The first semiconductor layer includes a first portion and a second portion juxtaposed with the first portion. The laser resonator is provided on the first portion and has a ring-shaped resonator structure circled along a major surface of the first semiconductor layer. The second portion guides light emitted from the laser resonator.

Abstract: A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.

Abstract: The present invention relates to integrating an inertial mechanical device on top of a CMOS substrate monolithically using IC-foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A thick silicon layer is added on top of the CMOS. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level. Comparing to the incumbent bulk or surface micromachined MEMS inertial sensors, the vertically monolithically integrated inertial sensors have smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.

Abstract: A semiconductor chip has an integrated inductor, manufactured during back end of line processing. In particular, a loop (30) is formed in a metallization layer and a central region (32) of magnetic material is provided within the loop. The size of the central region is controlled so that it includes no more than five magnetic domains to achieve the desired properties.

Abstract: A device including at least two spintronic devices and a method of making the same. A magnetic connector extends between the two spintronic devices to conduct a magnetization between the two. The magnetic connector may further be disposed to conduct current to switch a magnetization of one of the two spintronic devices.

Abstract: The disclosed technology is directed to a pixel unit and a method for manufacturing the same and a liquid crystal display device. The pixel unit comprises: an array substrate; a color filter substrate; and a liquid crystal layer located between the array substrate and the color filter substrate. The pixel unit includes a displaying region and a non-displaying region in which a first electrode and a second electrode are formed on the array substrate and the color filter substrate respectively, and the rotation of molecules in the liquid crystal layer between the first electrode and the second electrode can be controlled by a vertical electrical field generated between the first electrode and the second electrode after energized to realize a normal black display mode, so that light leaking from the liquid crystal layer between the first electrode and the second electrode is prevented.

Abstract: The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased.

Abstract: There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C.

Abstract: The present invention discloses a MEMS sensing device which comprises a substrate, a MEMS device region, a film, an adhesive layer, a cover, at least one opening, and a plurality of leads. The substrate has a first surface and a second surface opposite the first surface. The MEMS device region is on the first surface, and includes a chamber. The film is overlaid on the MEMS device region to seal the chamber as a sealed space. The cover is mounted on the MEMS device region and adhered by the adhesive layer. The opening is on the cover or the adhesive layer, allowing the pressure of the air outside the device to pressure the film. The leads are electrically connected to the MEMS device region, and extend to the second surface.

Abstract: A method is provided for forming a fine pattern. In the method, a first fine pattern and a first metal pattern are formed by respectively patterning a first fine pattern layer on a base substrate and a first metal layer on the first fine pattern layer. A second fine pattern layer and a second metal layer are sequentially formed over the first fine pattern and the first metal pattern. The second metal layer is patterned, so that a second metal pattern between adjacent portions of the first fine pattern. The second fine pattern layer is patterned using the second metal pattern as a mask, so that a second fine pattern is formed between adjacent portions of the first fine pattern.

Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.

Abstract: The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region.

Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring.

Abstract: A semiconductor device may include a piezoresistive body of which a resistance value is changed by action of an external force. The piezoresistive body may include a surface layer of diamond. The surface layer may be hydrogen-terminated.

Abstract: A method for fabricating a semiconductor device, the method comprising forming a magnetic tunnel junction pattern on a substrate, forming a spacer having a metal oxide layer on a sidewall of the magnetic tunnel junction pattern, forming a first interlayer insulating layer on the substrate having the spacer and the magnetic tunnel junction pattern formed thereon, forming a first damascene pattern by etching the first interlayer insulating layer so that a top portion of the magnetic tunnel junction pattern is exposed, and forming a first wire buried in the first damascene pattern.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The device includes a magnetoresistance effect element using magnetic material containing at least one of cobalt, iron, and nickel. Forming the element includes forming a stacked body above a semiconductor substrate. The stacked body includes layers. The layers includes the magnetic material. Forming the element further includes processing the stacked body in a vacuum atmosphere by plasma etching using a first gas containing chlorine. Forming the element further includes subjecting the stacked body to a gas treatment using a second gas containing an amino group while holding the stacked body in the vacuum atmosphere.

Abstract: The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction.

Abstract: Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described. For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. The trench has a bottom and sidewalls. A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls. A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate. A top metal plate layer is disposed on and conformal with the second dielectric layer.

Abstract: The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave.

Abstract: Disclosed herein is a microelectromechanical device and a process for manufacturing same. One or more embodiments may include forming a semiconductor structural layer separated from a substrate by a dielectric layer, and opening a plurality of trenches through the structural layer exposing a portion of the dielectric layer. A sacrificial portion of the dielectric layer is selectively removed through the plurality of trenches in membrane regions so as to free a corresponding portion of the structural layer to form a membrane. To close the trenches, the wafer is brought to an annealing temperature for a time interval in such a way as to cause migration of the atoms of the membrane so as to reach a minimum energy configuration.