Manufacture Or Treatment Of Semiconductor Device (epo) Patents (Class 257/E21.002)

  • Publication number: 20120187548
    Abstract: A method of modifying a fluorinated polymer surface comprising the steps of depositing a first layer on at least a portion of the fluorinated polymer surface, the first layer comprising a first polymer, the first polymer being a substantially perfluorinated aromatic polymer; and depositing a second layer on at least a portion of the first layer, the second layer comprising a second polymer, the second polymer being an aromatic polymer having a lower degree of fluorination than said first polymer, whereby the second layer provides a surface on to which a substance having a lower degree of fluorination than the first polymer, e.g. a non-fluorinated substance is depositable.
    Type: Application
    Filed: July 29, 2010
    Publication date: July 26, 2012
    Applicant: Cambridge Display Technology Limited
    Inventor: Thomas Kugler
  • Patent number: 8227279
    Abstract: A method of manufacturing a semiconductor element of good characteristics at a reduced manufacturing cost is provided. The manufacturing method of the semiconductor element includes a GaN-containing semiconductor layer forming step, an electrode layer forming step, a step of forming an Al film on the GaN-containing semiconductor layer, a step of forming a mask layer made of a material of which etching rate is smaller than that of a material of the Al film, a step of forming a ridge portion using the mask layer as a mask, a step of retreating a position of a side wall of the Al film with respect to a position of a side wall of the mask layer, a step of forming, on the side surface of the ridge portion and the top surface of the mask layer, a protective film made of a material of which etching rate is smaller than that of the material forming the Al film, and a step of removing the Al film and thereby removing the mask layer and a portion of the protective film formed on the top surface of the mask layer.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: July 24, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Katayama, Hiroyuki Kitabayashi, Satoshi Arakawa
  • Patent number: 8227359
    Abstract: A method for manufacturing a Group III nitride semiconductor layer according to the present invention includes a sputtering step of disposing a substrate and a target containing a Group III element in a chamber, introducing a gas for formation of a plasma in the chamber and forming a Group III nitride semiconductor layer added with Si as a dopant on the substrate by a reactive sputtering method, wherein a Si hydride is added in the gas for formation of a plasma.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 24, 2012
    Assignee: Showa Denko K.K.
    Inventors: Yasunori Yokoyama, Hisayuki Miki
  • Patent number: 8227323
    Abstract: A method for manufacturing a semiconductor device is disclosed in which, after semiconductor function regions and patterns of interlayer insulating films including required contact holes are formed on one main surface side of a semiconductor substrate, an aluminum film or an aluminum alloy film which is thick is formed all over the main surface side of the semiconductor substrate and brought into conductive contact with the surface of the semiconductor substrate including bottom surfaces of the contact holes so as to form a required electrode film. Formation of the aluminum film or the aluminum alloy film is divided into a plurality of steps so that the thickness of the aluminum film or the aluminum alloy film is formed gradually, and between every two of the plurality of steps of forming the aluminum film or the aluminum alloy film, there is provided a step of performing isotropic etching to flatten irregularities in a surface of the aluminum film or the aluminum alloy film formed in the previous step.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: July 24, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kouta Takahashi, Takeshi Fujii
  • Patent number: 8227290
    Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate through an ion implanting surface thereof; closely contacting the single crystal silicon substrate and a transparent insulator substrate with each other via a transparent adhesive while using the ion implanting surface as a bonding surface; curing the transparent adhesive; applying an impact to the ion implanted layer to mechanically delaminate the single crystal silicon substrate; forming a plurality of diffusion regions having a second conductivity type at the delaminated surface side of the single crystal silicon layer, such that a plurality of first conductivity-type regions and second conductivity-type regions are present at the delaminated surface of the single crystal silicon layer; forming pluralities of individual electrodes on the pluralities of first and second conductivity-type regions, respectively; and forming collector electrodes for the individual electrode
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 24, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Shoji Akiyama, Masahiro Furuya, Makoto Kawai, Koichi Tanaka, Yoshihiro Kubota, Yuuji Tobisaka
  • Patent number: 8227289
    Abstract: A method for producing a single crystal silicon solar cell including the steps of: implanting ions into a single crystal silicon substrate; conducting a surface activating treatment for at least one of: the ion implanting surface of the single crystal silicon substrate, and a surface of the transparent insulator substrate; bonding the ion implanting surface of the single crystal silicon substrate and the transparent insulator substrate to each other, such that the surface(s) subjected to the surface activating treatment is/are used as a bonding surface(s); applying an impact to the ion implanted layer; and forming a plurality of diffusion regions having a second conductivity type at the delaminated surface side of the single crystal silicon layer, such that a plurality of first conductivity-type regions and second conductivity-type regions are present at the delaminated surface of the single crystal silicon layer.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 24, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Atsuo Ito, Shoji Akiyama, Makoto Kawai, Koichi Tanaka, Yuuji Tobisaka, Yoshihiro Kubota
  • Patent number: 8227282
    Abstract: A method of manufacturing a vertical light emitting diode includes: providing a first substrate; forming a lapping stop layer on the first substrate, the lapping stop layer being harder than the first substrate; depositing an epitaxial layer on the lapping stop layer; bonding a second substrate on the epitaxial layer; and removing the first substrate from the lapping stop layer.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: July 24, 2012
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Tzu-Chien Hung, Chia-Hui Shen
  • Publication number: 20120184053
    Abstract: A method for manufacturing a magnetic sensor that decreases area resistance and decreases MR ratio of the sensor by eliminating any oxide formation in the capping layer of the sensor. The method includes forming a sensor stack having a multi-layer capping structure formed there-over. The multi-layer capping structure can include first, second, third and fourth layers. The second layer is constructed of a material that is not easily oxidized and which is different from the first layer. The sensor can be formed using a mask that includes a carbon hard mask. After the sensor stack has been formed by ion milling, the hard mask can be removed by reactive ion etching. Then, a cleaning process is performed to remove the second, third and fourth layers of the capping layer structure using an end point detection method such as secondary ion mass spectrometry to detect the presence of the second layer.
    Type: Application
    Filed: January 19, 2011
    Publication date: July 19, 2012
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Koji Sakamoto, Atsushi Katou, Takao Yonekawa, Norihiro Ookawa, Kouichi Nishioka, Kouji Okazaki
  • Publication number: 20120180842
    Abstract: A thermoelectric device, a method for fabricating a thermoelectric device and electrode materials applied to the thermoelectric device are provided according to the present invention. The present invention is characterized in arranging thermoelectric material power, interlayer materials and electrode materials in advance according to the structure of thermoelectric device; adopting one-step sintering method to make a process of forming bulked thermoelectric materials and a process of combining with electrodes on the devices to be completed simultaneously; and obtaining a ? shape thermoelectric device finally. Electrode materials related to the present invention comprise binary or ternary alloys or composite materials, which comprise at least a first metal selected from Cu, Ag, Al or Au, and a second metal selected from Mo, W, Zr, Ta, Cr, Nb, V or Ti.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 19, 2012
    Inventors: Lidong Chen, Monika Backhaus-Ricoult, Lin He, Xiaoya Li, Yunshan Tang, Xugui Xia, Degang Zhao
  • Publication number: 20120183009
    Abstract: The horizontal cavity surface emitting laser includes a cavity structure portion including a stacked structure of a first conduction type clad layer, an active layer and a second conduction type clad layer stacked over a semiconductor substrate and causing light generated by the active layer to be reflected or resonated, an optical waveguide layer provided at part of the semiconductor substrate and guiding the light, a reflector provided in the optical waveguide layer, for reflecting the light and emitting the light from the back surface of the semiconductor substrate, and a condensing lens provided at the back surface thereof and focusing the reflected light. The back surface thereof has a groove provided with the condensing lens and a terrace-like portion disposed below the cavity structure portion and has a terrace shape with the cleavage direction along a longitudinal direction thereof provided along a cleavage direction of the semiconductor substrate.
    Type: Application
    Filed: January 13, 2012
    Publication date: July 19, 2012
    Inventors: Koichiro ADACHI, Yasunobu MATSUOKA, Toshiki SUGAWARA, Kazunori SHINODA, Shinji TSUJI
  • Publication number: 20120181640
    Abstract: In one embodiment, a semiconductor device includes a glass substrate, a semiconductor substrate disposed on the glass substrate, and a magnetic sensor disposed within and/or over the semiconductor substrate.
    Type: Application
    Filed: January 17, 2011
    Publication date: July 19, 2012
    Inventors: Carsten von Koblinski, Volker Strutz, Manfred Engelhardt
  • Publication number: 20120181637
    Abstract: A method for forming a semiconductor device includes forming a substrate, forming a moveable member of bulk silicon and forming a first dimple structure on a first surface of the moveable member, where the first surface faces the substrate.
    Type: Application
    Filed: January 13, 2011
    Publication date: July 19, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Pao Shu, Chia-Hua Chu
  • Publication number: 20120181639
    Abstract: A cost-effective and space-saving component that includes a MEMS element and an access channel to the membrane structure of the MEMS element. The MEMS element is mounted by the rear side of the component on a substrate and is at least partially embedded in a molding compound. An access port is formed in the molding compound. The component also includes at least one semiconductor component having at least one through hole that is integrated in the molding compound above the MEMS element at a distance from the membrane structure, so that a hollow space is located between the semiconductor component and the membrane structure. The access port in the molding compound opens into the through hole of the semiconductor component and, together with this and the hollow space between the further semiconductor component and the membrane structure, forms the access channel to the membrane structure.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 19, 2012
    Inventors: Ricardo Ehrenpfordt, Ulrike Scholz
  • Patent number: 8222117
    Abstract: An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a single crystal silicon substrate to form a single crystal silicon substrate which is n (n is an optional positive integer, n?1) times as large as a size of one shot of an exposure apparatus; a step (B) of forming an insulating layer on one surface of the single crystal silicon substrate, and forming an embrittlement layer in the single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface are conducted.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: July 17, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma
  • Publication number: 20120178199
    Abstract: An array of sensor devices, each sensor including a set of semiconducting nanotraces having a width less than about 100 nm is provided. Method for fabricating the arrays is disclosed, providing a top-down approach for large arrays with multiple copies of the detection device in a single processing step. Nanodimensional sensing elements with precise dimensions and spacing to avoid the influence of electrodes are provided. The arrays may be used for multiplex detection of chemical and biomolecular species. The regular arrays may be combined with parallel synthesis of anchor probe libraries to provide a multiplex diagnostic device. Applications for gas phase sensing, chemical sensing and solution phase biomolecular sensing are disclosed.
    Type: Application
    Filed: January 11, 2011
    Publication date: July 12, 2012
    Applicant: NANOHMICS, INC.
    Inventors: Steve M. Savoy, Jeremy J. John, Daniel R. Mitchell, Michael K. McAleer
  • Publication number: 20120175790
    Abstract: A composition for a patternable adhesive film, a patternable adhesive film having the same, and a method of manufacturing a semiconductor package using the patternable adhesive film are provided. The composition contains a binder resin, a radical-polymerizable acrylate monomer, a photo-radical initiator, and a thermal-radical initiator without an epoxy resin. The composition may have good patternability, adhesiveness, and low-temperature stability, and be rapidly cured at a low temperature.
    Type: Application
    Filed: August 5, 2011
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Seok HAN, Joon Yong PARK, Jae Jun LEE, Chul Ho JEONG
  • Publication number: 20120175789
    Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 12, 2012
    Applicant: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Patrarca, Richard P. Volant, Kevin R. Winstel
  • Publication number: 20120175715
    Abstract: Encapsulated MEMS switches are disclosed along with methods of manufacturing the same. A non-polymer based sacrificial layer is used to form the actuation member of the MEMS switch while a polymer based sacrificial layer is used to form the enclosure that encapsulates the MEMS switch. The first non-polymer based sacrificial layer allows for highly reliable MEMS switches to be manufactured while also protecting the MEMS switch from carbon contamination. The polymer based sacrificial layer allows for the manufacture of more spatially efficient encapsulated MEMS switches.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 12, 2012
    Applicant: RF Micro Devices, Inc.
    Inventors: Jonathan Hale Hammond, Julio Costa
  • Publication number: 20120175714
    Abstract: Embodiments of embedded MEMS sensors and related methods are described herein. Other embodiments and related methods are also disclosed herein.
    Type: Application
    Filed: July 27, 2011
    Publication date: July 12, 2012
    Applicants: Arizona State University
    Inventors: Narendra V. Lakamraju, Sameer M. Venugopal, Stephen M. Phillips, David R. Allee
  • Publication number: 20120176708
    Abstract: The present disclosure provides a device that includes a signal input that is in electrical communication with an electrostatic discharge (ESD) protection device, wherein the ESD protection device includes a gated diode arranged as a polygon.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ming Hsien Tsai
  • Patent number: 8216860
    Abstract: A semiconductor device and a method of fabricating a semiconductor device that includes forming an interlayer insulating film on a semiconductor substrate; depositing a first soft magnetic thin film on the interlayer insulating film through sputtering using a target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; forming a metal film on the first soft magnetic thin film; depositing a second soft magnetic thin film on the metal film through sputtering using the same or another target containing at least one of Fe, Co, Ni, or alloys thereof, the target further containing at least one of Ti, Hf, or B, the sputtering being performed using an N2 reactive gas; and patterning to form an inductor.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: July 10, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo-hyun Jeong, Chul-ho Chung
  • Publication number: 20120168886
    Abstract: The invention concerns a method for the fabrication, on a plane substrate, of a microswitch actuatable by a magnetic field, comprising: a) the etching, in the upper face of the plane substrate, of cavities forming a hollow model of two strips, these cavities having vertical flanks extending perpendicularly to the plane of the substrate to form vertical faces of the strips, b) the filling of the cavities by a magnetic material to form the strips, then c) the etching in the substrate, by a method of isotropic etching, of a well that extends between the vertical faces of the strips and beneath and around one distal end of at least one of the strips to open out an air gap between these strips and make this distal end capable of being shifted between a closed position and an open position.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 5, 2012
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Henri Sibuet, Yannick Vuillermet
  • Publication number: 20120168885
    Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. At least one of the pinned layer and the free layer includes a magnetic substructure. The magnetic substructure includes at least two magnetic layers interleaved with at least one insertion layer. Each insertion layer includes at least one of Cr, Ta, Ti, W, Ru, V, Cu, Mg, aluminum oxide, and MgO. The magnetic layers are exchange coupled.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 5, 2012
    Applicant: GRANDIS, INC.
    Inventors: Dmytro Apalkov, Xueti Tang, Vladimir Nikitin
  • Publication number: 20120171784
    Abstract: A magnetron-sputtering film-forming apparatus includes: a vacuum film-forming chamber (11); electrostatic chuck units (12) for adjusting a temperature of the substrate (14); a target (15) for causing high-frequency magnetron sputtering; power supply units (17) for applying a discharge voltage between the substrate (14) and the target (15), and calculating an integral power consumption of an electricity discharged by the target (15); and control units (18) for controlling the electrostatic chuck units (12) and the power supply units (17). In the magnetron-sputtering film-forming apparatus, the temperature of the substrate to be processed (14) that is most suitable for sputtering is calculated based on the integral power consumption of the electricity discharged by the target (15) until that time, and the substrate (14) is adjusted to have a predetermined temperature to be subjected to the sputtering.
    Type: Application
    Filed: March 12, 2012
    Publication date: July 5, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Wensheng Wang
  • Publication number: 20120168882
    Abstract: A integrated circuit die includes a chemical sensor, a thermal sensor, and a humidity sensor formed therein. The chemical sensor, thermal sensor, and humidity sensor include electrodes formed in a passivation layer of the integrated circuit die. The integrated circuit die further includes transistors formed in a monocrystalline semiconductor layer.
    Type: Application
    Filed: October 31, 2011
    Publication date: July 5, 2012
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Suman Cherian, Olivier Le Neel
  • Publication number: 20120168883
    Abstract: A RF MEMS switch includes a substrate, a first electrode, a first insulating layer, a second insulating layer, a second electrode and a movable electrode. The first electrode is disposed on the substrate. The first insulating layer covers the first electrode. The second insulating layer covers a portion of the substrate. The second electrode is disposed in the second insulating layer and is located at a plane different from a plane of the first electrode. The movable electrode is partially disposed on a surface of the second insulating layer, and extends over the first electrode and the second electrode. A portion of the movable electrode not disposed on the surface of the second insulating layer is a movable portion. The second insulating layer has a gap exposing a space between the movable portion and the first insulating layer and a space between the movable portion and the second electrode.
    Type: Application
    Filed: March 16, 2011
    Publication date: July 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jun-Kai Mao, Chiung-I Lee
  • Publication number: 20120172479
    Abstract: Embodiments in accordance with the present invention are directed to polymer compositions that are useful for forming temporary bonding layers that serve to releasably join a first substrate to a second substrate as well as methods of both forming such a temporary bond and methods of debonding such substrates. Some such polymer compositions encompass a casting solvent, a photoacid generator and optionally a sensitizer and/or an adhesion promoter.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 5, 2012
    Applicant: PROMERUS LLC
    Inventors: Larry F. Rhodes, Leah J. Langsdorf, Venkat Ram Dukkipati
  • Publication number: 20120171798
    Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.
    Type: Application
    Filed: April 19, 2007
    Publication date: July 5, 2012
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Hideki Takeuchi, Emmanuel P. Quevy, Tsu-Jae King, Roger T. Howe
  • Patent number: 8212326
    Abstract: A manufacturing method for a micromechanical component having a thin-layer capping.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: July 3, 2012
    Assignee: Robert Bosch GmbH
    Inventor: Ando Feyh
  • Publication number: 20120164775
    Abstract: Electronic device which comprises a substrate provided with at least one passing opening, a MEMS device with function of differential sensor provided with a first and a second surface and of the type comprising at least one portion sensitive to chemical and/or physical variations of fluids present in correspondence with a first and a second opposed active surface thereof, the first surface of the MEMS device leaving the first active surface exposed and the second surface being provided with a further opening which exposes said second opposed active surface, the electronic device being characterized in that the first surface of the MEMS device faces the substrate and is spaced therefrom by a predetermined distance, the sensitive portion being aligned to the passing opening of the substrate, and in that it also comprises a protective package, which incorporates at least partially the MEMS device and the substrate so as to leave the first and second opposed active surfaces exposed respectively through the passin
    Type: Application
    Filed: January 25, 2012
    Publication date: June 28, 2012
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Lorenzo BALDO, Chantal COMBI, Mario Francesco CORTESE
  • Publication number: 20120160027
    Abstract: The disclosure relates to a micro-electromechanical system (MEMS) device having an electrical insulating structure. The MEMS device includes at least one moving part, at least one anchor, at least one spring and an insulating layer. The spring is connected to the anchor and to the moving part. The insulating layer is disposed in the moving part and the anchor. Each of the moving part and the anchor is divided into two conductive portions by the insulating layer. Whereby, the electrical signals of different moving parts are transmitted through the insulated electrical paths which are not electrically connected.
    Type: Application
    Filed: August 29, 2011
    Publication date: June 28, 2012
    Applicant: INDUSTRIALTECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu Wen HSU, Shih Ting Lin, Jen Yi Chen, Chao Ta Huang
  • Publication number: 20120161255
    Abstract: Embodiments of the invention provide methods of sealing a micro electromechanical systems (MEMS) cavity and devices resulting therefrom. A first aspect of the invention provides a method of sealing a micro electromechanical systems (MEMS) cavity in a substrate, the method comprising: forming in a substrate a cavity filled with a sacrificial material; forming a lid over the cavity; forming at least one vent hole over the lid extending to the cavity; removing the sacrificial material from the cavity; depositing a first material onto the lid such that a size of at least one vent hole at a surface of the substrate is reduced but not sealed; and depositing a second material onto the first material to seal the at least one vent hole, wherein a MEMS cavity within the substrate and beneath the at least one vent hole substantially retains a pressure at which the at least one vent hole is sealed by the second material.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas H. Gabert, Joseph P. Hasselbach, Anthony K. Stamper
  • Publication number: 20120164757
    Abstract: The present invention provides a method for manufacturing a TMR sensor that reduces damage to a sensor stack during intermediate stages of the manufacturing process. In an embodiment of the invention, after formation of a sensor stack, a protective layer is deposited on the sensor stack that provides protection from materials that may be used in subsequent steps of the manufacturing process. The protective layer is subsequently converted to an insulating layer and the thickness of the insulating layer is extended to an appropriate thickness. In converting the protective layer to an insulating layer, the sensor stack is not directly exposed to materials that may damage it. For example, in an embodiment of the invention, Mg is used as the protective layer that is subsequently converted to MgO with the introduction of oxygen. Although direct contact of oxygen with the sensor stack may cause damage to the sensor stack, direct contact is avoided by the present invention.
    Type: Application
    Filed: December 27, 2010
    Publication date: June 28, 2012
    Applicant: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Zheng Gao, Liubo Hong, Richard Hsiao, Kochan Ju, Stefan Maat
  • Publication number: 20120161319
    Abstract: A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: STMICROELECTRONICS PTE LTD.
    Inventors: Yaohuang Huang, Yonggang Jin, Puay Gek Chua, How Yuan Hwang
  • Publication number: 20120161254
    Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: Infineon Technologies AG
    Inventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
  • Publication number: 20120161264
    Abstract: Embodiments generally relate to a magnetic read sensor and a method for its manufacture. A multi-layer insulating material may be used to cover both the first shield layer and also the sidewalls of the sensor structure in the magnetic read sensor. The first insulating layer of the multi-layer insulating material may be deposited by an ion beam sputtering process in a chamber that does not have any oxygen gas flowing into it so that oxygen diffusion into the sensor structure is reduced or eliminated. Then, a second insulating layer of the multi-layer insulating material may be deposited by atomic layer deposition such that the second insulating layer has a greater quality than the first insulating layer. The higher quality increases the breakdown voltage for the magnetic read sensor. Thus, the magnetic read sensor of the present invention has an effective insulating portion that increases the breakdown voltage without sensor damage.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: LIUBO HONG, Guangli Liu
  • Publication number: 20120163749
    Abstract: An integrated circuit is configured for optical communication via an optical polymer stack located on top of the integrated circuit. The optical polymer stack may include one or more electro-optic polymer devices including an electro-optic polymer. The electro-optic polymer may include a host polymer and a second order nonlinear chromomophore, the host polymer and the chromophore both including aryl groups configured to interact with one another to provide enhanced thermal and/or temporal stability.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 28, 2012
    Applicant: GIGOPTIX, INC.
    Inventors: Diyun HUANG, Bing LI, Eric MILLER, Danliang JIN, Christopher A. WIKLOF, Guomin YU
  • Publication number: 20120164774
    Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a first semiconductive material and at least one trench disposed in the first semiconductive material, the at least one trench having a sidewall. An insulating material layer is disposed over an upper portion of the sidewall of the at least one trench in the first semiconductive material and over a portion of a top surface of the first semiconductive material proximate the sidewall. A second semiconductive material or a conductive material is disposed within the at least one trench and at least over the insulating material layer disposed over the portion of the top surface of the first semiconductive material proximate the sidewall.
    Type: Application
    Filed: February 27, 2012
    Publication date: June 28, 2012
    Applicant: Infineon Technologies, AG
    Inventors: Florian Schoen, Wolfgang Raberg, Bernhard Winkler, Werner Weber
  • Publication number: 20120161266
    Abstract: Radiation detectors can be made of n-type or p-type silicon. All segmented detectors on p-type silicon and double-sided detectors on n-type silicon require an “inter-segment isolation” to separate the n-type strips from each other; an alumina layer for isolating the strip detectors is applied, and forms negative charges at the silicon interface with appropriate densities. When alumina dielectric is deposited on silicon, the negative interface charge acts like an effective p-stop or p-spray barrier because electrons are “pushed” away from the interface due to the negative interface charge.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 28, 2012
    Applicants: Counsel
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Patent number: 8206995
    Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 26, 2012
    Assignee: IMEC
    Inventors: Judit Gloria Lisoni Reyes, Ludovic Goux, Dirk Wouters
  • Patent number: 8207453
    Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 26, 2012
    Assignee: Intel Corporation
    Inventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
  • Publication number: 20120153413
    Abstract: An apparatus and associated method for a non-volatile memory cell, such as an STRAM cell. In accordance with various embodiments, a magnetic free layer is laterally separated from an antiferromagnetic layer (AFM) by a non-magnetic spacer layer and medially separated from a synthetic antiferromagnetic layer (SAF) by a magnetic tunneling junction. The AFM pins the magnetization of the SAF through contact with a pinning region of the SAF that laterally extends beyond the magnetic tunneling junction.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Antoine Khoueir, Brian Lee, Patrick J. Ryan
  • Publication number: 20120155161
    Abstract: A three-terminal Ovonic Threshold Switch (OTS) is used to provide current to a Phase Change Memory Switch (PCMS) cross point array. The current is started by sending a small current into the second terminal of the three-terminal OTS allowing a larger current to flow from the first terminal to the third terminal of the three-terminal OTS. A method of making the three-terminal OTS is also presented.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: Jong-Won Lee, Gianpaolo Spadini
  • Publication number: 20120152296
    Abstract: Provided are a thermoelectric device, a thermoelectric device module, and a method of forming the thermoelectric device. The thermoelectric device includes a first conductive type first semiconductor nanowire including at least one first barrier region; a second conductive type second semiconductor nanowire including at least one second barrier region; a first electrode connected to one end of the first semiconductor nanowire; a second electrode connected to one end of the second semiconductor nanowire; and a common electrode connected to the other end of the first semiconductor nanowire and the other end of the second semiconductor nanowire. The first barrier region is greater than the first semiconductor nanowire in thermal conductivity, and the second barrier region is greater than the second semiconductor nanowire in thermal conductivity.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 21, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Moon-Gyu Jang, Myung-Sim Jun, Tae-Moon Roh, Jong-Dae Kim, Tae-Hyoung Zyung
  • Publication number: 20120152029
    Abstract: In a method of manufacturing a semiconductor pressure sensor, a multilayer structure including a polysilicon diaphragm, a polysilicon gauge resistor formed on a side of a space which is to serve as a vacuum chamber below the polysilicon diaphragm, and a group of insulating films containing the polysilicon diaphragm and the polysilicon gauge resistor and having an etching solution introduction hole in contact with a sacrificial layer is formed on the sacrificial layer. Then, an etching solution is supplied through the etching solution introduction hole and the sacrificial layer is etched with the etching solution, to thereby obtain a diaphragm body formed of the multilayer structure, which functions on the vacuum chamber, and a surface of a silicon substrate below a first opening of a first insulating film is etched to thereby form the space which is to serve as the vacuum chamber and a diaphragm stopper disposed in the space, protruding toward near the center of the diaphragm body.
    Type: Application
    Filed: August 9, 2011
    Publication date: June 21, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Kimitoshi SATO
  • Publication number: 20120153408
    Abstract: A method of forming a MEMS device by encapsulating a MEMS element with a sacrificial layer portion deposited over a substrate arrangement, the portion defining a cavity for the MEMS element, forming at least one strip of a further sacrificial material extending outwardly from the portion, forming a cover layer portion over the sacrificial layer portion, the cover layer portion terminating on the at least one strip, removing the sacrificial layer portion and the at least one strip, the removal of the at least one strip defining at least one vent channel extending laterally underneath the cover layer portion and sealing the at least one vent channel. A device including such a packaged micro electro-mechanical structure.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 21, 2012
    Applicant: NXP B.V.
    Inventors: Michael Antoine Armand in 't Zandt, Wim van den Einden, Harold Roosen
  • Publication number: 20120156820
    Abstract: The present Disclosure provides for fabrication devices and methods for manufacturing a micro-electromechanical system (MEMS) switch on a substrate. The MEMS fabrication device may have a first and second sacrificial layer that form the mold of an actuation member. The actuation member is formed over the first and second sacrificial layers to manufacture a MEMS switch from the MEMS fabrication device.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 21, 2012
    Applicant: RF MICRO DEVICES, INC.
    Inventor: Sangchae Kim
  • Patent number: 8202743
    Abstract: The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using the organic light emitting element. The average concentration of impurities contained in a layer made from an organic compound used in order to form an organic light emitting element having layers such as a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer, is reduced to 5×1019/cm2 or less, preferably equal to or less than 1×1019/cm2, by removing the impurities with the present invention. Formation apparatuses are structured as stated in the specification in order to reduce the impurities in the organic compounds forming the organic light emitting elements.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: June 19, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8202756
    Abstract: According to one embodiment, a method of manufacturing an organic EL device includes providing a structure including a substrate and an electrode positioned above the substrate, and forming an organic layer including a mixture of first and second organic materials above the electrode. The first organic material has a first sublimation point. The second organic material has a second sublimation point higher than the first sublimation point. The formation of the organic layer includes heating an evaporation material including a mixture of the first and second organic materials to an evaporation temperature so as to sublimate the first and second organic materials, and delivering the sublimed first and second organic materials toward the electrode to deposit a mixture including the first and second organic materials above the electrode. The evaporation temperature is, for example, a temperature higher than the second sublimation temperature by 50° C. or more.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 19, 2012
    Assignee: Toshiba Mobile Display Co., Ltd.
    Inventors: Kazuki Kitamura, Tetsuo Ishida
  • Publication number: 20120146452
    Abstract: A manufacturing method of the MEMS device disposes a conductive circuit to maintain various elements of the MEMS equi-potential thereby preventing electrostatic damages to various elements of the MEMS during the manufacturing process.
    Type: Application
    Filed: November 15, 2011
    Publication date: June 14, 2012
    Applicant: MIRADIA, INC.
    Inventors: HUA-SHU WU, SHIH-YUNG CHUNG, YU-HAO CHIEN, LI-TIEN TSENG, YU-TE YEH