Abstract: A combinatorial processing method is provided. The combinatorial processing method includes providing a flow of fluid over segregated sectors of a substrate to process the segregated sectors of the substrate in parallel without significantly exposing any section to a reagent without first applying a film and without subjecting any section to the same process step at the same time. Differently processed, segregated sectors may be generated in parallel.

Abstract: A phase change memory device having buried conduction lines directly underneath phase change memory cells is presented. The phase change memory device includes buried conduction lines buried in a semiconductor substrate and phase change memory cells arranged on top of the buried conductive lines. By having the buried conduction lines directly underneath the phase change memory cells, the resultant device can realize a considerable reduction in size.

Abstract: A nanosensor comprising a substrate in which an opening defining a hole is formed; a first layer disposed on the substrate, which comprises a first nanopore in communication with the hole in the substrate; and a second layer contacted or coupled with the first layer and formed of a porous material.

Abstract: A method includes forming a plurality of mirror periods, stacking the mirror periods, and bonding the mirror periods together to form a high reflectance mirror. At least one of the mirror periods is formed by bonding a first semiconductor layer to a first side of a film layer (where the film layer is formed on a second semiconductor layer), forming an opening through the second semiconductor layer to expose the film layer, and cutting through the first semiconductor layer, the film layer, and the second semiconductor layer. The first semiconductor layer could include a high resistivity silicon wafer, the film layer could include an oxide film, and the second semiconductor layer could include a silicon wafer. The high resistivity silicon wafer could be approximately 110 ?m thick, and the silicon wafer could be approximately 125 ?m thick. The opening through the second semiconductor layer could be 1.25 cm to 1.75 cm in width.

Abstract: A semiconductor thermoelectric cooler includes P-type and N-type thermoelectric cooling elements. The P-type and N-type thermoelectric elements have a first portion having a first cross-sectional area and a second portion having a second cross-sectional area larger than the first cross-sectional area. The P-type and N-type thermoelectric cooling elements may, for example, be T-shaped or L-shaped. In another example, the thermoelectric cooling elements have a first surface having a first shape configured to couple to a first electrical conductor and a second surface opposite the first surface and having a second shape, different from the first shape, and configured to couple to a second electrical conductor. For example, the first surface may have a rectilinear shape of a first area and the second surface may have a rectilinear shape of a second area different from the first area. The semiconductor thermoelectric cooler may be manufactured using thin film technology.

Abstract: In one embodiment, an integrated circuit (IC) is presented. The IC includes first and second sets of power distribution lines formed in the IC. The IC includes first and second capacitors formed in one or more layers of the IC. A first plurality of vias couple a first input of the first and second capacitors to the first set of power distribution lines, and a second plurality of vias couple a second input of the first and second capacitors to the second set of power distribution lines. The first capacitor and the first plurality of vias and the second plurality of vias coupled thereto having an equivalent series resistance greater than an equivalent series resistance of the second capacitor and the first plurality of vias and the second plurality of vias coupled thereto.

Abstract: Some embodiments relate to method of fabricating a sensor. The method includes providing a substrate wafer that includes a suspended beam; adding an adhesive layer to the substrate wafer such that the adhesive layer covers portions of the substrate without covering the suspended beam; positioning a cover wafer onto the adhesive layer such that the suspend beam is exposed to ambient air through openings in the cover wafer; and functionalizing the suspended beam by contacting the suspended beam with materials through the opening in the cover wafer.

Abstract: A MEMS manufacturing method and device in which a spacer layer is provided over a side wall of at least one opening in a structural layer which will define the movable MEMS element. The opening extends below the structural layer. The spacer layer forms a side wall portion over the side wall of the at least one opening and also extends below the level of the structural layer to form a contact area.

Abstract: A sensing apparatus for sensing target materials including biological or chemical molecules in a fluid. One such apparatus includes a semiconductor-on-insulator (SOI) structure having an electrically-insulating layer, a fluidic channel supported by the SOI structure and configured and arranged to receive and pass a fluid including the target materials, and a semiconductor device including at least three electrically-contiguous semiconductor regions doped to exhibit a common polarity. The semiconductor regions include a sandwiched region sandwiched between two of the other semiconductor regions, and configured and arranged adjacent to the fluidic channel with a surface directed toward the fluidic channel for coupling to the target materials in the fluidic channel, and further arranged for responding to a bias voltage. The sensing apparatus also includes an amplification circuit in or on the SOI and that is arranged to facilitate sensing of the target material near the fluidic channel.

Abstract: A laser processing method of converging laser light into an object to be processed made of silicon so as to form a modified region and etching the object along the modified region so as to form the object with a through hole comprises an etch resist film producing step of producing an etch resist film resistant to etching on an outer surface of the object; a laser light converging step of converging the laser light at the object after the etch resist film producing step so as to form the modified region along a part corresponding to the through hole in the object and converging the laser light at the etch resist film so as to form a defect region along a part corresponding to the through hole in the etch resist film; and an etching step of etching the object after the laser light converging step so as to advance the etching selectively along the modified region and form the through hole.

Abstract: A method for forming a sensor stack is presented. The method includes providing a substrate having a first side and a second side. Furthermore, the method includes disposing an integrated circuit having a first side and a second side on the first side of the substrate, where the integrated circuit comprises a first plurality of contact pads disposed on the first side of the integrated circuit. The method also includes providing a sensor array having a plurality of sensor elements, wherein each of the sensor elements has a first side and a second side, and wherein the sensor array comprises a second plurality of contact pads disposed on the second side of the sensor array.

Abstract: A capacitive sensor is configured for collapsed mode, e.g. for measuring sound or pressure, wherein the moveable element is partitioned into smaller sections. The capacitive sensor provides increased signal to noise ratio.

Abstract: A method for producing oblique surfaces in a substrate, comprising a formation of recesses on both surfaces of the substrate, until the recesses are so deep that the substrate is perforated by the two recesses. One recess is produced going out from a first main surface in the region of a first surface, and the other recess is produced going out from the second main surface in the region of a second surface, so that the first surface and the second surface do not coincide along a surface normal of the main surfaces of the substrate. Subsequently, flexible diaphragms are attached over the recesses on each of the main surfaces. If a vacuum pressure is then produced inside the recesses, the flexible diaphragms each curve in the direction of the recesses until their surfaces facing the substrate come into contact with one another, generally in the center of the recesses.

Abstract: In an example, a method of fabricating one or more vertical interconnects is provided. The method includes patterning and stacking a plurality of wafers to form a wafer stack. A plurality of apertures can be formed in the wafer stack within one or more saw streets of the wafer stack, and conductive material can be deposited on sidewalls of the plurality of apertures.

Abstract: Systems and methods for a micro-electromechanical system (MEMS) apparatus are provided. In one embodiment, a system comprises a first double chip that includes a first base layer; a first device layer bonded to the first base layer, the first device layer comprising a first set of MEMS devices; and a first top layer bonded to the first device layer, wherein the first set of MEMS devices is hermetically isolated. The system also comprises a second double chip that includes a second base layer; a second device layer bonded to the second base layer, the second device layer comprising a second set of MEMS devices; and a second top layer bonded to the second device layer, wherein the second set of MEMS devices is hermetically isolated, wherein a first top surface of the first top layer is bonded to a second top surface of the second top layer.

Abstract: Multiple-wavelength VCSEL array apparatus and method having a high contrast grating (HCG) mirror which can be implemented on a single substrate in which only the dimensions of the HCG (e.g., duty cycle or the period) need be changed to alter the wavelength of a given VCSEL in response to changing the reflectivity phase of the HCG mirror. The HCG can be defined by any desired lithographic process. By using a broadband HCG mirror a large wavelength span over 100 nm is provided, such as covering the entire C-band. The HCG multi-wavelength VCSEL array enables single-transverse mode emission and polarization control and scalability with respect to wavelength.

Abstract: In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

Abstract: Exact alignment of a recrystallized region, which is to be formed in an amorphous or polycrystalline film, is facilitated. An alignment mark is formed, which is usable in a step of forming an electronic device, such as a thin-film transistor, in the recrystallized region. In addition, in a step of obtaining a large-grain-sized crystal-phase semiconductor from a semiconductor film, a mark structure that is usable as an alignment mark in a subsequent step is formed on the semiconductor film in the same exposure step. Thus, the invention includes a light intensity modulation structure that modulates light and forms a light intensity distribution for crystallization, and a mark forming structure that modulates light and forms a light intensity distribution including a pattern with a predetermined shape, and also forms a mark indicative of a predetermined position on a crystallized region.

Abstract: An organic light emitting device (OLED) and a method of fabricating the same are provided, wherein the OLED includes a thin film transistor having a gate electrode, and source and drain electrodes on a substrate; a triple-layered pixel electrode connected to one of the source and drain electrodes through a via-contact hole formed in an insulating layer on the substrate, and having a lower pixel electrode, a reflective layer pattern and an upper pixel electrode; an organic layer disposed on the upper pixel electrode and having at least an emission layer; and an opposite electrode disposed on the organic layer.

Abstract: An apparatus and associated method for a non-volatile memory cell with a phonon-blocking insulating layer. In accordance with various embodiments, a magnetic stack has a tunnel junction, ferromagnetic free layer, pinned layer, and an insulating layer that is constructed of an electrically and thermally insulative material that blocks phonons while allowing electrical transmission through at least one conductive feature.

Abstract: The invention relates to a device for pulsed laser deposition, which device comprises: a substrate mount with a substrate mounted thereon; a target mount with a target material mounted thereon and opposite of the substrate mount; a laser device for directing a laser beam on the target material; and a shadow mask arranged over the substrate; wherein the shadow mask is arranged in a movable disc, which movable disc is movable in axial direction to and from the substrate mount. The invention also relates to a method for operating such a device.

Abstract: Methods and apparatus are provided for controlling a depth of a cavity between two layers of a light modulating device. A method of making a light modulating device includes providing a substrate, forming a sacrificial layer over at least a portion of the substrate, forming a reflective layer over at least a portion of the sacrificial layer, and forming one or more flexure controllers over the substrate, the flexure controllers configured so as to operably support the reflective layer and to form cavities, upon removal of the sacrificial layer, of a depth measurably different than the thickness of the sacrificial layer, wherein the depth is measured perpendicular to the substrate.

Abstract: Methods of fabricating semiconductor sensor devices include steps of fabricating a hermetically sealed MEMS cavity enclosing a MEMS sensor, while forming conductive vias through the device. The devices include a first semi-conductor layer defining at least one conductive via lined with an insulator and having a lower insulating surface; a central dielectric layer above the first semiconductor layer; a second semiconductor layer in contact with the at least one conductive via, and which defines a MEMS cavity; a third semiconductor layer disposed above the second semiconductor layer, and which includes a sensor element aligned with the MEMS cavity; a cap bonded to the third semiconductor to enclose and hermetically seal the MEMS cavity; wherein the third semiconductor layer separates the cap and the second semiconductor layer.

Abstract: A method of fabricating a device is disclosed. The method comprises coating a solid structure by nanostructures selected from the group consisting of peptides and amino acids, under conditions that at least partially prevent assembly of the nanostructures into supramolecular structures.

Abstract: A thermoelectric apparatus includes a first and a second assemblies, at least a first and a second heat conductors. The first assembly includes a first and a second substrates, and several first thermoelectric material sets disposed between the first and second substrates. The first substrate has at least a first through hole. The second assembly includes a third and a fourth substrates, and several second thermoelectric material sets disposed between the third and fourth substrates. The fourth substrate has at least a second through hole. Each of the first and second thermoelectric material sets has a p-type and an n-type thermoelectric element. The first and second heat conductors respectively penetrate the first and second through holes. Two ends of the first heat conductor respectively connect the second and fourth substrates, while two ends of the second heat conductor respectively connect the first and third substrates.

Abstract: A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Abstract: A method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for dividing the plurality of device regions, and a lower surface (second surface) opposite from the upper surface (first surface), forming upper layer wires on the device regions of the upper surface (first surface), etching the semiconductor wafer from a side of the lower surface (second surface) to form a through hole through which the upper layer wire is exposed, and to form a groove in a region of the lower surface (second surface) corresponding to the partition region of the upper surface (first surface), and dicing the semiconductor wafer to form individual device regions.

Abstract: For the present ferromagnetic tunnel junction structure, employed is a means characterized by using an MgO barrier and using a Co2FeAl full-Heusler alloy for any of the ferromagnetic layers therein. The ferromagnetic tunnel junction structure is characterized in that Co2FeAl includes especially a B2 structure and one of the ferromagnetic layers is formed on a Cr buffer layer. The magnetoresistive element is characterized in that the ferromagnetic tunnel junction structure therein is any of the above-mentioned ferromagnetic tunnel junction structure. Accordingly, a large TMR, especially a TMR over 100% at room temperature can be attained, using Co2FeAl having a smallest ? though not a half-metal.

Abstract: A thermoelectric device and a method for manufacturing the same are provided. The thermoelectric device includes a middle substrate, electrodes, N-type thermopiles, and P-type thermopiles, in which the N-type thermopile and the P-type thermopile are electrically connected to each other by the electrodes in series. The thermoelectric device includes further includes an upper substrate bonded to an upper surface of the middle substrate and a lower substrate bonded to a lower surface of the substrate, such that a temperature difference is provided between opposite sides of each of the N-type thermopiles and the P-type thermopiles.

Abstract: A packaging structure including at least one cavity wherein at least one micro-device is provided, the cavity being bounded by at least a first substrate and at least a second substrate integral with the first substrate through at least one bonding interface consisting of at least one metal or dielectric material, wherein at least one main face of the second substrate provided facing the first substrate is covered with at least one layer of at least one getter material, the bonding interface being provided between the first substrate and the layer of getter material.

Abstract: A method of forming a concave-convex pattern according to an embodiment includes: forming a guide pattern on a base material, the guide pattern having a convex portion; forming a formative layer on the guide pattern, the formative layer including a stacked structure formed by stacking a first layer and a second layer, the first layer including at least one element selected from a first metal element and a metalloid element, the second layer including a second metal element different from the first metal element; selectively leaving the formative layer only at side faces of the convex portions by performing etching on the formative layer; removing the guide pattern; and forming the concave-convex pattern in the base material by performing etching on the base material, with the remaining formative layer being used as a mask.

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: A method of manufacturing a semiconductor optical device including a semiconductor layer includes: forming a semiconductor layer; forming a first dielectric film on a first region of a surface of the semiconductor layer; forming a second dielectric film on a second region of the surface of the semiconductor layer, the second dielectric film having a density higher than that of the first dielectric film; and performing a thermal treatment in a predetermined temperature range after the second dielectric film forming, wherein within the temperature range, as the temperature is lowered, a difference increases between a bandgap in the semiconductor layer below the second dielectric film and a bandgap in the semiconductor layer below the first dielectric film due to the thermal treatment.

Abstract: A method for producing a sealed cavity, including: a) producing a sacrificial layer on a substrate; b) producing a cover layer covering at least the sacrificial layer and a portion of the face of the substrate not covered by the sacrificial layer, the cover layer including lateral flanks forming, with the substrate, an angle of less than 90°; c) producing a hole through one of the lateral flanks of the cover layer such that a maximum distance between the substrate and an edge of the hole is less than approximately 3 ?m, the hole crossing a portion of the cover layer deposited on a portion of the substrate not covered by the sacrificial layer; d) eliminating the sacrificial layer through the hole, forming the cavity; and e) depositing at least one material plugging the hole in a sealed fashion.

Abstract: The inductance of an inductor is increased by forming a conductive wire to have a serpentine shape that weaves through a ferromagnetic core that has a number of segments that are connected together in a serpentine shape where each segment of the ferromagnetic core also has a number of sections that are connected together in a serpentine shape.

Abstract: Provided is a system for measuring an etch stage of an etch process involving one or more layers in a substrate, the etch stage measurement system configured to meet two or more etch stage measurement objectives. The system includes an etch process tool, the etch process tool having an etch chamber, a controller, and process parameters. The etch process tool is coupled to two or more optical metrology devices and at least one etch sensor device measuring an etch process parameter with high correlation to the etch stage. The processor is coupled to the etch process tool and is configured to extract an etch measurement value using a correlation of etch stage measurements to actual etch stage data and etch stage measurement obtained from the two or more metrology devices and the at least one etch process sensor device.

Abstract: A thin film deposition apparatus to remove static electricity generated between a substrate and a mask, and a method of manufacturing an organic light-emitting display device using the thin film deposition apparatus.

Abstract: A laser medium comprises a solid-state host material and dopant species provided within the solid-state host material. A first portion of the dopant species has a first valence state, and a second portion of the dopant species has a second valence state. In an embodiment, a concentration of the first portion of the dopant species decreases radially with increasing distance from a center of the medium, and a concentration of the second portion of the dopant species increases radially with increasing distance from the center of the medium. The laser medium further comprises impurities within the solid-state host material, the impurities converting the first portion of the dopant species having the first valence state into the second portion of dopant species having the second valence state.

Abstract: Provided is a method for designing an etch stage measurement system involving an etch process for one or more layers on a substrate using an etch process tool. The etch process tool uses two or more metrology devices, at least one etch process sensor device, and a metrology processor, the etch stage measurement system configured to meet two or more etch stage measurement objectives. A correlation algorithm using the etch stage measurements to the actual etch stage data is developed and used to extract etch measurement value. If the set two or more etch stage measurement objectives are not met, the optical metrology devices are modified, a different etch process sensor device is selected, the correlation algorithm is refined, and/or the measurement data is enhanced by adjusting for noise.

Abstract: A semiconductor laser module having a substrate and having at least one semiconductor laser situated on the substrate, the substrate having a layer structure which includes at least one primary layer which establishes a thermal contact with the semiconductor laser. The semiconductor laser is designed in such a way that it emits heat pulses having a minimum specific heat of approximately 3 mJ per mm2, preferably approximately 5 mJ/mm2, and having a pulse duration of approximately 100 ?s to approximately 2,000 ?s, and the primary layer has a layer thickness which is between approximately 200 ?m and approximately 2,000 ?m, preferably between approximately 400 ?m and approximately 2,000 ?m.

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including first transistors and interconnecting metal layers to perform at least one first electronic function; providing a second monocrystalline layer on top of the metal layers, wherein the second monocrystalline layer includes second transistors to perform at least one second electronic function and substituting the at least one first electronic function with the at least one second electronic function.

Abstract: A pressure sensor has a sensor body at least partly formed with an electrically insulating material, particularly a ceramic material, defining a cavity facing on which is a diaphragm provided with an electric detector element, configured for detecting a bending of the diaphragm. The sensor body supports a circuit arrangement, including, a plurality of circuit components, among which is an integrated circuit, for treating a signal generated by the detection element. The circuit arrangement includes tracks made of electrically conductive material directly deposited on a surface of the sensor body made of electrically insulating material. The integrated circuit is made up of a die made of semiconductor material directly bonded onto the surface of the sensor body and the die is connected to respective tracks by means of wire bonding, i.e. by means of thin connecting wires made of electrically conductive material.

Abstract: This disclosure provides systems, methods, and apparatus for producing roughness in an electromechanical device by nucleation under plasma CVD conditions. In one aspect, a substrate and at least a first layer are provided. The disclosure further provides gas phase nucleating particles under plasma CVD conditions and depositing a first layer, where the particles are incorporated into the first layer to create roughness in the first layer. The roughness may be transferred to a second layer by conformal deposition of the second layer over the first layer. The roughness of the second layer corresponds to the roughness of the first layer, where the first layer has a roughness greater than or equal to about 20 ? root mean square (RMS).

Abstract: In one embodiment, a capacitor includes a first via level having first metal bars and first vias, such that the first metal bars are coupled to a first potential node. The first metal bars are longer than the first vias. Second metal bars and second vias are disposed in a second via level, the second metal bars are coupled to the first potential node. The second metal bars are longer than the second vias. The second via level is above the first via level and the first metal bars are parallel to the second metal bars. Each of the first metal bars has a first end, an opposite second end, and a middle portion between the first and the second ends. Each of the middle portions of the first metal bars and the second ends of the first metal bars do not contact any metal line.

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.

Abstract: It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semiconductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over a first conductive layer and a second conductive layer over the organic compound layer including an insulator. Further, the semiconductor device is manufactured by forming a first conductive layer, discharging a composition of an insulator and an organic compound over the first conductive layer to form an organic compound layer including an insulator, and forming a second conductive layer over the organic compound layer including an insulator.

Abstract: In a manufacturing method of a semiconductor device, a substrate including single crystalline silicon is prepared, a reformed layer that continuously extends is formed in the substrate, and the reformed layer is removed by etching. The forming the reformed layer includes polycrystallizing a portion of the single crystalline silicon by irradiating the substrate with a pulsed laser beam while moving a focal point of the laser beam in the substrate.

Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.

Abstract: Structures having a hybrid MEMS RF switch and method of fabricating such structures using existing wiring layers of a device is provided. The method of manufacturing a MEMS switch includes forming a forcing electrode from a lower wiring layer of a device and forming a lower electrode from an upper wiring layer of the device. The method further includes forming a flexible cantilever arm over the forcing electrode and the lower electrode such that upon application of a voltage to the forcing electrode, the flexible cantilever arm will contact the lower electrode to close the MEMS switch.

Abstract: The present invention provides a microscale pressure sensor that exhibits high sensitivity in a small form factor. The sensor is a bridged device in which a photonic crystal waveguide, surrounded by a photonic crystal slab, is suspended over a dielectric substrate. Under applied pressure, the photonic crystal waveguide is deflected toward the substrate, causing a decrease in optical transmission across the waveguide due to the coupling of the evanescent field of the guided mode to the dielectric substrate. In a preferred embodiment, the waveguide is coupled to a photonic crystal microcavity, which increases evanescent coupling.