Abstract: An image sensor includes a photoelectric converter, a reflector, and a charge carrier guiding region. The reflector is disposed under the photoelectric converter, and the charge carrier guiding region is disposed between the photoelectric converter and the reflector. The reflector reflects incident light passed by the photoelectric converter back through the photoelectric converter for increasing photoelectric conversion efficiency and reduced crosstalk. The charge carrier guiding region dissipates undesired charge carriers for further increasing photoelectric conversion efficiency.

Abstract: A method of double patterning is disclosed. The method includes forming a first photosensitive layer; exposing the first photosensitive layer using a first reticle; developing the first photosensitive layer thereby forming a first image pattern including first elements; forming a second photosensitive layer; exposing the second photosensitive layer using the first reticle; and developing the second photosensitive layer thereby forming a second image pattern.

Abstract: Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a process common to external input/output circuits I/O. The first power domains include second power domains SPD11 to SPD42 including logic blocks, control circuit blocks SCB1 to SCB4, and thin-film power switches SWN11 to SWN42 that are connected to the thick-film power switches via virtual ground lines VSSM1 to VSSM4, and formed by thin-film power transistors manufactured in a process common to the logic blocks. In this way, power switches having different thickness of gate insulating films from one another are vertically stacked so as to be in a hierarchical structure, and each power switch is individually controlled by a power switch controller and a control circuit block correspondingly to each mode.

Abstract: A wafer having a heat dissipation structure is provided. The wafer having the heat dissipation structure includes a wafer and a number of metallic heat dissipation parts. The wafer has a first surface and a second surface opposite thereto. Besides, a number of blind holes are formed on the second surface of the wafer. The metallic heat dissipation parts are partially embedded in the blind holes respectively and protrude from the second surface of the wafer.

Abstract: A semiconductor device according to the present invention includes: a first region having a first conductive type; a plurality of second regions having a second conductive type that differs from the first conductive type, and formed to be arranged in the first region; a plurality of third regions having the first conductive type and formed in the second regions; an electrode forming a channel between the first region and the third region; and a plurality of extended second regions having the second conductive type, arranged in the first region such as to individually include one of the second regions and having an impurity density that is lower than an impunity density of the second regions.

Abstract: The claimed subject matter provides systems and/or methods that facilitate mitigating an impact resulting from mismatch between signal chains in a CMOS imaging System-on-Chip (iSoC) sensor. Two-by-two pixel structures can be a basic building block upon which a pixel array is constructed. Further, each two-by-two pixel structure can be associated with a read bus that carries a sampled signal to a top end and a bottom end of a chip. Moreover, multiplexers at either end of the chip can select a subset of the read buses from which to receive a subset of the sampled signals. Accordingly, pixels in a first color plane can be read, processed, etc. on the same side of the chip (e.g., utilizing a common signal chain), while pixels in at least one second color plane can be read, processed, etc. on the other side of the chip (e.g., employing a differing signal chain).

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.

Abstract: A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The protective layer covers the active device and a part of the insulation layer. The protective layer has a contact window exposing the active device. The pixel electrode is disposed on the protective layer and electrically connected to the active device through the contact window. The patterned semiconductor layer is disposed on the insulation layer above the common line pattern. The patterned semiconductor layer is located between the common line pattern and the pixel electrode.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device may comprise a semiconductor substrate including a main surface configured to define a groove, a trench, and a cavity sequentially disposed downward from a given region of the main surface and open toward the main surface.

Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer on the first semiconductor layer, etching the second semiconductor layer and the first semiconductor layer to form a first groove passing through the second semiconductor layer and the first semiconductor layer, forming a first support having tensile stress in the first groove, etching the second semiconductor layer to form a second groove that exposes the first semiconductor layer, forming a cavity between the second semiconductor layer and the semiconductor substrate by etching the first semiconductor layer through the second groove, forming an insulating film in the cavity, and forming a buried film having tensile stress in the second groove.

Abstract: Embodiments relate to an image sensor and a method for manufacturing the same. According to embodiments, a semiconductor substrate may include a pixel part and a peripheral part. A photo diode pattern may be formed over the pixel part having a height that is greater than a height of a surface of an interlayer dielectric film over the peripheral part. A device isolation film and a metal layer may be provided over the photodiode and over interlayer dielectric film over the peripheral part. A planarization layer may be provided and may compensate for a height difference so that a first metal film pattern connected to the photo diode pattern and a second metal film pattern connected to the metal wire in peripheral part may be simultaneously formed by patterning the planarization layer and metal film.

Abstract: In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, a method may include forming a semiconductor substrate including a pixel part and a peripheral part, forming an interlayer dielectric film including a metal wire on and/or over the semiconductor substrate, forming photo diode patterns on and/or over the interlayer dielectric film and connected to the metal wire in the pixel part, forming a device isolation dielectric layer on and/or over the interlayer dielectric film including the photo diode patterns, forming a first via hole on and/or over the device isolation dielectric layer to partially expose the photo diode patterns, and forming a second via hole on and/or over the device isolation dielectric layer to expose the metal wire in the peripheral part. According to embodiments, vertical integration of transistor circuitry and a photo diode may be achieved.

Abstract: A method for manufacturing a fuse of a semiconductor device comprises forming an island-type metal fuse in a region where a laser is irradiated, so that laser energy may not be dispersed in a fuse blowing process, thereby improving repair efficiency.

Abstract: An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.

Abstract: A capacitor includes a first lower metal layer and an insulating layer on a lower interlayer dielectric layer of a semiconductor substrate; a first upper metal layer aligned on the insulating layer to partially expose it; a first capping layer and an upper interlayer dielectric layer on the insulating layer including the first upper metal layer; a second lower metal layer connected to the first upper metal layer through the upper interlayer dielectric layer and the first capping layer; a second capping layer aligned on the upper interlayer dielectric layer including the second lower metal layer and formed with a hole for partially exposing the second lower metal layer; a pad aligned on the second capping layer and connected to the second lower metal layer; a protective layer on the second capping layer; and a second upper metal layer aligned on the second capping layer.

Abstract: A semiconductor component (has at least one semiconductor chip in which an electrical circuit is integrated. The semiconductor chip is surrounded by an electrically insulating encapsulating compound and has on its surface at least one termination surface for a test signal, which is covered by the encapsulating compound. The termination surface is connected in an electrically conductive manner to an analysis contact that projects above the surface of the semiconductor chip, that is located in the interior of the encapsulating compound at a distance from its exterior surface, and that can be exposed by removing a layer of the encapsulating compound located near the exterior.

Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) apparatus on a substrate (10) comprises the steps of processing the substrate (10) so as to fabricate an electronic circuit (11); depositing a first electrode (15) that is operably coupled with the electronic circuit (11); depositing a membrane (16) so that it is mechanically coupled to the first electrode (15); applying a sacrificial layer (50); depositing a structural layer (18) and a second electrode (17) that is operably coupled with the electronic circuit (11) so that the sacrificial layer (50) is disposed between the membrane (16) and the structural layer (18) so as to form a preliminary structure; singulating the substrate (10); and removing the sacrificial layer (50) so as to form a MEMS structure, in which the step of singulating the substrate (10) is carried out before the step of removing the sacrificial layer (50).

Abstract: The invention discloses a method for fabricating a photoelectric device. A ceramic substrate is first provided, and then a first patterned electrode and a second patterned electrode are formed on and underneath the surface of the ceramic substrate. A plurality of photoelectric devices is sequentially connected to the first electrode layer with a wire solder or a eutectic joint method. The encapsulation materials cover the each photoelectric die to prevent damaged from the external force or environment. Cutting the ceramic substrate along the spaces between the photoelectric dies forms a plurality of independent package units.

Abstract: The present invention relates to a semiconductor device and a method of manufacture thereof, being capable of improving the high integration by increasing a cell region while securing the reliability of device and the process margin through forming a cell region and a core region with the stacking structure.

Abstract: A light emitting element includes a light emitting layer emitting light and a refractive index composite structure layer arranged in a light path of the light output from the light emitting layer.

Abstract: A micromachined sensor having a capacitive sensing structure. The sensor includes a first substrate with first and second conductive layers separated by a buried insulator layer, and a member defined by the first and second conductive layers and the buried insulator layer. A first set of elements defined with the first conductive layer is connected to the member and includes first and second elements that are electrically isolated from each other by the buried insulator layer. A second set of elements is defined with the first conductive layer and capacitively coupled with the first set of elements. A second substrate is bonded to the first substrate so that the member and the first set of elements are movably supported above the second substrate. The second set of elements is anchored to the second substrate, and the first and second sets of elements are physically interconnected through the second substrate.

Abstract: A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

Abstract: The light emitting structure disclosed includes a light emitting device, a metal frame, and a repressing fastener. The light emitting device has a plurality of first coupling terminals, and the metal frame has a plurality of second coupling portions. The light emitting device is disposed in the metal frame, and the first coupling terminals touch the second coupling portions to electrically connect the light emitting device and the metal frame. The repressing fastener is disposed on the light emitting device and fastened to the metal frame to secure the light emitting device in the metal frame. An LED securing device is also disclosed.

Abstract: It is an object of the present invention, in a case of using a conductive material as part of an electrode for an organic transistor, to provide an organic transistor having a structure whose characteristics are not controlled by the work function of the conductive material. Moreover, it is other objects of the present invention to provide an organic transistor having favorable carrier mobility and to provide an organic transistor which is excellent in durability. A composite layer containing an organic compound and an inorganic material is used for an electrode for an organic field effect transistor, that is, at least part of one of a source electrode and a drain electrode in the organic field effect transistor.

Abstract: A thin film transistor includes: an insulation substrate; a semiconductor layer formed on the insulation substrate including, conductive regions that includes impurity, and a channel region sandwiched between the conductive regions; an insulation layer that covers the semiconductor layer; a gate electrode that is formed on the insulator layer at a position where opposes the channel region; and a source electrode and a drain electrode connected to the conductive regions. The channel region divided into a plurality of channel regions and each of channel widths of the plurality of channel regions is in a range from 5 ?m to 30 ?m.

Abstract: A semiconductor device includes: a semiconductor substrate; and an insulating layer formed on at least a main surface of the semiconductor substrate; wherein a contact hole is formed at the insulating layer so as to expose the main surface of the semiconductor substrate through the insulating layer so that a cross section of the contact hole parallel to the main surface of the semiconductor substrate is shaped rectangularly.

Abstract: The present invention provides a light-emitting apparatus capable of improving brightness and reducing power consumption and a method of manufacturing the same. The light-emitting apparatus includes: a light-emitting device 2 including electrode pads 9 and 10; and a lead frame 3 including electrode leads 11 and 12. The electrode pads 9 and 10 and the electrode leads 11 and 12 are electrically connected to each other by bonding wires 14 and 15, and the light-emitting device 2 is arranged with a gap H between the lead frame 3 and the light-emitting device 2. In this way, it is possible to effectively use light emitted from one surface of the light-emitting device 2 facing the lead frame 3. Therefore, it is possible to improve the utilization efficiency of light emitted from the light-emitting device 2.

Abstract: A failure detecting method has inputting a foreign substance inspection map created by foreign substance inspection for a wafer surface after each processing process in a wafer processing process, inputting a die sort map created by a die sort test after the wafer processing process, setting a plurality of region segments in the wafer, setting a region number for each of the region segments, calculating foreign substance density in each of the region segments, based on the foreign substance inspection map, and plotting the foreign substance density, using the region numbers, to calculate a foreign substance inspection map waveform characteristic amount, calculating failure density in each of the region segments, based on the die sort map, and plotting the failure density, using the region numbers, to calculate a die sort map waveform characteristic amount, calculating similarity between the foreign substance inspection map waveform characteristic amount and the die sort map waveform characteristic amount, and

Abstract: A semiconductor integrated circuit device (10) which has a layered structure is composed of a plurality of semiconductor layers (L1, L2, L3) in which an integrated circuit is formed on a substrate. Each of the semiconductor layers (L1, L2, L3) has a semiconductor integrated circuit portion (16) that includes the abovementioned integrated circuit on a substrate (11). Each of the semiconductor layers (L1, L2, L3) also has on a substrate at least one unit of through-wiring (17a) for electrically connecting the integrated circuit included in the semiconductor integrated circuit portion (16) to an integrated circuit of another semiconductor layer, and a surrounding insulation portion (18) for surrounding and insulating the through-wiring from the semiconductor integrated circuit portion.

Abstract: A method for forming a pattern is provided. First, a substrate is provided. Then, a discontinuous film is formed on the substrate so as to reduce the stress of the film. After that, the discontinuous film is patterned to form a pattern. Besides, a method for manufacturing a thin film transistor (TFT) is also provided. First, a substrate is provided. Then, a poly silicon island is formed on the substrate. After that, a gate insulating layer is formed to cover the poly silicon island. Then, a gate is formed on the gate insulating layer. After that, a source/drain is formed in the poly silicon island below one side and the other side of the gate respectively, and a channel layer is formed between the source/drain. At least one of the poly silicon island and the gate is formed according to the above mentioned method for forming the pattern.

Abstract: A pressure sensor for use in a harsh environment including a substrate and a sensor die directly coupled to the substrate by a bond frame positioned between the substrate and the sensor die. The sensor die includes a generally flexible diaphragm configured to flex when exposed to a sufficient differential pressure thereacross. The sensor further includes a piezoelectric or piezoresistive sensing element at least partially located on the diaphragm such that the sensing element provides an electrical signal upon flexure of the diaphragm. The sensor also includes an connecting component electrically coupled to the sensing element at a connection location that is fluidly isolated from the diaphragm by the bond frame. The bond frame is made of materials and the connecting component is electrically coupled to the sensing element by the same materials of the bond frame.

Abstract: A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting other chips and without being affected by other chips. This MCM structure also may facilitate testing of interconnects/connections between two or more chips.

Abstract: In one exemplary embodiment, a detector of electromagnetic radiation includes: a substrate; at least one layer of semiconductor material formed on the substrate, said at least one layer of semiconductor material defining a radiation absorbing and detecting region; an electrical contact configured to couple said region to a readout circuit; and a fuse coupled between the region and the electrical contact. In another exemplary embodiment, a fusible link between a first component and a second component is provided and includes: a fuse with an undercut located underneath at least a portion of the fuse; a first contact coupling the first component to the fuse; and a second contact coupling the second component to the fuse, wherein the undercut is disposed between the first contact and the second contact. In another exemplary embodiment, a fusible link includes a fuse having a layer of material having a negative temperature coefficient of resistance.

Abstract: Apparatus and methods for performing quantum computations are disclosed. Such quantum computational systems may include quantum computers, quantum cryptography systems, quantum information processing systems, quantum storage media, and special purpose quantum simulators.

Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

Abstract: Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.

Abstract: Provided is an organic tunneling p-n junction diode. The organic tunneling p-n junction diode includes an n-doped organic semiconductor layer and a p-doped organic semiconductor layer which are doped with extrinsic impurities. When either a reverse-bias voltage or a forward-bias voltage is applied, the organic tunneling p-n junction diode is turned off within a predetermined voltage range and has exponential voltage-current characteristics outside the predetermined voltage range.

Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.

Abstract: A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

Abstract: A method for fabricating a semiconductor device includes forming an insulating pattern over a semiconductor substrate. An epitaxial growth layer is formed over the semiconductor substrate exposed by the insulating pattern to fill the insulating pattern with the epitaxial growth layer. A recess gate having a recess channel is formed. The recess channel is disposed between two neighboring insulating patterns.

Abstract: A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n?doped region (16) disposed adjacent to the substrate (14), and a p?doped region (18) disposed adjacent to the n?doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p?doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p?doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n?doped region.

Abstract: A semiconductor integrated circuit device has a basic cell structure which allows avoidance of wiring congestion of signal lines or the like. The semiconductor integrated circuit device comprises a plurality of basic cells having predetermined functions, respectively, which are configured by connecting semiconductor elements via wirings. Each of the basic cells has a polygonal shape when viewed from the top. Moreover, a power source line is provided in an inner portion of the basic cell.

Abstract: The manufacturing method of a semiconductor device according to the present invention comprises steps of forming a metal film, an insulating film, and an amorphous semiconductor film in sequence over a first substrate; crystallizing the metal film and the amorphous semiconductor film; forming a first semiconductor element by using the crystallized semiconductor film as an active region; attaching a support to the first semiconductor element by using an adhesive; causing separation between the metal film and the insulating film; attaching a second substrate to the separated insulating film; separating the support by removing the adhesive; forming an amorphous semiconductor film over the first semiconductor element; and forming a second semiconductor element using the amorphous semiconductor film as an active region.

Abstract: In a manufacturing of a semiconductor device, at least one of elements is formed in each of element formation regions of a substrate having a main side and a rear side, and the substrate is thinned by polished from a rear side of the substrate, and then, multiple trenches are formed on the rear side of the substrate, so that each trench reaches the main side of the substrate. After that, an insulating material is deposited over an inner surface of each trench to form an insulating layer in the trench, so that the element formation regions are isolated. Thereby, generation of cracks and structural steps in the substrate and separation of element formation regions from the substrate can be suppressed.

Abstract: An electro-static discharge protection circuit includes a thyristor mode ensuring circuit and a thyristor rectifier circuit. The thyristor mode ensuring circuit includes a capacitive element connected between a higher potential line and a lower potential line, and ensures a constant and sufficient capacity independently of the number of input/output signal bits, even when the number of input/output signal bits is a theoretical minimum, i.e. 1, so that a surge current induced by electro-static discharge (ESD) applied to an output pad is injected into the first capacitive element to charge it. Thus, by means of the current caused by the surge current, the thyristor rectifier circuit is triggered into a thyristor mode, which allows the surge current to flow to the lower potential line through the thyristor rectifier circuit, protecting circuitry against the surge current.

Abstract: An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.

Abstract: An optical receiving apparatus that receives an optical signal and outputs a data value of digital data transmitted by the optical signal is provided, including a light receiving element that receives the optical signal and outputs a photocurrent according to a strength of the optical signal, a present cycle integrator that integrates the photocurrent corresponding to a present cycle of the digital data over a prescribed period within the cycle, a previous cycle integrator that integrates the photocurrent corresponding to a cycle prior to the present cycle over a period that is substantially equal to the prescribed period in the cycle, and a data value identifying circuit that outputs a data value of the present cycle of the digital data based on a difference between a charge amount obtained through integration by the present cycle integrator and a charge amount obtained through integration by the previous cycle integrator.

Abstract: Methods for producing MEMS (microelectromechanical systems) devices with a thick active layer and devices produced by the method. An example method includes heavily doping a first surface of a first silicon wafer with P-type impurities, and heavily doping a first surface of a second silicon wafer with N-type impurities. The heavily doped first surfaces are then bonded together, and a second side of the first wafer opposing the first side of the first wafer is thinned to a desired thickness, which may be greater than about 30 micrometers. The second side is then patterned and etched, and the etched surface is then heavily doped with P-type impurities. A cover is then bonded to the second side of the first wafer, and the second wafer is thinned.