Abstract: A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.

Abstract: The present disclosure provides an optical functional device-mounted module which needs no expensive or special members, can be reduced in size, and provide a producing process thereof. A bank to dam a liquid sealing resin is provided on a substrate around an optical functional device, the substrate being formed with a predetermined wiring pattern and having the optical functional device mounted thereon. The liquid sealing resin is filled between the functional device and the bank by dropping the liquid sealing resin therebetween. A package component member having a light transmission hole corresponding to an optical function part of the optical functional device is brought into contact with the bank such that the light transmission hole is opposed to the function part of the optical functional device, thereby causing the package component member to contact with the liquid sealing resin.

Abstract: An active-matrix addressing substrate improves the degradation of initial alignment of liquid-crystal molecules caused by the steps or level differences due to the pixel electrodes and/or the common electrode. The pixel electrodes are formed on or over the first insulating layer and the common electrode is formed on the second or third insulating layer. The second insulating layer has steps or level differences due to the pixel electrodes in their vicinities. The second insulating layer is made of a dielectric material having fluidity prior to hardening, e.g., an acrylic resin. The steps of the second insulating layer are relaxed, resulting in the gently sloping steps. The steps of an overlying alignment layer due to the common electrode slope gently as well. The thickness of the pixel electrodes, the thickness and inclination angle of the second insulating layer, and the thicknesses of the pixel and common electrodes are defined.

Abstract: To provide a semiconductor device including a thinned substrate with high yield. After forming a protective layer in a predetermined portion (at least a portion covering a side surface of a substrate) of the substrate, grinding and polishing of the substrate are performed. In other words, an element layer including a plurality of integrated circuits is formed over one surface of the substrate, the protective layer is formed in contact with at least the side surface of the substrate, and the substrate is thinned (for example, the other surface of the substrate is ground and polished), the protective layer is removed, and the polished substrate and the element layer is divided so as to form stack bodies including a layer provided with at least one of the plurality of integrated circuits.

Abstract: A solid-state element has: a semiconductor layer formed on a substrate, the semiconductor layer having a first layer that corresponds to an emission area of the solid-state element to and a second layer through which current is supplied to the first layer; a light discharge surface through which light emitted from the first layer is externally discharged, the light discharge surface being located on the side of the substrate; and an electrode having a plurality of regions that are of a conductive material and are in ohmic-contact with the second layer.

Abstract: A semiconductor device with a number of integrated coils is disclosed. In one embodiment, a first coil portion and a second coil portion are at least in part overlapping each other. Another embodiment provides a process for manufacturing a semiconductor device having at least the processes of generating a first coil portion, generating a second coil portion, wherein at least a part of the first coil portion and a part of the second coil portion are overlapping each other.

Abstract: There is provided a silicon member that can prevent the resistivity of a member itself from varying in a semiconductor manufacturing process, in particular, in a plasma processing process, thereby making wafer processing uniform and being not an impurity contamination source to a wafer to be processed, and a method for manufacturing the same. The silicon member having a resistivity of 0.1 ?·cm or more and 100 ?·cm or less is manufactured with steps which are manufacturing a P-type silicon single crystal doped with 13 group atoms of a periodic table having an intrinsic resistivity of 1 ?·cm or more and 100 ?·cm or less, and changing said P-type silicon single crystal into an N-type silicon single crystal by oxygen donors formed by annealing at a temperature of 300° C. or more and 500° C. or less.

Abstract: Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.

Abstract: On a glass substrate, gate bus lines, data bus lines, and TFTs are formed. Then, on the substrate, an insulating film, covering the gate bus lines, data bus lines and TFTs, is formed, and a positive type photoresist film is further formed thereon. Next, through exposure and development processes, the resist film is divided for each picture element and subjected to ultraviolet ray irradiation to harden only a surface layer thereof. Then, the resist film is subjected to heat treatment to form thereon wrinkle-form surface ruggedness of a uniform pattern, which is determined depending on the size of the resist film. Subsequently, reflection electrodes are formed on the resist film. The reflection electrodes are formed to overlap the gate bus line, data bus line and TFTs, and the regions between the adjacent reflection electrodes serve as light transmission regions.

Abstract: Disclosed is an integrated circuit arrangement for safety-critical applications, such as for regulating and controlling tasks in an electronic brake system for motor vehicles. The arrangement includes several electronic, cooperating functional groups (25, 25?), with electric lines (30) provided to interconnect the functional groups (25, 25?). The functional groups consist of a first type and a second type, with the functional groups of the first type having at least the functional group redundant microprocessor system (1) or the functional group input/output devices (19). The functional groups of the second type have at least the functional groups actuator drivers (11, 15, 24, 35) and safety circuits (5, 5?, 7, 7?). The functional groups of the first type and the second type are grouped on a joint chip or chip support member (23).

Abstract: An ESD protection device is provided. The ESD protection device of the present invention includes a semiconductor substrate/well, a first doped region, a second doped region and a third doped region. The first doped region doped with a first dopant is disposed in the semiconductor substrate/well. The second doped region doped with a second dopant is disposed in the semiconductor substrate/well, wherein a predetermined distance is maintained between the second doped region and the first doped region. The third doped region doped with the second dopant is disposed in the first doped region. The ESD protection device of the present invention is adapted for solving the reverse recovery problem of the conventional diode during the bipolar type ESD stressing.

Abstract: Nanoelectromechanical systems are disclosed that utilize vertically grown or placed nanometer-scale beams. The beams may be configured and arranged for use in a variety of applications, such as batteries, generators, transistors, switching assemblies, and sensors. In some generator applications, nanometer-scale beams may be fixed to a base and grown to a desired height. The beams may produce an electric potential as the beams vibrate, and may provide the electric potential to an electrical contact located at a suitable height above the base. In other embodiments, vertical beams may be grown or placed on side-by-side traces, and an electrical connection may be formed between the side-by-side traces when beams on separate traces vibrate and contact one another.

Abstract: A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.

Abstract: A solid-state element has: a semiconductor layer formed on a substrate, the semiconductor layer having a first layer that corresponds to an emission area of the solid-state element to and a second layer through which current is supplied to the first layer; a light discharge surface through which light emitted from the first layer is externally discharged, the light discharge surface being located on the side of the substrate; and an electrode having a plurality of regions that are of a conductive material and are in ohmic-contact with the second layer.

Abstract: A multi-layer package structure for an acoustic microsensor, the package structure mainly utilizes a stack of multiple substrates for housing and protecting circuit elements such that integrated circuit element and acoustic microsensor arranged in recessions of a substrate can reduce volume of the package structure. By adding various sound hole designs, the problem of larger package volume can be effectively solved and sensing frequency of the acoustic microsensor can be increased simultaneously.

Abstract: A lithographic system is provided in which an extent of overlap between pattern sections is adjusted in order to match a size of a pattern section to a size of a repeating portion of the pattern to be formed.

Abstract: Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece. The bulk removal process, for example, can form a first opening that extends to an intermediate depth within the workpiece, but does not extend to the contact surface of the electrically conductive element. After forming the first opening, a second opening is formed from the intermediate depth in the first opening to the contact surface of the conductive element. The second opening has a second width less than the first width of the first opening. This method further includes filling the blind vias with a conductive material and subsequently thinning the workpiece from the exterior side until the cavity is eliminated.

Abstract: A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate to cover the scan lines, the data lines and the active devices. Then, a plasma treatment is performed to the surface of the organic material layer to form a number of concave patterns. The dimension of each of the concave patterns is smaller than one micrometer. Afterward, pixel electrodes are formed on the organic material layer and each of the pixel electrodes is electrically connected to one of the corresponding active devices.

Abstract: Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer.

Abstract: A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridization, antibody/antigen reaction, diagnostics, and biopolymer synthesis. The device can be fabricated using both microlithographic and micro-machining techniques. The device can electronically control the transport and attachment of specific binding entities to specific micro-locations. The specific binding entities include molecular biological molecules such as nucleic acids and polypeptides. The device can subsequently control the transport and reaction of analytes or reactants at the addressed specific micro-locations. The device is able to concentrate analytes and reactants, remove non-specifically bound molecules, provide stringency control for DNA hybridization reactions, and improve the detection of analytes. The device can be electronically replicated.

Abstract: The present application is directed to a method of selectively positioning sub-resolution assist features (SRAF) in a photomask pattern for an interconnect. The method comprises determining if a first interconnect pattern option will result in improved circuit performance compared with a second interconnect pattern option, where the first option is designed to be formed with SRAF and the second option is designed to be formed without SRAF. If it is determined that the first option will result in improved circuit performance, the first pattern option is selected as a target pattern and one or more SRAF patterns are positioned to facilitate patterning of the first pattern option. If it is not determined that the first option will result in improved performance, the second pattern option is selected as a target pattern.

Abstract: SOI wafers are manufactured to have very thin device layers of high surface quality. The layer is ?20 nm in thickness, has an HF density of ?0.1/cm2, and a surface roughness of 0.2 nm RMS.

Abstract: A biochemical semiconductor chip laboratory is disclosed including a coupled address and control chip for biochemical analyses and a method for producing the same. In at least one embodiment the semiconductor chip laboratory has a semiconductor sensor chip, which provides numerous analytical positions for biochemical samples in a matrix. The sensor chip is located on the address and control chip and the analytical positions are in electric contact with a printed contact structure on the upper face of the address and control chip via low-resistance through-platings through the semiconductor substrate of the semiconductor chip.

Abstract: A separated MEMS thermal actuator is disclosed which is largely insensitive to creep in the cantilevered beams of the thermal actuator. In the separated MEMS thermal actuator, a inlaid cantilevered drive beam formed in the same plane, but separated from a passive beam by a small gap. Because the inlaid cantilevered drive beam and the passive beam are not directly coupled, any changes in the quiescent position of the inlaid cantilevered drive beam may not be transmitted to the passive beam, if the magnitude of the changes are less than the size of the gap.

Abstract: The invention relates to a radiation detector (1) for detecting low-intensity radiation, especially for detecting individual photons. The radiation detector includes a plurality of rows of image cells (5) with respective pluralities of image cells (5) disposed one after the other and respective signal outputs (6). The radiation to be detected generates signal charge carriers in the individual image cells (5), the charge carriers being transported along the rows of image cells to the respective signal output (6). A plurality of output amplifiers (7) are connected in parallel to one of the signal outputs each of the individual image cell columns and amplify the signal charge carriers. The invention is characterized in that the output amplifiers (7) include respective avalanche amplifiers (8).

Abstract: A semiconductor device has a conductive film formed over a substrate, an insulating film formed over the conductive film, and having a hole on the conductive film, and a conductive plug formed in the hole including a barrier metal film and a conductive film. A nitride concentration of the barrier metal film is decreased towards an interface between the barrier metal film and the conductive film, and the nitride concentration of the side of the barrier metal film is higher than the nitride concentration of the side of the conductive film at the interface.

Abstract: A semiconductor device includes a transistor, a first diode, and a second diode. A collector of the transistor and a cathode of the first diode are electrically connected. The collector of the transistor and a cathode of the second diode are electrically connected, and an emitter of the transistor and an anode of the second diode are electrically connected. The first diode and the second diode are formed in an identical substrate. Thereby, the semiconductor device can be produced in a smaller size and in less steps.

Abstract: A semiconductor region having an upper surface and a side surface is formed on a substrate. A first impurity region is formed in an upper portion of the semiconductor region. A second impurity region is formed in a side portion of the semiconductor region. The resistivity of the second impurity region is substantially equal to or smaller than that of the first impurity region.

Abstract: A CMOS structure and a method for fabricating the CMOS structure include a first transistor located within a first semiconductor substrate region having a first polarity. The first transistor includes a first gate electrode that includes a first metal containing material layer and a first silicon containing material layer located upon the first metal containing material layer. The CMOS structure also includes a second transistor located within a laterally separated second semiconductor substrate region having a second polarity that is different than the first polarity The second transistor includes a second gate electrode comprising a second metal containing material layer of a composition that is different than the first metal containing material layer, and a second silicon containing material layer located upon the second metal containing material layer. The first silicon containing material layer and the first semiconductor substrate region comprise different materials.

Abstract: New spin-on, bonding compositions and methods of using those compositions are provided. The cured bonding compositions comprise a crosslinked oxazoline (either crosslinked with another oxazoline or with a crosslinking agent), and can be used to bond an active wafer to a carrier wafer or substrate to assist in protecting the active wafer and its active sites during subsequent processing and handling. The compositions form bonding layers that are chemically and thermally resistant, but that can be thermally decomposed at 285° C. or higher to allow the wafers to slide apart at the appropriate stage in the fabrication process.

Abstract: The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).

Abstract: Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below.

Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract: A method of fabricating a stacked nanostructure array includes preparing a substrate; forming a bottom electrode directly on the substrate; growing a first nanostructure array directly on the bottom electrode; forming an insulating layer on the first nanostructure array; exposing the upper surface of the first nanostructure array; depositing a second, and subsequent, nanostructure array on a nanostructure array immediately below the second and subsequent nanostructure array; repeating said forming, said exposing and said depositing a subsequent steps to form a stacked nanostructure array; removing an uppermost insulating layer; and forming a top electrode on an uppermost nanostructure array. A sensor incorporating the nanostructure array includes top and bottom electrodes with plural layers of nanostructure array therebetween.

Abstract: A method of forming a semiconductor device can include forming a trench in a semiconductor substrate to define an active region. The trench is filled with a first device isolation layer. A portion of the first device isolation layer is etched to recess a top surface of the first device isolation layer below an adjacent top surface of the active region of the semiconductor substrate and to partially expose a sidewall of the active region. The exposed sidewall of the active region is epitaxially grown to form an extension portion of the active region that extends partially across the top surface of the first device isolation layer in the trench. A second device isolation layer is formed on the recessed first device isolation layer in the trench. The second device isolation layer is etched to expose a top surface of the extension portion of the active region and leave a portion of the second device isolation layer between extension portions of active regions on opposite sides of the trench.

Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Abstract: The present invention concerns an element designed to interconnect at least two conductors of a microelectronic circuit, including: an initial conductor (210), referred to as lower conductor; a dielectric layer (230) situated on said initial conductor; a second conductor (220), referred to as upper conductor, on said dielectric layer; a cavity (240) in the dielectric layer emerging, on the one hand, on the lower conductor and, on the other hand, on the upper conductor. The upper conductor (220) forms a bridge above the lower conductor (210) and the cavity (240) forms, at a level where it emerges on the upper conductor (243), two vents on both sides of the latter.

Abstract: Provided are an electrical fuse, a semiconductor device having the same, and a method of programming and reading the electrical fuse. The electrical fuse includes first and second anodes disposed apart from each other. A cathode is interposed between the first and second anodes. A first fuse link couples the first anode to the cathode, and a second fuse link couples the second anode to the cathode.

Abstract: The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.

Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

Abstract: An inductor formed on a semiconductor substrate is provided in the present invention. The inductor comprises a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer comprises at least one insulator slot, and each insulator slot is encompassed in the metal layer.

Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.

Abstract: A method for singulating a substrate such as a semiconductor wafer populated with a plurality of MEMS devices. A preferred embodiment of the present invention comprises mounting a glass cover onto the wafer, then orienting the wafer and removably mounting it on an adhesive tape. A partial cut or series of partial cuts is then made through the cover to facilitate the later removal of selected cover portions using an automated process. The dice are then separated using a series of full cuts made perpendicular and parallel to the partial cuts and the selected cover portions removed from each die. The separated dice are then packaged for use or for further fabrication.

Abstract: A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.

Abstract: An improved compensation circuit that compensates for lifetime performance drifts due to aging of integrated circuits to improve the circuit performance.

Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.

Abstract: Herein described are at least a layout of an integrated circuit chip that is resistant to the negative effects of IR power supply voltage drops and a method of implementing the integrated circuit chip. The integrated circuit chip layout comprises one or more capacitors positioned in between adjacent functional blocks. The one or more capacitors provide a charge reservoir for use by functional blocks that are affected by IR power supply voltage drops. The method for implementing the integrated circuit chip comprises positioning one or more capacitors in between adjacent functional blocks and connecting one end of each of the one or more capacitors to a power supply rail while connecting the other end to a ground rail. Each of the one or more capacitors may be implemented using a polysilicon layer and an N-well layer.