With Two-dimensional Charge Carrier Gas Channel (e.g., Hemt; With Two-dimensional Charge-carrier Layer Formed At Heterojunction Interface) (epo) Patents (Class 257/E29.246)
-
Patent number: 8735940Abstract: There are provided a semiconductor device and a method for manufacturing the same.Type: GrantFiled: December 10, 2010Date of Patent: May 27, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park, Jung Hee Lee
-
Patent number: 8735942Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.Type: GrantFiled: February 15, 2012Date of Patent: May 27, 2014Assignee: Fujitsu LimitedInventors: Tadahiro Imada, Atsushi Yamada
-
Patent number: 8729604Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.Type: GrantFiled: December 22, 2011Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventor: Naoko Kurahashi
-
Patent number: 8729644Abstract: A III-nitride semiconductor device which includes a charged gate insulation body.Type: GrantFiled: May 30, 2013Date of Patent: May 20, 2014Assignee: International Rectifier CorporationInventor: Michael A. Briere
-
Patent number: 8723226Abstract: An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.Type: GrantFiled: November 22, 2011Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventor: Sandeep Bahl
-
Patent number: 8723227Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.Type: GrantFiled: September 24, 2012Date of Patent: May 13, 2014Assignee: Analog Devices, Inc.Inventors: Srivatsan Parthasarathy, Javier Alejandro Salcedo, Shuyun Zhang
-
Patent number: 8723228Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. An electrical segregation region is formed in the third semiconductor layer between the gate electrode and the drain electrode.Type: GrantFiled: March 12, 2013Date of Patent: May 13, 2014Assignee: LG Innotek Co., Ltd.Inventor: Jung Hun Oh
-
Patent number: 8723224Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.Type: GrantFiled: September 14, 2012Date of Patent: May 13, 2014Assignee: Sharp Kabushiki KaishaInventors: Nobuyuki Ito, John Kevin Twynam
-
Patent number: 8716075Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.Type: GrantFiled: February 7, 2013Date of Patent: May 6, 2014Assignee: Micron Technology, Inc.Inventors: Jun Liu, Michael P. Violette, Chandra Mouli, Howard Kirsch, Di Li
-
Patent number: 8709886Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.Type: GrantFiled: July 23, 2012Date of Patent: April 29, 2014Assignee: Fujitsu LimitedInventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
-
Patent number: 8710548Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.Type: GrantFiled: June 7, 2010Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka
-
Patent number: 8710511Abstract: An N-face GaN HEMT device including a semiconductor substrate, a buffer layer including AlN or AlGaN deposited on the substrate, a barrier layer including AlGaN or AlN deposited on the buffer layer and a GaN channel layer deposited on the barrier layer. The channel layer, the barrier layer and the buffer layer create a two-dimensional electron gas (2-DEG) layer at a transition between the channel layer and the barrier layer.Type: GrantFiled: July 29, 2011Date of Patent: April 29, 2014Assignee: Northrop Grumman Systems CorporationInventors: Vincent Gambin, Xing Gu, Benjamin Heying
-
Patent number: 8704273Abstract: A semiconductor device includes a nitride semiconductor layer having a (0001) face and a (000-1) face, formed above a common substrate; a (0001) face forming layer provided partially between the substrate and the nitride semiconductor layer; a source electrode, a drain electrode, and a gate electrode, provided on the nitride semiconductor layer having the (0001) face; and a hole extracting electrode provided on the nitride semiconductor layer having the (000-1) face.Type: GrantFiled: June 3, 2010Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventors: Naoya Okamoto, Atsushi Yamada
-
Publication number: 20140103398Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.Type: ApplicationFiled: October 15, 2012Publication date: April 17, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
-
Patent number: 8698162Abstract: Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heat dissipation substrate (that is, a thermal conductive substrate); a GaN-based multi-layer arranged on the heat dissipation substrate and having N-face polarity; and a heterostructure field effect transistor (HFET) or a Schottky electrode arranged on the GaN-based multi-layer. The HFET device may include a gate having a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used.Type: GrantFiled: September 1, 2011Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-hoon Lee, Ki-se Kim
-
Patent number: 8698200Abstract: Described herein is a liquid crystal (LC) device having Gallium Nitride HEMT electrodes. The Gallium Nitride HEMT electrodes can be grown on a variety of substrates, including but not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium flouride buffer layer), and spinel. Also described is a structure provided from GaN HEMT grown on large area silicon substrates and transferred to another substrate with appropriate properties for OPA devices. Such substrates include, but are not limited to sapphire, silicon carbide, silicon, fused silica (using a calcium fluoride buffer layer), and spinel. The GaN HEMT structure includes an AlN interlayer for improving the mobility of the structure.Type: GrantFiled: August 10, 2012Date of Patent: April 15, 2014Assignee: Raytheon CompanyInventors: Daniel P. Resler, William E. Hoke
-
Patent number: 8697506Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.Type: GrantFiled: March 13, 2012Date of Patent: April 15, 2014Assignee: General Electric CompanyInventors: Vinayak Tilak, Alexei Vertiatchikh, Kevin Sean Matocha, Peter Micah Sandvik, Siddharth Rajan
-
Patent number: 8698201Abstract: A method for fabricating a gate structure for a field effect transistor having a buffer layer on a substrate, a channel layer and a barrier layer over the channel layer includes forming a gate of a first dielectric, forming first sidewalls of a second dielectric on either side and adjacent to the gate, selectively etching into the buffer layer to form a mesa for the field effect transistor, depositing a dielectric layer over the mesa, planarizing the dielectric layer over the mesa to form a planarized surface such that a top of the gate, tops of the first sidewalls, and a top of the dielectric layer over the mesa are on the same planarized surface, depositing metal on the planzarized surface, annealing to form the gate into a metal silicided gate, and etching to remove excess non-silicided metal.Type: GrantFiled: August 15, 2013Date of Patent: April 15, 2014Assignee: HRL Laboratories, LLCInventors: Dean C. Regan, Keisuke Shinohara, Andrea Corrion, Ivan Milosavljevic, Miroslav Micovic, Peter J. Willadsen, Colleen M. Butler, Hector L. Bracamontes, Bruce T. Holden, David T. Chang
-
Patent number: 8698286Abstract: The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer. The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).Type: GrantFiled: February 12, 2013Date of Patent: April 15, 2014Assignee: Cree, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo
-
Publication number: 20140097469Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device and methods of fabrication thereof are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).Type: ApplicationFiled: October 4, 2012Publication date: April 10, 2014Inventors: Helmut Hagleitner, Zoltan Ring
-
Publication number: 20140097441Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.Type: ApplicationFiled: October 5, 2012Publication date: April 10, 2014Applicant: Micron Technology, Inc.Inventors: Martin F. Schubert, Vladimir Odnoblyudov, Cem Basceri, Thomas Gehrke
-
Patent number: 8692294Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.Type: GrantFiled: January 24, 2013Date of Patent: April 8, 2014Assignee: Transphorm Inc.Inventors: Rongming Chu, Robert Coffie
-
Publication number: 20140091309Abstract: A predisposed high electron mobility transistor (HEMT) is disclosed. The predisposed HEMT includes a buffer layer, a HEMT channel layer on the buffer layer, a first HEMT barrier layer over the HEMT channel layer, and a HEMT cap layer on the first HEMT barrier layer. The HEMT cap layer has a drain region, a source region, and a gate region. Further, the HEMT cap layer has a continuous surface on the drain region, the source region, and the gate region. When no external voltage is applied between the source region and the gate region, the gate region either depletes carriers from the HEMT channel layer or provides carriers to the HEMT channel layer, thereby selecting a predisposed state of the predisposed HEMT.Type: ApplicationFiled: October 1, 2012Publication date: April 3, 2014Applicant: CREE, INC.Inventor: Christer Hallin
-
Publication number: 20140091308Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Niloy MUKHERJEE, Niti GOEL, Sanaz KABEHIE, Seung Hoon SUNG, Ravi PILLARISETTY, Robert S. CHAU
-
Publication number: 20140084347Abstract: A protection circuit including a multi-gate high electron mobility transistor (HEMT), a forward conduction control block, and a reverse conduction control block is provided between a first terminal and a second terminal. The multi-gate HEMT includes an explicit drain/source, a first depletion-mode (D-mode) gate, a first enhancement-mode (E-mode) gate, a second E-mode gate, a second D-mode gate, and an explicit source/drain. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward conduction control block turns on the second E-mode gate when a voltage difference between the first and second terminals is greater than a forward conduction trigger voltage, and the reverse conduction control block turns on the first E-mode gate when the voltage difference is more negative than a reverse conduction trigger voltage.Type: ApplicationFiled: September 24, 2012Publication date: March 27, 2014Applicant: ANALOG DEVICES, INC.Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy, Shuyun Zhang
-
Patent number: 8680579Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.Type: GrantFiled: September 22, 2008Date of Patent: March 25, 2014Assignee: International Rectifier CorporationInventor: Michael A. Briere
-
Patent number: 8680535Abstract: A HEMT includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer, and a passivation material layer having one or more buried portions contacting or almost contacting the UID GaN layer. A carrier channel layer at the interface of the donor-supply layer and the UID GaN layer has patches of non-conduction in a drift region between the gate and the drain. A method for making the HEMT is also provided.Type: GrantFiled: January 20, 2012Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Wei Yao, Chun-Wei Hsu, Chen-Ju Yu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chih-Wen Hsiung, King-Yuen Wong
-
Patent number: 8680578Abstract: A III-nitride based field effect transistor obtains improved performance characteristics through manipulation of the relationship between the in-plane lattice constant of the interface of material layers. A high mobility two dimensional electron gas generated at the interface of the III-nitride materials permits high current conduction with low ON resistance, and is controllable through the manipulation of spontaneous polarization fields obtained according to the characteristics of the III-nitride material. The field effect transistor produced can be made to be a nominally on device where the in-plane lattice constants of the material forming the interface match. A nominally off device may be produced where one of the material layers has an in-plane lattice constant that is larger than that of the other layer material. The layer materials are preferably InAlGaN/GaN layers that are particularly tailored to the characteristics of the present invention.Type: GrantFiled: August 23, 2007Date of Patent: March 25, 2014Assignee: International Rectifier CorporationInventor: Robert Beach
-
Patent number: 8674407Abstract: The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0?x?1), a channel layer composed of InyGa1-yN (0?y?1) with compressive strain and a contact layer composed of AlzGa1-zN (0?z?1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.Type: GrantFiled: March 12, 2009Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Yuji Ando, Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
-
Patent number: 8669163Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; a gate electrode over the gate dielectric; and a first source/drain region adjacent the gate dielectric. The first source/drain region is of a first conductivity type. At least one of the channel region and the first source/drain region includes a superlattice structure. The semiconductor device further includes a second source/drain region on an opposite side of the channel region than the first source/drain region. The second source/drain region is of a second conductivity type opposite the first conductivity type. At most, one of the first source/drain region and the second source/drain region comprises an additional superlattice structure.Type: GrantFiled: October 5, 2010Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Wen-Chin Lee, Carlos H. Diaz
-
Patent number: 8669591Abstract: The present invention describes a transistor based on a Hetero junction FET structure, where the metal gate has been replaced by a stack formed by a highly doped compound semiconductor and an insulating layer in order to achieve enhancement mode operation and at the same time drastically reduce the gate current leakage. The combination of the insulating layer with a highly doped semiconductor allows the tuning of the threshold voltage of the device at the desired value by simply changing the composition of the semiconductor layer forming the gate region and/or its doping allowing a higher degree of freedom. In one of the embodiment, a back-barrier layer and a heavily doped threshold tuning layer are used to suppress Short Channel Effect phenomena and to adjust the threshold voltage of the device at the desired value. The present invention can be realized both with polar and non-polar (or semi-polar) materials.Type: GrantFiled: December 27, 2011Date of Patent: March 11, 2014Assignee: Eta Semiconductor Inc.Inventors: Fabio Alessio Marino, Paolo Menegoli
-
Publication number: 20140061724Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain.Type: ApplicationFiled: August 29, 2012Publication date: March 6, 2014Inventors: Chih-Fang Huang, Chien-Wei Chiu, Ting-Fu Chang, Tsung-Yu Yang, Tsung-Yi Huang
-
Patent number: 8664696Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.Type: GrantFiled: March 21, 2011Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
-
Patent number: 8659055Abstract: Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4.Type: GrantFiled: June 16, 2010Date of Patent: February 25, 2014Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Kazuki Ota, Takashi Inoue, Hironobu Miyamoto, Tatsuo Nakayama, Yuji Ando
-
Patent number: 8653562Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.Type: GrantFiled: December 28, 2011Date of Patent: February 18, 2014Assignee: WIN Semiconductor Corp.Inventors: Cheng-Guan Yuan, Shih-Ming Joseph Liu
-
Patent number: 8653559Abstract: A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.Type: GrantFiled: June 29, 2011Date of Patent: February 18, 2014Assignee: HRL Laboratories, LLCInventors: Andrea Corrion, Karim S. Boutros, Mary Y. Chen, Samuel J. Kim, Rongming Chu, Shawn D. Burnham
-
Publication number: 20140042446Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hao Chiang, Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu
-
Publication number: 20140042448Abstract: A semiconductor device includes a semiconductor body having a compound semiconductor material on a substrate. The compound semiconductor material has a channel region. A source region extends to the compound semiconductor material. A drain region also extends to the compound semiconductor material and is spaced apart from the source region by the channel region. An insulating region is buried in the semiconductor body between the compound semiconductor material and the substrate in an active region of the semiconductor device. The active region includes the source, the drain and the channel region of the device. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.Type: ApplicationFiled: August 13, 2012Publication date: February 13, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
-
Patent number: 8648390Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.Type: GrantFiled: February 25, 2013Date of Patent: February 11, 2014Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis J. Kub, Karl D. Hobart, Charles R. Eddy, Jr., Michael A. Mastro, Travis Anderson
-
Patent number: 8637905Abstract: The invention relates to a semiconductor device and a fabrication method thereof. A semiconductor device according to an aspect of the invention comprising: a semiconductor layer on a substrate; an isolation layer on the semiconductor layer; a source and a drain which are in contact with the semiconductor layer, each of the source and the drain comprises multiple fingers, and the multiple fingers of the source intersect the multiple fingers of the drain; and a gate on the isolation layer, the gate is located between the source and the drain and comprises a closed ring structure which encircles the multiple fingers of the source and the drain.Type: GrantFiled: August 18, 2010Date of Patent: January 28, 2014Assignee: Dynax Semiconductor, Inc.Inventor: Naiqian Zhang
-
Patent number: 8637903Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.Type: GrantFiled: July 19, 2011Date of Patent: January 28, 2014Assignee: Fujitsu LimitedInventor: Toshihide Kikkawa
-
Patent number: 8633518Abstract: Enhancement mode III-nitride devices are described. The 2DEG is depleted in the gate region so that the device is unable to conduct current when no bias is applied at the gate. Both gallium face and nitride face devices formed as enhancement mode devices.Type: GrantFiled: December 21, 2012Date of Patent: January 21, 2014Assignee: Transphorm Inc.Inventors: Chang Soo Suh, Umesh Mishra
-
Patent number: 8633519Abstract: Provided is an HEMT exhibiting a normally-off characteristic and low on-state resistance, which includes a first carrier transport layer; two separate second carrier transport layers formed of undoped GaN and provided on two separate regions of the first carrier transport layer; and carrier supply layers formed of AlGaN and respectively provided on the two separate second carrier transport layers. The second carrier transport layers and the carrier supply layers are respectively formed through crystal growth on the first carrier transport layer. The heterojunction interface between the second carrier transport layer and the carrier supply layer exhibits high flatness, and virtually no growth-associated impurities are incorporated in the vicinity of the heterojunction interface. Therefore, reduction in mobility of 2DEG is prevented, and on-state resistance is reduced.Type: GrantFiled: September 20, 2010Date of Patent: January 21, 2014Assignee: Toyoda Gosei Co., Ltd.Inventor: Toru Oka
-
Patent number: 8633494Abstract: A semiconductor device includes a buffer layer that is disposed over a substrate, a high-resistance layer that is disposed over the buffer layer, the high-resistance layer being doped with a transition metal for achieving high resistance, a low-resistance region that is disposed in a portion of the high-resistance layer or over the high-resistance layer, the low-resistance region being doped with an impurity element for achieving low resistance, an electron travel layer that is disposed over the high-resistance layer including the low-resistance region, an electron supply layer that is disposed over the electron travel layer, a gate electrode that is disposed over the electron supply layer, and a source electrode and a drain electrode that are disposed over the electron supply layer.Type: GrantFiled: July 19, 2012Date of Patent: January 21, 2014Assignee: Fujitsu LimitedInventors: Masato Nishimori, Toshihide Kikkawa
-
Patent number: 8633094Abstract: A method of fabricating a multi-layer structure for a power transistor device includes performing, within a reaction chamber, a nitrogen plasma strike, resulting in the formation of a nitride layer directly on a nitride-based active semiconductor layer. A top surface of the nitride layer is then exposed to a second source. A subsequent nitrogen-oxygen plasma strike results in the formation of an oxy-nitride layer directly on the nitride layer. The nitride layer comprises a passivation layer and the oxy-nitride layer comprises a gate dielectric of the power transistor device.Type: GrantFiled: December 1, 2011Date of Patent: January 21, 2014Assignee: Power Integrations, Inc.Inventors: Jamal Ramdani, Linlin Liu, John Paul Edwards
-
Publication number: 20140014966Abstract: A semiconductor structure having mesa structure comprising: a lower semiconductor layer; an upper semiconductor layer having a higher band gap than, and in direct contact with, the lower semiconductor layer to form a two-dimension electron gas (2DEG) region between the upper semiconductor layer. The 2DEG region has outer edges terminating at sidewalls of the mesa. An additional electron donor layer has a band gap higher than the band gap of the lower layer disposed on sidewall portions of the mesa structure and on the region of the 2DEG region terminating at sidewalls of the mesa. An ohmic contact material is disposed on the electron donor layer. In effect, a sideway HEMT is formed with the electron donor layer, the 2DEG region and the ohmic contact material increasing the concentration of electrons (i.e., lowering ohmic contact resistance) all along the contact between the lower semiconductor layer and the electron donor layer.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicant: Raytheon CompanyInventors: Kamal Tabatabaie, William E. Hoke, Eduardo M. Chumbes, Kevin McCarthy
-
Patent number: 8629479Abstract: A semiconductor device includes a first GaN layer provided on a SiC substrate, a second GaN layer provided on the first GaN layer, and an electron supply layer that is provided on the second GaN layer and has a band gap greater than that of GaN, the first GaN layer having an acceptor concentration higher than that of the second GaN layer.Type: GrantFiled: July 28, 2011Date of Patent: January 14, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ken Nakata, Isao Makabe, Keiichi Yui
-
Patent number: 8629454Abstract: A semiconductor device includes: a nitride semiconductor layer; a source electrode, a gate electrode and a drain electrode; an insulating layer covering at least the gate electrode and a part of the nitride semiconductor layer; and a field plate on the insulating layer, a width of a region of the field plate between an edge of the field plate of a side of the drain electrode and an edge of the side face of the insulating layer covering a side face of the gate electrode of a side of the drain electrode being 0.1 ?m or more, a distance between an edge of the field plate and an edge of the drain electrode in a contact face between the nitride semiconductor layer and the drain electrode being 3.5 ?m or more, an operating frequency of the semiconductor device being 4 GHz or less.Type: GrantFiled: June 4, 2012Date of Patent: January 14, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Fumikazu Yamaki
-
Publication number: 20140008658Abstract: A transistor device includes a heterostructure body having a source, a drain spaced apart from the source and a two-dimensional charge carrier gas channel between the source and the drain. The transistor device further includes a piezoelectric gate on the heterostructure body. The piezoelectric gate is operable to control the channel below the piezoelectric gate by increasing or decreasing a force applied to the heterostructure body responsive to a voltage applied to the piezoelectric gate.Type: ApplicationFiled: July 3, 2012Publication date: January 9, 2014Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Ralf Siemieniec, Gilberto Curatola
-
Publication number: 20140001516Abstract: A semiconductor structure includes a high mobility semiconductor, an interfacial oxide layer, a high dielectric constant (high-k) layer, a stack, a gate electrode, and a gate dielectric. The stack comprises a lower metal layer, a scavenging metal layer comprising a scavenging metal, and an upper metal layer formed on the scavenging metal layer. A Gibbs free energy change of a chemical reaction, in which an atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer combines with a metal oxide material comprising the scavenging metal and oxygen to form the scavenging metal in elemental form and oxide of the atom constituting the high mobility semiconductor layer that directly contacts the interfacial oxide layer, is positive.Type: ApplicationFiled: September 13, 2012Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi ANDO, Martin M. FRANK, Vijay NARAYANAN