Manufacturing Circuit On Or In Base Patents (Class 29/846)
  • Patent number: 9924883
    Abstract: Disclosed herein are neural probes comprising an L1 polypeptide functional fragment thereof on the exterior surface of the probe, devices including such electrodes, and methods of their use. The disclosed embodiments are useful, for example, for in methods of recording and/or stimulating neural signals in a subject.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 27, 2018
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Xinyan T. Cui, Carl F. Lagenaur, Erdrin Azemi, Noah R. Snyder
  • Patent number: 9917013
    Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and applying a pressure substantially uniformly along the second major surface to batch separate the layer of material in the singulation lines. In one embodiment, a fluid filled vessel can be used to apply the pressure.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 13, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Patent number: 9906879
    Abstract: Disclosed herein, among other things, are systems and methods for solderless module connectors for hearing assistance devices. One aspect of the present subject matter includes a method of assembling a hearing assistance device. According to various embodiments, the method includes providing a structure including a laser-direct structuring (LDS) portion, and inserting a flexible universal circuit module (UCM) having conductive surface traces into the structure. The UCM is electrically connected to the LDS portion using direct compression without the use of wires or solder, according to various embodiments.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: February 27, 2018
    Assignee: Starkey Laboratories, Inc.
    Inventors: David Prchal, Susie Johansson, John Dzarnoski
  • Patent number: 9871897
    Abstract: Apparatuses and methods for creating a sensor stack or element for use in an electronic device. In one example, a method may include providing a substrate made of sapphire; affixing, by physical vapor deposition, a decorative feature on the substrate; providing a silicon layer including a capacitive sensor; and bonding the sensor to the substrate. In one example, the affixing operation may include an icon, logo, symbol or other graphic as the decorative feature. The method may also include reducing the substrate or silicon layer from an initial thickness to a second thickness, the second thickness being thinner that the initiation thickness. The sensor stack may be used or configured as an input button for the electronic device such as a mobile phone, tablet computer, or other computing device.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: January 16, 2018
    Assignee: APPLE INC.
    Inventors: Benjamin B. Lyon, Patrick E. O'Brien, Scott A. Myers
  • Patent number: 9860994
    Abstract: A circuit board having a substrate, a first metal layer, a second metal layer and a solder mask layer. The first metal layer and the second metal layer with unequal surface areas spacedly arranged on the substrate and respectively providing a first solderable region and a second solderable region with equal surface areas. The solder mask layer having an opening and covered on the substrate, the first metal layer and the second metal layer to expose the first solderable region and the second solderable region. Besides, the first metal layer further provides a window abutted to the first solderable region, and the opening exposes a first blank region and a second blank region. Thus, the problem of unequal solder regions due to offset of the solder mask layer can be avoided, and improving the yield rate of the fabrication process.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 2, 2018
    Assignee: Universal Global Technology (Shanghai) Co., Ltd.
    Inventors: Wan-Chen Chan, Chun-Chi Chiu, Hsun-Fa Li
  • Patent number: 9817528
    Abstract: A touch sensitive device includes a plurality of first electrodes; a plurality of second electrodes, disposed around the plurality of first electrodes; a plurality of first surrounding pattern that are formed by the plurality of first electrodes and the plurality of second electrodes and a plurality of second surrounding patterns that are formed by the plurality of first electrodes and the plurality of second electrodes. Each of the first surrounding patterns comprises one of the first electrodes that interleaves with one of the second electrodes. Each of the second surrounding patterns comprises one of the second electrodes that is sandwiched between another of the second electrodes and one of the second electrodes.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 14, 2017
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chia-Wei Hu, Wai Pan Wu, Shen-Feng Tai
  • Patent number: 9780324
    Abstract: An OLED includes a first electrode, a second electrode arranged on the first electrode, a light emitting layer arranged between the first electrode and the second electrode, and a conductive layer arranged within the light emitting layer or being directly contacted with the light emitting layer. In view of the above, by configuring a conductive layer within the OLED, the OLED may be adjusted and balanced by an external voltage such that the OLED may not be limited to the circuit input between two electrodes. In this way, the lighting brightness of the OLED may be adjusted. In addition, the evaporated conductive layer may not damage the light emitting layer, and thus the OLED component of top-emission may be adopted.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: October 3, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Lixuan Chen
  • Patent number: 9723726
    Abstract: A film composite with electrical functionality for application on a substrate includes at least one conductive structure, a first bonding coat, a film layer and a second bonding coat. The first bonding coat is disposed on an underside of the at least one conductive structure, wherein the first bonding coat has an adhesive effect for application of the at least one conductive structure on the substrate. The second bonding coat is disposed between an upper side of the at least one conductive structure and the film layer. The second bonding coat has an adhesive effect, by which the film layer adheres to the at least one conductive structure.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: August 1, 2017
    Assignee: Schreiner Group GmbH & Co. KG
    Inventors: Wolfram Fischer, Olaf Nitschke, Thomas Samuel, Oliver Wiesener
  • Patent number: 9711424
    Abstract: A low thermal stress package for large area semiconductor dies. The package may include a substrate and at least one pedestal extending from the substrate, wherein the pedestal may have a mounting surface that is smaller than a mounting surface of a semiconductor die that is mounted to the pedestal. The bonded area between the die and the pedestal is therefore reduced relative to conventional semiconductor package substrates, as is the amount of thermal stress sustained by the die during thermal cycling.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: July 18, 2017
    Assignee: Littelfuse, Inc.
    Inventors: Richard J. Bono, Neil Solano
  • Patent number: 9666729
    Abstract: An electronic device in the form a two-dimensional array of nanopillars extending generally normal to a substrate is provided. The nanopillars are made from a paraelectric or superparaelectric material. In addition, a linear dielectric medium is located between individual nanopillars. A two-dimensional array of paraelectric or superparaelectric nanopillars and a linear dielectric medium form the effective dielectric medium of a paraelectric or superparaelectric varactor. In some instances, the nanopillars are cylindrical nanopillars that have an average diameter and/or average height/length between 1-300 nanometers. In other instances, the nanopillars are quasi-nanoparticles that form self-aligned nano-junctions. In addition, each of the nanopillars has a single paraelectric or superparaelectric dipole domain therewithin. As such, each of the nanopillars can be void of crystallographic defects, polycrystallinity, interactions between ferroic domains, and defects due to ferroic domain walls.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 30, 2017
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Ryan C. Toonen, Mathew P. Ivill, Melanie W. Cole
  • Patent number: 9639721
    Abstract: An encoding module and related systems and components are provided. The encoding module includes a plurality of encoding elements arranged in an array of columns and rows and one or more switching elements configured to selectively connect the encoding elements to a reader. The connection of the encoding elements may be based on the location of a targeted transponder disposed among multiple adjacent transponders to ensure the selective communication with the targeted transponder only. The module is configured for various types and locations transponders to be used within a system, such as a printer-encoder. Each encoding element may include a loaded conductive strip comprising a loop shape portion and a shield that corresponds to the loop shape portion. In another embodiment, an access control system having an encoding module with the plurality of couplers and an access card having a plurality of transponders corresponding to the couplers is provided.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: May 2, 2017
    Assignee: ZIH Corp.
    Inventors: Boris Y. Tsirline, Robert S. Gawelczyk, Steven R. Kovanko, Anthony Brown, Mao Tian, Karl Torchalski, Michael Fein, Christopher Aiello
  • Patent number: 9596748
    Abstract: A lens mount is attached to a circuit board and covers electrical components on the circuit board. An electrically insulating device is positioned between the lens mount and the circuit board. The circuit board includes a grounding pad adjacent the electrically insulating device. The lens mount includes an aperture aligned with the grounding pad and the electrically insulating device. A conductive glue is dispensed into the aperture to electrically ground the lens mount to the grounding pad. The electrically insulating device seals the conductive glue from the electrical components. A method of grounding a lens mount to a circuit board is provided.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 14, 2017
    Assignee: STMicroelectronics Pte Ltd
    Inventor: Wee Chin Judy Lim
  • Patent number: 9596766
    Abstract: A method of manufacturing a circuit board is described herein. The method may include adding a resin, forming first and second fiberglass fibers, and forming first and second signal line traces capable of transmitting electrical signals. In some examples, a ratio between fiberglass and resin material near the first signal line trace is similar to a ratio between fiberglass and resin material near the second signal line trace. In some examples, the first and second fiberglass fibers diagonally cross near the first and second signal line traces. In some examples, the first and second fiberglass fibers cross near the first and second signal line traces in a zig-zag pattern.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: David N. Shykind, James A. McCall
  • Patent number: 9451705
    Abstract: A touch panel that includes a substrate, a first conductive layer, a second conductive layer, and FPCs including a first FPC and a second FPC, the first FPC is connected to the first conductive layer, the second FPC is connected to the second conductive layer; the first conductive layer includes n rows of first conductive patterns, one end of each row is connected to one end of a first metal wire, the other end of the first metal wire is connected to the first FPC; the second conductive layer includes m columns of second conductive patterns, one end of each column is connected to one end of a second metal wire, the other end of the second metal wire is connected to the second FPC.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 20, 2016
    Assignee: Huawei Device Co., Ltd.
    Inventors: Xingfa Tian, Zengcai Sun, Zhu Liu
  • Patent number: 9423898
    Abstract: A method of preparing an OGS touch screen is disclosed. The method includes forming a first film layer on a provided substrate, where the first film layer includes at least one hollow region and a protection film surrounding each hollow region. The method also includes tempering each hollow region by tempering the substrate, and removing the protection film on the substrate.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: August 23, 2016
    Assignees: Shanghai Tianma Micro-Electronics Co., Ltd., Tianma Micro-Electronics Co., Ltd.
    Inventors: Yujun Li, Bengang Zhao
  • Patent number: 9412708
    Abstract: Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shyh-An Chi
  • Patent number: 9410987
    Abstract: A probe card includes a board or silicon substrate; a plurality of probes (terminals) at a first surface of the board, the respective probes having a first extending portion extending along the first surface of the board; a plurality of through-holes formed in correspondence to the respective probes and penetrating between the first and second surfaces of the board; through electrodes embedded in the respective through-holes and conductively connected to the probes in the respective through-holes; and a wiring at the second surface of the board conductively connected to the through electrodes, the wiring having a second extending portion extending along the second surface of the board, wherein the first extending portion and the second extending portion extend in different directions from each other, and a space is formed across the entire width of the first extending portion between the first extending portion and the first surface of the board.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: August 9, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Goro Nakatani, Masahiro Sakuragi, Koichi Niino
  • Patent number: 9406659
    Abstract: A transistor arrangement comprising an electrically conductive substrate; a semiconductor body including a transistor structure, the transistor structure including a source terminal connected to said substrate; a bond pad providing a connection to the transistor structure configured to receive a bond wire; wherein the semiconductor body includes an RF-return current path for carrying return current associated with said bond wire, said RF-return current path comprising a strip of metal arranged on said body, said strip configured such that it extends beneath said bond pad and is connected to said source terminal of the transistor structure.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: August 2, 2016
    Assignee: Ampleon Netherlands B.V.
    Inventors: Petra Christina Anna Hammes, Josephus Henricus Bartholomeus van der Zanden, Rob Mathijs Heeres, Albert Gerardus Wilhelmus Philipus van Zuijlen
  • Patent number: 9336479
    Abstract: A portable object (10) comprises an integrated circuit (11), a first pad (12) that is mechanically and electrically connected to the integrated circuit (11) and a second pad (13) that is mechanically and electrically connected to the integrated circuit (11). The portable object (10) is designed for data transfer by capacitive coupling of the first pad (12) to a first conducting line (33) and of the second pad (13) to a second conducting line (34), when the portable object (10) is brought in vicinity to the first and the second conducting line (33, 34).
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: May 10, 2016
    Assignee: ams AG
    Inventor: Giuliano Manzi
  • Patent number: 9321633
    Abstract: The present invention relates to a process for producing a 3-dimensional structure assembled from nanoparticles by using a mask having a pattern of perforations, which comprises the steps of: in a grounded reactor, placing a mask having a pattern of perforations corresponding to a determined pattern at a certain distance above a substrate to be patterned, and then applying voltage to the substrate to form an electrodynamic focusing lens; and introducing charged nanoparticles into the reactor, the charged particles being guided to the substrate through the pattern of perforations so as to be selectively attached to the substrate with 3-dimensional shape. According to the process of the present invention, a 3-dimensional structure of various shapes can be produced without producing noise pattern, with high accuracy and high efficiency.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: April 26, 2016
    Assignees: Global Frontier Center for Multiscale Energy Systems, SNU R&DB Foundation
    Inventors: Hoseop Choi, Man Soo Choi
  • Patent number: 9318862
    Abstract: An electrical interconnect including a substrate with at least two adjacent layers configured to translate relative to each other between a nominal position and a translated position. A plurality of through holes are formed through the layers from a first surface of the substrate to a second surface of the substrate in both the nominal position and the translated position. At least one contact member is positioned in the through holes with distal portions accessible from the first surface and a proximal portions positioned near the second surface. The proximal portion of the contact members are secured to the substrate near the second surface with a conductive structure. The two adjacent layers of the substrate are translated from the nominal position to the translated position to elastically deform the contact members within the through holes and to displace the distal portions of the contact members toward the conductive structures, respectively.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 19, 2016
    Assignee: HSIO Technologies, LLC
    Inventor: Jim Rathburn
  • Patent number: 9275934
    Abstract: Aspects of the present disclosure generally relate to a microelectronic package including a plurality of through vias having walls in a glass interposer having a top portion and a bottom portion. The microelectric package may also include a stress relief barrier on at least a portion of the top and bottom portions of the glass interposer. The microelectric package may further include a metallization seed layer on at least a portion of the stress relief layer and a conductor on at least a portion of the metallization seed layer. The conductor extends through at least a portion of the plurality of the through vias, forming a plurality of metalized through package vias. At least a portion of the through vias are filled with the stress relief layer or the metallization seed layer.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 1, 2016
    Assignee: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Venkatesh Sundaram, Fuhan Liu, Rao Tummala, Vijay Sukumaran, Vivek Sridharan, Qiao Chen
  • Patent number: 9265161
    Abstract: An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 16, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chi Hee Ahn, Sang Myung Lee, Yeong Uk Seo, Jin Su Kim, Sung Woon Yoon, Myoung Hwa Nam
  • Patent number: 9244000
    Abstract: A test strip with an incorporated optical waveguide and deflectors punched through the optical waveguide allows light to exit through a layer of the test strip and be detected by a photo detector. Using light and a photodetector, these uniquely coded strips are identified. The waveguide can be constructed by sandwiching two layers of the test strip around a light transmissible layer. This configuration allows light to be transmitted through the test strip and out the other end, as well as allowing some light to escape the deflector. This light is detected by a photodetector mounted in the analyte test meter. The deflectors may be placed in patterns such that detection of this light indicates certain characteristics of the strip, such as non-counterfeit, regional identification, type of analyte tested, and coding information.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: January 26, 2016
    Assignee: AgaMatrix, Inc.
    Inventors: Sridhar Iyengar, Ian Harding, Charles Boiteau, Collin Butters
  • Patent number: 9167688
    Abstract: Micro-wires are arranged to form an electrical conductor connected to an electrode structure. The electrical conductor includes a plurality of spaced-apart first micro-wires extending in a first direction, wherein one of the first micro-wires is a connection micro-wire. A plurality of spaced-apart second micro-wires extends in a second direction different from the first direction. At least two adjacent second micro-wires are spaced apart by a distance greater than the spacing between at least two adjacent first micro-wires. Each second micro-wire is electrically connected to at least two first micro-wires. The electrode structure includes a plurality of electrically connected third micro-wires electrically connected to the connection micro-wire at spaced-apart connection locations and at least some of the adjacent connection locations are separated by a distance greater than any of the distances separating the second micro-wires.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: October 20, 2015
    Assignee: EASTMAN KODAK COMPANY
    Inventors: John Andrew Lebens, David Paul Trauernicht, Yongcai Wang, Ronald Steven Cok
  • Patent number: 9148947
    Abstract: An EBG (electromagnetic bandgap) device with a stacked structure includes a first ground plane, a first power plane, a via, a second power plane, a second ground plane; a third power plane, and several ground vias. The first ground plane, the second power plane, and the second ground plane are connected through the several ground vias. The ground vias and the second power plane do not have actually electrical connection. The first ground plane, the first power plane, the second power plane, and the via form a first EBG structure and the first ground plane, the second ground plane, the third power plane and the several ground vias form a second EBG structure.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 29, 2015
    Assignee: ShenZhen Treasure City Technology Co., LTD.
    Inventor: Shao-You Tang
  • Patent number: 9144158
    Abstract: The apparatus of the present application reduces poor soldering having gas left there at when soldering. in a reflow soldering apparatus for soldering electronic components mounted on a board by heated atmospheric gas while transferring the printed circuit board with the electronic components within preheating chambers and reflow chambers. Reflow chamber in order within a furnace, a pressure reducing chamber capable of reducing a pressure of the atmospheric gas is installed in the reflow chamber where the heated atmospheric gas circulates in the chamber, and gas involved in a heated and melted soldering part on the printed circuit board is removed at the pressure reducing chamber.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: September 22, 2015
    Assignee: Yokota Technica
    Inventor: Yatsuharu Yokota
  • Patent number: 9131606
    Abstract: A pattern of micro-wires in a layer over which ink is to be coated to form micro-wires includes a substrate with first, second, and third regions. A plurality of connected first micro-channels, second micro-channels, and third micro-channels are formed in the first, second, and third regions having first, second, and third micro-channel densities, respectively. The first density is greater than the second density and the second density is greater than the third density. Thus, the density of the layer monotonically decreases from the first region to the second region and from the second region to the third region so that the ink coated over the layer is more effectively distributed.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: September 8, 2015
    Assignee: EASTMAN KODAK COMPANY
    Inventors: John Andrew Lebens, Ronald Steven Cok
  • Patent number: 9125335
    Abstract: A ceramic circuit board for use in packaging an electronic element includes a ceramic-copper plate, and a heat-dissipating unit that is adapted for dissipating heat from the electronic element. The ceramic-copperplate includes a ceramic substrate that has opposite first and second surfaces, and a through-hole formed through the first and second surfaces, a top copper pattern that overlies the first surface of the ceramic substrate and that has at least two conducting portions spaced apart from each other, and a bottom copper layer that underlies the second surface of the ceramic substrate. The heat-dissipating unit includes a heat-dissipating layer that is disposed in the through-hole of the ceramic substrate above the bottom copper layer and that has a thermal conductivity larger than that of the ceramic substrate. A method of making the ceramic circuit board is also disclosed.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: September 1, 2015
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventor: Wen-Chung Chiang
  • Patent number: 9116579
    Abstract: A multi input and multi output (MIMO) sonic touch panel includes at least a sonic touch module and a display module. The sonic touch module includes a first carrier layer, a first vibrating layer and a first conducting layer. The first vibrating layer is disposed at the first carrier layer. The first conducting layer is disposed at the first carrier layer or the first vibrating layer and coupled with the first vibrating layer. The first conducting layer and the first vibrating layer are located at the same side or the opposite side of the first carrier layer. The display module is disposed opposite to the sound touch module. Besides, a MIMO smart sound potential server is also disclosed.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: August 25, 2015
    Inventors: Yue-Shih Jeng, Wei-Chih Liu, Tien-Rong Lu
  • Patent number: 9116169
    Abstract: One plate-like member and the other plate-like member to be aligned with each other are provided with guide holes and guide portions to be received in the guide holes, respectively. The plate-like members are aligned appropriately, and in a state in which this alignment is held, the guide portions are formed on land portions provided on the other plate-like member so as to be aligned with the guide holes. Accordingly, regardless of presence/absence or size of a process error in the guide holes, the guide portions appropriate to the respective guide holes can be formed. Consequently, by aligning the guide portions with the guide holes, the plate-like members can be aligned appropriately without relative fine adjustment between the members.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 25, 2015
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Tomokazu Saito, Seito Moriyama
  • Patent number: 9099982
    Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are provided herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.
    Type: Grant
    Filed: January 25, 2012
    Date of Patent: August 4, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
  • Patent number: 9082821
    Abstract: A method for forming a copper interconnection structure includes the steps of forming an opening in an insulating layer, forming a copper alloy layer including a metal element on an inner surface of the opening, and conducting a heat treatment on the copper alloy layer so as to form a barrier layer. An enthalpy of oxide formation for the metal element is lower than the enthalpy of oxide formation for copper. The heat treatment is conducted at temperatures ranging from 327° C. to 427° C. and for a time period ranging from 1 minute to 80 minutes.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: July 14, 2015
    Assignee: Advanced Interconnect Materials, LLC
    Inventors: Junichi Koike, Akihiro Shibatomi
  • Patent number: 9044929
    Abstract: Disclosed is a printing apparatus which comprises: a base; a frame member installed on the base; a printing section supported by the frame member to subject a board to printing; a board conveying segment provided on the base displaceably; a control section for controlling the driving of the board conveying segment; a mark provided on the frame member; and an image pickup section mounted on the board conveying segment to pick up an image of the mark, wherein the control section is operable to cause the board conveying segment to be displaced so as to allow a board to be set in the printing zone, and, based on the image of the mark picked up by the image pickup section, to perform a strain compensation for correcting an error in displacement of the board conveying segment due to a strain of the driving mechanism.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 2, 2015
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventor: Hidetoshi Sato
  • Publication number: 20150145925
    Abstract: The present disclosure describes a printhead circuit, devices, and methods of forming the printhead circuit. An example of a printhead circuit includes a substrate including a slot having a first, a second, and a third dimension in the substrate, circuitry on a first side and a second side of the slot, and a number of conductor traces routed across the slot along substantially a same geometrical plane as the circuitry on the first side and the second side of the slot.
    Type: Application
    Filed: May 31, 2012
    Publication date: May 28, 2015
    Inventors: Rio Rivas, Christopher Bakker, Edward Friesen, James R. Przybyla
  • Publication number: 20150146382
    Abstract: Disclosed herein are a package substrate, a method of manufacturing the same, and a power module package using the package substrate.
    Type: Application
    Filed: July 15, 2014
    Publication date: May 28, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Bum Sik Jang, Sung Min Song
  • Publication number: 20150143694
    Abstract: Disclosed herein is a carrier for manufacturing a printed circuit board, including: an insulating layer; a release layer buried in at least any one of top and bottom surfaces of the insulating layer and having a length shorter than that of the insulating layer; and a metal foil bonded to a surface of the insulating layer in which the release layer is buried and having a length longer than that of the release layer, thereby increasing reliability of a product in the manufacturing the substrate using the carrier.
    Type: Application
    Filed: September 15, 2014
    Publication date: May 28, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jae Ean Lee, Jung Hyun Cho, Kyung Hwan Ko, Yong Ho Baek
  • Publication number: 20150144381
    Abstract: Various embodiments provide a flexible printed circuit comprising a substrate layer portion and an electrically-conductive layer portion. The electrically-conductive layer portion may be superimposed over the substrate layer portion. The substrate layer portion may have an opening formed therein and part of the electrically-conductive layer portion may be positioned over the opening to form a partially detachable tab. The tab may be for use in initiating separation of one portion of the flexible printed circuit from another portion of the flexible printed circuit. Various embodiments provide a corresponding method of fabrication of a flexible printed circuit. Various embodiments provide a corresponding method of fabrication of a plurality of electronic devices.
    Type: Application
    Filed: June 29, 2012
    Publication date: May 28, 2015
    Inventors: Siang Sin Foo, Choong Meng How
  • Patent number: 9038266
    Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a first conductive circuit formed on the first interlayer resin insulation layer, a second interlayer resin insulation layer formed on the first interlayer resin insulation layer and the first conductive circuit and having an opening portion exposing a portion of the first conductive circuit, a second conductive circuit formed on the second interlayer resin insulation layer, a via conductor formed in the opening portion of the second interlayer resin insulation layer and connecting the first conductive circuit and the second conductive circuit, and a coating layer having a metal layer and a coating film and formed between the first conductive circuit and the second interlayer resin insulation layer. The metal layer is formed on the surface of the first conductive circuit and the coating film is formed on the metal layer.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: May 26, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Sho Akai, Tatsuya Imai, Iku Tokihisa
  • Publication number: 20150136475
    Abstract: A housing of an active medical device includes a metal wall having at least one feedthrough for an electrical connection through the wall. In the area of the feedthrough, the housing wall includes a contour groove extending through the thickness of wall, defining a metal islet electrically and physically isolated from the rest of the wall. The housing wall further includes an electrically insulating outer layer on the outer side of the wall extending over a region in alignment with the groove and beyond either side of the groove. The insulating outer layer includes a recess formed in alignment with the islet. The wall further includes an electrically conductive outer layer formed outside of the insulating layer and extending over the region in alignment with the groove and beyond either side of the groove. The islet is mechanically supported by the insulating and conductive outer layers.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 21, 2015
    Inventor: Bertrand Boutaud
  • Publication number: 20150136169
    Abstract: The invention relates to hair styling apparatus. A hair styling apparatus comprises a first and a second arm each comprising a heatable plate and arm member. The first and second arms are moveable between a closed position in which the heatable plate of the first arm is adjacent the heatable plate of the second arm and an open position in which the heatable plates of each arm are spaced apart. The heatable plate of at least one of the arms is coupled to a respective arm member about a pivot arranged to allow the heatable plate to move relative to the respective arm member about an axis transverse to the length of said respective arm member such that the plate pivots.
    Type: Application
    Filed: April 30, 2013
    Publication date: May 21, 2015
    Inventors: Timothy David Moore, Mark Andrew Gagiano
  • Publication number: 20150136459
    Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 21, 2015
    Applicant: IBIDEN Co., Ltd.
    Inventors: Masatoshi KUNIEDA, Makoto Terui, Ryoujiro Tominaga, Takashi Kariya
  • Publication number: 20150142090
    Abstract: An assembly for a medical lead includes an elongated lead body, and a conductive element located at a distal portion of the lead body. The conductive element substantial!)? encircles a longitudinal axis of the lead body. The assembly further includes a plurality of insulated conductors extending within the lead body, each of the insulated conductors being in electrical contact with the conductive element and extending to a proximal end of the lead body. Each of the insulated conductors contacts a different circumferential portion of the conductive element. The conductive element is configured to facilitate mechanical and electrical separation of different circumferential portions of the conductive element to form two or more electrode segments for the medical lead from the conductive element.
    Type: Application
    Filed: February 14, 2013
    Publication date: May 21, 2015
    Inventors: Victor Duijsens, Paulus C. van Venrooij
  • Publication number: 20150138137
    Abstract: A capacitive touch sensitive device includes a matrix of pads patterned in a first electrically conductive material on a substrate. Horizontally adjacent pads within each even row of the matrix are electrically coupled to one another via channels to form a plurality of horizontally arranged electrodes. Insulators are positioned over respective channels. Conductive links are formed over respective insulators and are configured to electrically couple vertically adjacent pads between odd rows of the matrix to form a plurality of vertically arranged electrodes. The dimensions of the channels and the conductive links are configured such that an RC time-constant (RCtc) of each of the vertically arranged electrodes substantially matches an RCtc of each of the horizontally arranged electrodes.
    Type: Application
    Filed: April 17, 2013
    Publication date: May 21, 2015
    Inventors: Kyu-Tak Son, Joel C. Kent
  • Patent number: 9032615
    Abstract: A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 19, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edward O. Travis, Douglas M. Reber, Mehul D. Shroff
  • Publication number: 20150128412
    Abstract: Certain processes for manufacturing an electrochemical sensor module include etching a Silicon wafer to form precursor sensor bodies, disposing sensor fibers along rows of the precursor sensor bodies, securing a rigid layer over the sensor fibers, dividing the wafer, rigid layer, and sensor fibers into individual precursor sensor bodies, and joining each precursor sensor body to a component body to form sensor modules.
    Type: Application
    Filed: May 18, 2012
    Publication date: May 14, 2015
    Applicant: PEPEX BIOMEDICAL, INC.
    Inventor: James L. Say
  • Patent number: 9027238
    Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 12, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Patent number: 9030199
    Abstract: An apparatus of a magnetoresistance sensor consisting of a substrate, a conductive unit on the substrate, and a magnetoresistance structure on the conductive unit is provided. The conductive unit includes a first surface and a second surface opposite to each other, and the first surface faces the substrate. The magnetoresistance structure is formed on the second surface of the conductive unit and is electrically connected to the conductive unit. The magnetoresistance sensor has high performance and reliability. A magnetoresistance sensor fabricating method based on this apparatus is also provided.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 12, 2015
    Assignee: Voltafield Technology Corporation
    Inventors: Fu-Tai Liou, Chien-Min Lee
  • Publication number: 20150124182
    Abstract: A display device with a touch panel is disclosed. The display device with the touch panel includes: a sensor having a substrate, a sensing electrode layer and a protective layer with a plurality of protrusions, wherein the sensing electrode layer is configured between the substrate and the protective layer; and a display module disposed under the sensor, wherein the sensor is connected to the display module with a glue, and the glue is configured along a periphery of the sensor.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 7, 2015
    Inventors: Ming-Liang Chen, Chih-Wei Chen, Ching-Feng Tsai
  • Publication number: 20150124181
    Abstract: A touch display device is provided. The touch display device comprises a display panel and a touch panel disposed on the display panel. The touch panel comprises a touch substrate and a sensing electrode layer. The touch substrate has a first surface, a second surface and a third surface. The first surface is opposite to the third surface and away from the display panel. The second surface is connected to the first surface and the third surface, and has a stress fracture area adjacent to the first surface. The sensing electrode layer is disposed on the third surface.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 7, 2015
    Inventors: Mao-Hsing Lin, Wei-Wu Pan