Manufacturing Circuit On Or In Base Patents (Class 29/846)
  • Patent number: 9021691
    Abstract: A method for introducing electrical insulations in a printed circuit board includes selectively introducing groove-shaped recesses between different regions of an electrically conductive layer on a substrate along a machining path using a thermal energy input such that end portions of each of the recesses or different ones of the recesses are joined to one another. The end portions are introduced parallel to one another without overlap such that a strip-shaped region of the conductive layer is initially retained between the end portions so as to insulate the different regions.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: May 5, 2015
    Assignee: LPKF Laser & Electronics AG
    Inventor: Jan van Aalst
  • Patent number: 9021692
    Abstract: A printed wiring board includes a resin insulation layer having a first surface and a second surface on an opposite side of the first surface, the resin insulation layer having an opening for a first via conductor, a pad formed on the first surface of the resin insulation layer and provided to mount an electronic component, a first conductive circuit formed on the second surface of the resin insulation layer, and a first via conductor formed in the opening and connecting the pad and the first conductive circuit. The pad has an embedded portion embedded in the resin insulation layer and a protruding portion protruding from the resin insulation layer, and the embedded portion has an external shape which is greater than an external shape the protruding portion.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: May 5, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Satoru Kawai, Kenji Sakai, Liyi Chen
  • Patent number: 9021669
    Abstract: Provided is a method for manufacturing a surface acoustic wave apparatus that can reduce degradation of electric characteristics and also reduce the number of manufacturing processes. The method for manufacturing a surface acoustic wave apparatus includes the steps of: forming an IDT electrode on an upper surface of a piezoelectric substrate, forming a frame member surrounding a formation area in which the IDT electrode is formed on the piezoelectric substrate, and mounting a film-shaped lid member on the upper surface of the frame member so as to be joined to the frame member so that a protective cover, used for covering the formation area and for providing a tightly-closed space between it and the formation area, is formed.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: May 5, 2015
    Assignee: KYOCERA Corporation
    Inventor: Toru Fukano
  • Publication number: 20150116059
    Abstract: A method and device for a compact microstrip bandpass filter that includes an input terminal, an output terminal, a plurality of quarter-wavelength resonators, a resonant disk, a plurality of layers, and a microstrip line which connects the resonant disk to a joint point of the quarter-wavelength resonators. A method of forming two signal paths in a compact microstrip bandpass filter includes forming a first signal path between an input terminal and an output terminal of the filter with a plurality of quarter-wavelength resonators with a resonant disk and a microstrip line which connects the resonant disk to a joint point of the quarter-wavelength resonators. The method includes forming a second signal path of the quarter-wavelength resonators, the filter includes a plurality of layers.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Zhejiang University
    Inventors: Faxin Yu, Qin Zheng, Zhiyu Wang
  • Publication number: 20150116242
    Abstract: Disclosed herein is a touch sensor. The touch sensor includes: a window substrate; a base substrate having one surface formed so as to be bonded to the window substrate and the other surface having a first electrode pattern formed thereon; a bezel formed along an edge of the base substrate; an insulating layer applying the electrode pattern while filling between the bezel and the bezel; and a second electrode pattern formed on the insulating layer.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 30, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Beom Seok OH, Tae Kyung Lee, Ho Joo Lee
  • Publication number: 20150116947
    Abstract: A laminate substrate may include a slug positioned within a cavity of a laminate core. The laminate substrate may have routing layers on either side of the laminate core, at least one of which is coplanar with an outer side of the slug. A capping layer may then be applied to the laminate substrate which is directly coupled with the slug and the routing layer. In embodiments, a dielectric layer may be coupled with the capping layer, and an additional routing layer may be coupled with the dielectric layer. Therefore, the routing layer may be an “inner” routing layer that is coplanar with, and coupled with, the slug.
    Type: Application
    Filed: October 24, 2013
    Publication date: April 30, 2015
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Thomas R. Landon, Jr., Paul D. Bantz, Tarak A. Railkar
  • Patent number: 9015936
    Abstract: A method for manufacturing an IC substrate includes following steps: providing a roll of double-sided flexible copper clad laminate; converting the roll of double sided flexible copper clad laminate into a roll of double sided flexible wiring board in a roll to roll manner; cutting the roll of double-sided flexible wiring board into a plurality of separate sheets of double sided flexible wiring board; forming first and second rigid insulating layers on the first and second wiring layers of each sheet of double sided flexible wiring board; forming third and fourth wiring layers on the first and second rigid insulating layers, and electrically connecting the first and third wiring layers, and electrically connecting the fourth and second wiring layers, thereby obtaining a sheet of substrate having a plurality of IC substrate units; and cutting the sheet of substrate into separate IC substrate units.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 28, 2015
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 9015914
    Abstract: A method for manufacturing an electronic component includes a first step of preparing a piezoelectric body with a flat surface, a second step of implanting ions into the piezoelectric body such that an ion-implanted layer is formed in the piezoelectric body, a third step of forming sacrificial layers on the flat surface of the piezoelectric body, a fourth step of forming an insulating body over the flat surface of the piezoelectric body and the sacrificial layers to form a piezoelectric structure, a fifth step of dividing the piezoelectric body at the ion-implanted layer to form a piezoelectric laminar structure in which a piezoelectric film separated from the piezoelectric body is bonded to the insulating body, a sixth step of forming electrodes on portions of a division surface of the piezoelectric film, and a seventh step of removing the sacrificial layers from the piezoelectric laminar structure.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: April 28, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Taro Nishino, Takashi Iwamoto
  • Publication number: 20150107884
    Abstract: The object of the present invention is to provide a multi-layer wiring board which is easy to adjust the characteristic impedance and is able to adapt to the narrow-pitch tendency of terminals, and a process for manufacturing the same.
    Type: Application
    Filed: February 28, 2013
    Publication date: April 23, 2015
    Applicant: KABUSHIKI KAISHA NIHON MICRONICS
    Inventors: Tatsuo Inoue, Takayasu Sugai, Toshiyuki Kudo, Toshinori Omori
  • Publication number: 20150107882
    Abstract: Various embodiments relate to a circuit board, including a base and a heat-conducting layer. The base has a first region and a second region on one side thereof facing the heat-conducting layer, the first region is recessed with respect to the second region, a first insulating layer is accommodated in the first region, a second insulating layer is formed on the second region, and the first insulating layer and the second insulating layer have different thermal conductivities. In addition, various embodiments further relate to an electronic module and an illuminating device including such circuit board. Various embodiments also relate to a method for manufacturing such circuit board.
    Type: Application
    Filed: June 14, 2013
    Publication date: April 23, 2015
    Inventors: Jianghui Yang, Chuanpeng Zhong, Hao Li, Xiaomian Chen
  • Publication number: 20150109251
    Abstract: A method of fabricating a capacitance touch panel module includes forming a plurality of first conductive patterns on a substrate comprising a touching area and a peripheral area along a first orientation, a plurality of second conductive patterns along a second orientation, and a plurality of connecting portions in the touching area; forming a plurality of insulated protrusions, in which each insulated protrusion covering one connecting portion, and forming an insulated frame on the peripheral area; and forming a bridging member on each insulated protrusion.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 23, 2015
    Inventors: KAI MENG, LIEN-HSIN LEE
  • Publication number: 20150109540
    Abstract: An in-cell touch panel includes a transparent substrate having a first surface, a plurality of drive-end traces and a plurality of receive-end traces disposed on the first surface of the transparent substrate, and a plurality of color photoresists. The drive-end traces and the receive-end traces are utilized as a black matrix for defining a plurality of pixel regions. The color photoresists are disposed on the first surface of the transparent substrate and disposed in the pixel regions respectively.
    Type: Application
    Filed: December 30, 2013
    Publication date: April 23, 2015
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chih-Wei CHANG, Kun-Chi CHIU, Shu-Wen CHANG, Chao-Wei WEI, Chun-Chung WU
  • Publication number: 20150107878
    Abstract: Electrically conductive films and methods for making them. The films include at least two patterns, the first of which, alone, would be visible, but with the addition of one or more other patterns, becomes invisible to the unaided human eye. These films are useful in applications where invisible patterning is desirable, such as, for example, devices employing touch screens.
    Type: Application
    Filed: September 30, 2014
    Publication date: April 23, 2015
    Inventors: Andrew T. Fried, Robert S. Loushin, Robert J. Monson
  • Patent number: 9009958
    Abstract: A mountable device includes a bio-compatible structure embedded in a polymer that defines at least one mounting surface. The bio-compatible structure includes an electronic component having electrical contacts, sensor electrodes, and electrical interconnects between the sensor electrodes and the electrical contacts. The bio-compatible structure is fabricated such that it is fully encapsulated by a bio-compatible material, except for the sensor electrodes. In the fabrication, the electronic component is positioned on a first layer of bio-compatible material and a second layer of bio-compatible material is formed over the first layer of bio-compatible material and the electronic component. The electrical contacts are exposed by removing a portion of the second layer, a conductive pattern is formed to define the sensor electrodes and electrical interconnects, and a third layer of bio-compatible material is formed over the conductive pattern.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventor: James Etzkorn
  • Patent number: 9009954
    Abstract: A method for manufacturing a Z-directed component for insertion into a mounting hole in a printed circuit board according to one example embodiment includes forming the Z-directed component in a cavity formed by a constraining material that defines the outer shape of the Z-directed component. The constraining material is dissipated to release the Z-directed component from the constraining material and the Z-directed component is fired.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: April 21, 2015
    Assignee: Lexmark International, Inc.
    Inventors: Keith Bryan Hardin, Paul Kevin Hall, Zachary Charles Nathan Kratzer, Qing Zhang
  • Patent number: 9003654
    Abstract: A method for metalizing at least one blind via formed in at least one substrate, including: a) arranging at least one solid portion of electrically conductive material in the blind via, b) performing a thermal treatment of the solid portion of electrically conductive material, making it melt in the blind via, cooling the electrically conductive material, solidifying it in the blind via, and wherein, before carrying out step a), at least part of the walls of the blind via is covered with a material able to prevent wetting of said part of the walls of the blind via by the melted electrically conductive material obtained during the performance of step b), the solidified electrically conductive material obtained after carrying out step c) being able not to be secured to said non-wetting part of the walls of the blind via.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: April 14, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Fabrice Jacquet, Sebastien Bolis, Damien Saint-Patrice
  • Patent number: 9006580
    Abstract: Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: April 14, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shinnosuke Maeda, Hajime Saiki, Satoshi Hirano
  • Patent number: 9003651
    Abstract: Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Mirzafer Abatchev, David Wells, Baosuo Zhou, Krupakar Murali Subramanian
  • Patent number: 9003652
    Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: April 14, 2015
    Assignee: Dell Products L.P.
    Inventors: Joel R. Goergen, Greg Hunt, Peter Tomaszewski, Joseph Pankow, Michael Laudon
  • Publication number: 20150097801
    Abstract: In one embodiment, a touch sensor includes a drive electrode and a sense electrode. The sense electrode is separated from the drive electrode by a gap having a width, and the width of the gap is substantially uniform throughout the entire extent of the gap.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Inventors: Matthew TREND, Carl Carley
  • Publication number: 20150096172
    Abstract: A system and method for balancing the capacitive charge on touch sensor electrodes so that every two adjacent routes have the same capacitance as any other adjacent two routes, wherein routing electrodes are spaced further and further apart, or graduated, as they get longer, to thereby balance the capacitance on the touch sensor electrodes without having to add or subtract an offset from each touch sensor electrode.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 9, 2015
    Applicant: CIRQUE CORPORATION
    Inventors: Jared G. Bytheway, Jon Alan Bertrand
  • Publication number: 20150096788
    Abstract: A method for fabrication of a circuit board using the disclosed embodiments relies on a CAD model of a multilayer circuit board with conductive elements defined by layer. A first granular conductive material layer is introduced into a mold. A fusion process element traverses across the mold to fuse selected portions of the first granular conductive material layer forming first layer conductive elements. An additional granular conductive material layer is introduced into the mold over the fused selected portions of the first layer and unfused portions of the first layer. The fusion process element is then traversed across the mold to fuse selected portions of the additional granular conductive material layer forming an additional layer of conductive elements. Unfused granular conductive material is then purged from the fused first conductive elements and additional conductive layer elements.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: The Boeing Company
    Inventor: Donald F. Wilkins
  • Publication number: 20150096797
    Abstract: Disclosed herein are a package board and a method of manufacturing the same. The package board includes: an insulating layer; and a ground layer formed in the insulating layer, wherein one side of the ground layer is formed so that a plurality of pattern parts having a plurality of diameters are spaced apart from each other and the other side thereof is continuously formed.
    Type: Application
    Filed: April 8, 2014
    Publication date: April 9, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Heung Ku Kim
  • Publication number: 20150099959
    Abstract: An electrode array (10) is configured for implantation into a subject. The electrode array (10) includes an organic substrate material (12) configured to be implanted into an in vivo environment and to optionally dissolve after implantation into the in vivo environment and be absorbed by the in vivo environment, and an electrode (14) mounted to the organic substrate material (12) and configured to acquire signals generated by the in vivo environment. The electrode array (10) includes a connection pad (20) mounted to the organic substrate (12), and a conductive trace (16) formed between the electrode (14) and the connection pad (2). The conductive trace (16) includes a conductive ink that is MRI-compatible.
    Type: Application
    Filed: April 26, 2013
    Publication date: April 9, 2015
    Inventors: Giorgio Bonmassar, Alexandra Golby
  • Patent number: 8997320
    Abstract: Provided is a method for manufacturing an acoustic wave device that has an excellent temperature coefficient of frequency (TCF) and high accuracy of IDT pattern forming and is capable of resisting high temperature processing of 200 degrees or more. The method for manufacturing an acoustic wave device according to the present invention includes forming an IDT (2) on a principal surface (1a) of a piezoelectric substrate (1), and forming a film by thermal spraying a material (3) having a smaller linear thermal expansion coefficient than the piezoelectric substrate onto an opposite principal surface (1b) of the piezoelectric substrate (1) where the IDT (2) is formed.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 7, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshiyuki Fuyutsume, Taro Nishino, Hisashi Yamazaki, Noboru Tamura, Nakaba Ichikawa, Masaki Aruga
  • Patent number: 8997330
    Abstract: An implantable sensor is provide which can be used for determining a concentration of at least one analyte in a medium, in particular a body tissue and/or a body fluid. The implantable sensor has a layered construction with at least one insulating carrier substrate and at least two electrodes which are arranged in at least two different layer planes of the implantable sensor and are electrically isolated from one another by the at least one insulating carrier substrate. The electrodes have electrode areas which face the medium when the sensor has been implanted, and are in contact with the medium over a large area and substantially uniformly, directly or via a generally analyte-permeable membrane layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 7, 2015
    Assignee: Roche Diagnostics Operations, Inc.
    Inventors: Holger Kotzan, Gregor Bainczyk
  • Patent number: 9000303
    Abstract: The invention provides a method for preparing a pattern for an electric circuit comprising the steps of: (a) providing a substrate; (b) providing a pattern of an inhibiting material for an electrical circuit onto said substrate by i) applying a layer of the inhibiting material onto said substrate and mechanically removing locally the layer of the inhibiting material to obtain said pattern; or ii) applying a layer of the inhibiting material onto said substrate, wherein said layer has pre-determined pattern which incompletely covers said substrate; (c) establishing a distribution of particles of a first metal or alloy thereof on the layer of the inhibiting material and the pattern as obtained in step.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 7, 2015
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Roland Anthony Tacken, Renatus Marius De Zwart, Erwin Rinaldo Meinders, Maria Peter
  • Patent number: 8997344
    Abstract: A method for manufacturing an interposer including forming a first insulating layer comprising an inorganic material on a supporting substrate, forming a first wire in the first insulating layer, forming a second insulating layer on a first side of the first insulating layer, forming a second wire with a longer wire length and a greater thickness than the first wire on the second insulating layer, and removing the supporting substrate.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: April 7, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Hajime Sakamoto, Shuichi Kawano, Daiki Komatsu, Hiroshi Segawa
  • Patent number: 8997340
    Abstract: A method of manufacturing an insulating sheet, the method including providing a reinforcement material having a thermoplastic resin layer stacked thereon; stacking the thermoplastic resin layer stacked on the reinforcement material over a core substrate; and hot pressing the reinforcement material and the thermoplastic resin layer onto the core substrate.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Keungjin Sohn, Nobuyuki Ikeguchi, Joung-Gul Ryu, Ho-Sik Park, Sang-Youp Lee, Joon-Sik Shin, Jung-Hwan Park
  • Patent number: 8997331
    Abstract: A matrix analyzer for determining the size and location of a conductive item placed thereon. The matrix analyzer includes plural row conductors and column conductors with a corresponding grid of conductive areas exposed on the surface of the matrix analyzer. When a conductive item, such as an ink droplet, is jetted onto the matrix analyzer, the intersection of various row conductors and column conductors exhibit a low resistance. The rows and columns of the matrix analyzer can be sequentially accessed to find those intersections where the low resistance exists. From such data, the size and location of the ink droplets can be determined.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: April 7, 2015
    Assignee: Lexmark International, Inc.
    Inventor: David Thomas Shadwick
  • Patent number: 8997333
    Abstract: A method of manufacturing an inductor includes a lamination step, a division step, a firing step, and a plating step. In the lamination step, a laminate including an insulator, a coil body, and external electrodes is formed. That is, in the lamination step, insulating layers having wide filling conductors, insulating layers having narrow filling conductors, and conductor patterns having external electrode patterns are laminated. As a result, the conductor patterns form the coil body, and the wide filling conductors, the narrow filling conductors, and the external electrode patterns form the external electrodes. The narrow filling conductors have a width that is less than the widths of the wide filling conductors and the external electrode patterns, and recesses and projections are provided in the external electrodes.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kazuhiko Yamano
  • Patent number: 8997341
    Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.
    Type: Grant
    Filed: September 6, 2010
    Date of Patent: April 7, 2015
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Yoshinori Ejiri, Kiyoshi Hasegawa, Takehisa Sakurai, Yoshiaki Tsubomatsu
  • Publication number: 20150091152
    Abstract: Disclosed herein are an external connection terminal, a semiconductor package having the external connection terminal, and a method of manufacturing the same. The external connection terminal includes an internal insulating material, an external insulating material formed to enclose the internal insulating material, and metal lines formed between the internal insulating material and the external insulating material.
    Type: Application
    Filed: September 19, 2014
    Publication date: April 2, 2015
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eun Jung JO, Chang Seob HONG, Kyu Hwan OH, Kang Hyun LEE
  • Publication number: 20150092371
    Abstract: According to various embodiments, a contact pad structure may be provided, the contact pad structure may include: a dielectric layer structure; at least one contact pad being in physical contact with the dielectric layer structure; the at least one contact pad including a metal structure and a liner structure, wherein the liner structure is disposed between the metal structure of the at least one contact pad and the dielectric layer structure, and wherein a surface of the at least one contact pad is at least partially free from the liner structure, and a contact structure including an electrically conductive material; the contact structure completely covering at least the surface being at least partially free from the liner structure of the at least one contact pad, wherein the liner structure and the contact structure form a diffusion barrier for a material of the metal structure of the at least one contact pad.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Infineon Technologies AG
    Inventor: Dirk Meinhold
  • Patent number: 8991042
    Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Manabu Sakamoto, Tetsuya Shirasu, Naoki Idani
  • Patent number: 8991039
    Abstract: A process for manufacturing a multilayer article, the article comprising two crosslinked semiconductive layers separated by and bonded to an insulation layer, the semiconductive layers formed from a peroxide-crosslinkable olefin elastomer and the insulation layer comprising composition comprising a silane-grafted olefinic elastomer, the process comprises the steps of: (A) injecting the silane-grafted olefinic elastomer between the two crosslinked semiconductive layers so as to have direct contact with each semiconductive layer, and (B) crosslinking the silane-grafted olefinic elastomer in the absence of a peroxide catalyst.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: March 31, 2015
    Assignee: Dow Global Technologies LLC
    Inventors: Mohamed Esseghir, Jeffrey M. Cogen, Saurav S. Sengupta
  • Publication number: 20150085504
    Abstract: In one aspect, a circuit board includes a base board and a layer of an elastic material comprising a first surface and a second surface. The layer of elastic material is adhered to the base board via the first surface. The circuit board further includes an electrical trace disposed on the second surface of the layer of elastic material. At least a portion of the layer of elastic material stretches or shrinks when the base board expands or contracts. A method of manufacturing a circuit includes obtaining an aluminum board, obtaining a layer of an elastic material, and applying a layer of adhering material to a surface of the aluminum board. The method further includes disposing the layer of the elastic material onto the layer of adhering material, and adhering the layer of the elastic material onto the aluminum board via the layer of adhering material.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Inventor: Ellis W. Patrick
  • Publication number: 20150083479
    Abstract: A method of fabricating a capacitance touch panel module includes forming a plurality of first conductive patterns on a substrate comprising a touching area and a peripheral area along a first orientation, a plurality of second conductive patterns along a second orientation, and a plurality of connecting portions in the touching area; forming a plurality of insulated protrusions, in which each insulated protrusion covering one connecting portion, and forming an insulated frame on the peripheral area; and forming a bridging member on each insulated protrusion.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventors: KAI MENG, LIEN-HSIN LEE
  • Publication number: 20150082628
    Abstract: A method uses time-domain reflectometry to measure a signal reflection delay in a conductive trace formed on a specific passive printed circuit board, and uses the measured signal reflection delay as an index into a table storing a predetermined association between signal reflection delay and passive printed circuit board manufacturing information, wherein the table includes a plurality of predetermined signal reflection delay values, and wherein each of the predetermined signal reflection delay values is associated with unique passive printed circuit board manufacturing information. During manufacturing of the passive printed circuit board, a hole is drilled through the passive printed circuit board so that the hole intersects with the conductive trace and divides the conductive trace into a proximal segment extending from the connector to the hole and a distal segment that is electrically isolated from the proximal segment by the hole.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jordan HP Chin, Timothy M. Wiwel
  • Publication number: 20150085457
    Abstract: An electrical connector for electrically connecting a first electronic element having protruding conductive portions in the bottom thereof to a second electronic element, includes an insulating body located below the first and above the second electronic element, a conductor, a solder pad disposed on the lower surface of the insulating body, and a conducting line disposed in the insulating body and conducting the conductor and the solder pad. Upper surface of the insulating body has accommodation holes. Aperture of the accommodation hole is greater than outer diameter of the conductive portion. Wall and bottom of the accommodation holes form the conductor. The accommodation hole has low-melting point liquid metal conductor. When the conductive portion enters the accommodation hole, the liquid metal adheres to the conductive portion, and forms a conductive path between the conductive portion and the conductor. A manufacturing method of the electrical connector.
    Type: Application
    Filed: December 2, 2013
    Publication date: March 26, 2015
    Applicant: LOTES CO., LTD
    Inventor: Ted Ju
  • Publication number: 20150087945
    Abstract: A method of making a sensor includes depositing a layer of hydrogel over a substrate, the hydrogel configured to change thickness or volume in response to a selected condition and including a plurality of magnetic particles disposed in the hydrogel so that a magnetic property of the hydrogel changes with changes of thickness or volume of the hydrogel. The hydrogel is sacrificed in selected region(s) of the layer so that the hydrogel outside the selected region(s) forms a plurality of spaced-apart islands of the hydrogel. The islands of the hydrogel are enclosed in an enclosure at least partly permeable to a selected fluid. A sensor for detecting a condition includes the substrate, islands, and a device coil arranged with respect to the hydrogel so that changes in the magnetic property modulate an electrical property of the sensor. A system includes the substrate, islands, and a magnetic-field detector.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventors: Babak Ziaie, Ronald A. Siegel
  • Patent number: 8984748
    Abstract: A socket assembly that forms a solderless electrical interconnection between terminals on a singulated integrated circuit device and another circuit member. The socket housing has an opening adapted to receive the singulated integrated circuit device. The compliant printed circuit is positioned relative to the socket housing to electrically couple with the terminals on a singulated integrated circuit device located in the opening. The compliant printed circuit includes a dielectric base layer printed onto a surface of a fixture, while leaving cavities in the surface of the fixture exposed. A plurality of contact members are formed in the plurality of cavities in the fixture and coupled to the dielectric base layer. The contact members are exposed wherein the compliant printed circuit is removed from the fixture. At least one dielectric layer with recesses corresponding to a target circuit geometry is printed on the dielectric base layer.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: March 24, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8984747
    Abstract: Methods for manufacturing a fabric-type circuit board, including: forming a metal plating layer on a base substrate, forming a circuit pattern by etching the metal plating layer, bonding a carrier film on the circuit pattern, and bonding an adhesive film directly below the circuit pattern after removing the base substrate; or bonding an adhesive film to a metal thin film, forming a circuit pattern by etching the metal thin film, and bonding a carrier film on the circuit pattern. In either case, the circuit pattern is transferred to a fabric by bonding the adhesive film to the fabric.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 24, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Bae sun Kim, Yong Ki Son, Ji Eun Kim, Sung yong Shin
  • Patent number: 8984746
    Abstract: A method for the manufacture of a circuit board containing a component and circuit board containing a component. The invention is based on first manufacturing an intermediate product, which contains the insulator layer of the circuit board and the components, which are set in place inside the insulator layer in such a way that the contact elements of the components face the surface of the intermediate product. After this, the intermediate product is transferred to the circuit-board manufacturing line, on which a suitable number of conductor-pattern layers and, if necessary, insulator layers are manufactured on one or both sides of the intermediate product, in such a way that, when manufacturing the first conductor-pattern layer, the conductor material forms an electrical contact with the contact elements of the components. Alternatively, stages can also be performed on a single manufacturing line.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: March 24, 2015
    Assignee: GE Embedded Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm, Antti Lihola
  • Publication number: 20150077733
    Abstract: Some embodiments of the present disclosure relate to a method of overlay control which utilizes a deformable electrostatic chuck. The method comprises exposing a substrate to radiation which is reflected off of a reticle. The reticle is mounted to a deformable electrostatic chuck by a plurality of raised contacts, where each raised contact is configured to independently vary in height from a surface of the deformable electrostatic chuck. After exposure of the substrate to radiation which is reflected off of the reticle, a displacement between a first alignment shape formed on a first layer disposed on a surface of the substrate and a second alignment shape formed by the exposure is measured. The height of one or more of the plurality of raised contact is changed based upon the displacement to alter a surface topology of the reticle, which negates some effects of clamping topology. Other embodiments are also disclosed.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 19, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ching Huang, Chia-Hao Hsu, Chia-Chen Chen
  • Publication number: 20150076240
    Abstract: A method for producing a smartcard body for receiving a semiconductor chip includes forming at least one lead frame of the smartcard body in a carrier material connected by at least one material strip. Surrounding the at least one lead frame is an electrically insulating casing having a cavity for receiving the semiconductor chip. Either before or during the forming of the casing, the at least one material strip is separated or severed, so that the material strip is separated into a first strip part connected with the carrier material and a second strip part connected with the lead frame forming an interspace there between. When forming the casing at least a portion of the first strip part as well as at least a portion of the second strip part of the at least one material strip is comprised by the casing.
    Type: Application
    Filed: October 23, 2014
    Publication date: March 19, 2015
    Inventors: Eric Daniel, Frank Eberhardt, Sébastien Kalck, Frédéric Morgenthaler, Rainer Mutz, Timo Schabinger
  • Publication number: 20150076237
    Abstract: A temporary carrier of a removable memory card (2) is in the shape of a flat card (1), where the removable memory card (2) forms an element to be released from the flat card body (1). The removable memory card (2) has at least five additional contacts (4) for temporary usage before the removable memory card is removed from the flat card (1) body. The additional contacts (4) take up a smaller surface as a contact field (5) of a standardized flat card (1). The removable memory card (2) is located within the flat card (1) in such a way that the position of additional contacts (4) corresponds to the position of a standardized flat card (1) contact field (5). The suitable sixth additional switch contact (8) can be used to switch secure elements. The temporary carrier is inserted into a standard burning device, which operates with it in the same way as it would with a common card with a contact field (5).
    Type: Application
    Filed: March 22, 2013
    Publication date: March 19, 2015
    Inventors: Miroslav Florek, Michal Masaryk, Pavel Travnicek
  • Patent number: 8978244
    Abstract: A method for manufacturing a printed circuit board with cavity includes following steps. First, a first substrate is provided. The first substrate includes a first electrically conductive layer defining an exposed portion and a laminating portion. Second, a second substrate is provided. The second substrate includes an unwanted portion corresponding to the exposed portion and a preserving portion. Third, a first annular bump surrounding the exposed portion is formed. Fourth, a second annular bump surrounding the unwanted portion is formed. Fifth, a first adhesive layer defining an opening is provided. Sixth, the first and second substrates are laminated to the first adhesive layer, the exposed portion and the unwanted portion are exposed in the opening, and the second annular bump is in contact with the first annular bump. Seventh, the unwanted portion is removed and a cavity is defined, the exposed portion is exposed in the cavity.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: March 17, 2015
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventors: Xue-Jun Cai, Zhi-Yong Li, Chao Liu
  • Publication number: 20150068523
    Abstract: A pressure sensitive device includes a ring having a central axis, first side and second side. The ring includes a dielectric portion parallel to the central axis and between the first and second sides. A flexible membrane is connected to a periphery of the ring on the first side, the flexible membrane including a conductive portion. A perforated membrane is connected to a periphery of the ring on the second side. The perforated membrane is spaced apart and electrically isolated from the flexible membrane by the ring below a threshold pressure differential across the pressure sensitive device. The perforated membrane includes an opening therethrough and a conductive portion facing and corresponding to the conductive portion of the flexible membrane such that a threshold pressure differential across the pressure sensitive device causes deflection between the conductive portions of the flexible membrane and the perforated membrane to change an electrical property.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: ARROW ELECTRONICS, INC.
    Inventors: NICHOLAS POWERS, Christian Curtis
  • Publication number: 20150068315
    Abstract: A pressure sensor includes a pressure sensing element and a top cap. The pressure sensing element includes a bonded wafer substrate having a buried sealed cavity. A wall of the buried sealed cavity forms a sensing diaphragm. One or more sense elements may be supported by the sensing diaphragm and one or more bond pads are supported by the upper side of the bonded wafer substrate. Each of the bond pads may be positioned adjacent to the sensing diaphragm and electrically connected to one or more of the sense elements. The top cap may be secured to the upper side of the bonded wafer substrate such that an aperture in the top cap facilitates passage of a media in a downward direction to the sensing diaphragm. The top cap may be configured to isolate the bond pads from the media.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: Honeywell International Inc.
    Inventors: RIchard A. Davis, Carl Stewart