Manufacturing Circuit On Or In Base Patents (Class 29/846)
  • Publication number: 20150073409
    Abstract: Electrode placement and connection systems are described which allow for the electrical connection and maintenance of one or more electrodes positioned on a substrate which is subjected to a variety of mechanical stresses. Electrodes may also be formed on flexible circuit assemblies integrated within or along the hood. The circuit assemblies may also provide structural support to the hood during delivery and/or deployment. Such a system may include an imaging hood having an aperture through which transparent fluid is flowed and one or more electrodes positioned along or about the hood. As the hood is configured between a low-profile and opened configuration, these electrodes may remain electrically coupled despite the mechanical stresses subjected to the electrodes and the connections thereto.
    Type: Application
    Filed: November 11, 2014
    Publication date: March 12, 2015
    Inventors: John Paul Watson, Edmund Tam, Vahid Saadat
  • Publication number: 20150068033
    Abstract: A packaging substrate includes a first dielectric layer, a first circuit layer, a first metal bump, and a built-up structure. The first metal bump and the first circuit layer are embedded in and exposed from two surfaces of the first dielectric layer. The end of the first metal bump is embedded in the first circuit layer and between the first circuit layer and the first dielectric layer. In addition, a conductive seedlayer is disposed between the first circuit layer and the first metal bump. The built-up structure is disposed on the first circuit layer and the first dielectric layer. The outmost layer of the built-up structure has a plurality of conductive pads. Compared to the prior art, the present invention can effectively improve the warpage problem of the conventional packaging substrate.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 12, 2015
    Inventors: Tzyy-Jang Tseng, Chung-W. Ho
  • Publication number: 20150068787
    Abstract: Provided herein is a conductive pattern making method and conductive pattern, the method including forming a groove such that its width in an inlet area is bigger than its width in an inner area; filling the groove with a conductive ink composition; and drying the conductive ink composition so that a solvent contained in the conductive ink composition inside the groove is volatilized to reduce the volume of the conductive ink composition.
    Type: Application
    Filed: September 8, 2014
    Publication date: March 12, 2015
    Inventors: Kwang-Choon Chung, Ji Hoon Yoo, Joonki Seong, Dae Sang Han, Nam-Boo Cho
  • Publication number: 20150068299
    Abstract: A gas flow sensing device, and related method of manufacturing, comprising a conductive layer encapsulated in dielectric film, suspended over a cavity to form a diaphragm. The conductive layer functions as both a heating a sensing element and is patterned to provide uniform heat distribution across the diaphragm. The device is designed to sense flow from any direction relative to the device and the design of the dielectric film and diaphragm reduces sensor drift during prolonged operation.
    Type: Application
    Filed: April 11, 2013
    Publication date: March 12, 2015
    Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Jianzhong Zhu, Hilary Bart-Smith, Zheng Chen
  • Publication number: 20150068032
    Abstract: A method of making a multi-layer micro-wire structure includes providing a substrate having a substrate edge and first and second layers formed over the substrate. One or more micro-channels are imprinted in each of the first and second layers and first and second micro-wires located in the imprinted micro-channels, the micro-wires forming at least a portion of an exposed connection pad in each layer. The second layer edge is farther from the substrate edge than the first layer edge for at least a portion of the second layer edge so that the first connection pads are exposed through the second layer.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 12, 2015
    Inventor: Ronald Steven Cok
  • Patent number: 8974094
    Abstract: A lamp includes a collar with internal and outer surfaces, where two or more connection pins extend from the internal surface of the collar. At least two connection pins have a head portion distal from the collar internal surface. The head portions include a slot. The lamp includes a light source with at least two external lead-in wires. The lead-in wires are located within respective slots and are mechanically coupled to respective surfaces of the slots in a press-fit manner which may be free of wrapping, winding, twisting, or soldering. A PCB disposed inside the lamp has two opposing surfaces and a rim between the two opposing surfaces. There are conductive surfaces disposed on at least one of the rim and one of the opposing surfaces at positions corresponding to connection pin slots. The PCB is located between connection pins with the conductive surfaces in electrical communication with the lead-in wires.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: March 10, 2015
    Assignee: General Electric Company
    Inventors: Tamás Vásárhelyi, József Fülöp, Tímea Seszták, Zsolt Bagoly, Jácint Gergely
  • Patent number: 8975531
    Abstract: Various embodiments include interconnect structures and methods of forming such structures. The interconnect structures can include a composite copper wire which includes at least two distinct copper sections. The uppermost copper section can have a thickness of approximately 1 micrometer or less, which inhibits surface roughening in that uppermost section, and helps to enhance cap adhesion with overlying layers.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Felix Anderson, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 8973257
    Abstract: Methods for building a neutron detector are disclosed, in which the neutron detector comprises at least two conductive cathode sheets lying parallel to one another and coated with neutron reactive material on at least one side thereof; dielectric material separating the cathode sheets and covering less than about 80% of their surface area; and a plurality of anode wires lying generally parallel to the cathode sheets and separated from them by the dielectric, with the distance between adjacent anode wires being no more than twenty times the distance between said cathode sheets. The cathode sheets may be flat or curved; they may be separate plates or they may be successive folds or windings of a single folded or spiral-shaped metal sheet.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: March 10, 2015
    Assignee: Material Innovations, Inc.
    Inventors: Andrew C. Stephan, Vincent D. Jardret
  • Patent number: 8973259
    Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: March 10, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Sotaro Ito, Michimasa Takahashi, Yukinobu Mikado
  • Patent number: 8973229
    Abstract: A method for manufacturing a composite piezoelectric substrate in which a piezoelectric substrate and a supporting substrate are prepared, ions are implanted in the piezoelectric substrate to form a defective layer at a predetermined depth in the piezoelectric substrate, impurities that are adhered to a surface of the piezoelectric substrate or a surface of the supporting substrate are removed to expose the constituent atoms thereof and to activate the surfaces, the supporting substrate is bonded to the piezoelectric substrate to form a bonded substrate body, the bonded substrate body is separated at the defective layer so that a separation layer between the surface of the piezoelectric substrate and the defective layer is separated from the piezoelectric substrate and bonded to the supporting substrate to form a composite piezoelectric substrate, and the surface of the separation layer of the composite piezoelectric substrate is smoothed.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 10, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hajime Kando, Yoshiharu Yoshii
  • Patent number: 8973258
    Abstract: A manufacturing method of substrate structure is provided. A base material having a core layer, a first patterned copper layer, a second patterned copper layer and at least one conductive via is provided. The first and second patterned copper layers are respectively located on a first surface and a second surface of the core layer. The conductive via passes through the core layer and connects the first and second patterned copper layers. A first and a second solder mask layers are respectively formed on the first and second surfaces. Portions of the first and second patterned copper layers are exposed by the first and second solder mask layers, respectively. A first gold layer is formed on the first and second patterned copper layers exposed by the first and second solder mask layers. A nickel layer and a second gold layer are successively formed on the first gold layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Ching-Sheng Chen
  • Patent number: 8973228
    Abstract: A vibration layer is formed by the AD method on a cavity plate before forming pressure chambers, a common electrode is formed on the vibration layer, and a piezoelectric layer is formed on the common electrode by the AD method. Subsequently, the pressure chambers are formed in the cavity plate by the etching. After that, individual electrodes are formed on the piezoelectric layer. Subsequently, the stack of the cavity plate, the vibration layer, the common electrode, the piezoelectric layer, and the individual electrodes is heated at about 850° C. to simultaneously perform the annealing of the piezoelectric layer and the sintering of the individual electrodes and the common electrode. Accordingly, the atoms of the cavity plate are suppressed from being diffused into the driving portions of the piezoelectric layer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: March 10, 2015
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroto Sugahara
  • Patent number: 8977078
    Abstract: An optical printed circuit board according to the embodiment includes an insulating layer; an optical wave guide buried in the insulating layer to transmit an optical signal; and an optical path converting part provided on at least one end of the optical wave guide to convert a transmission path of the optical signal defined by the optical wave guide such that the transmission path has a predetermined curvature.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: March 10, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyoun Jeong Lee
  • Patent number: 8973261
    Abstract: A manufacturing method of an object having a conductive line includes the following steps. A hardening layer and a conductive line layer are formed in an in-mold roller (IMR) material in sequence. The conductive line layer is formed on a non-conductive substrate by an IMR process. A carrier sheet is then separated to expose the hardening layer. A connecting piece is formed on the hardening layer. The connecting piece runs through the hardening layer by a connection process, and the connecting piece is electrically connected to the conductive line layer. Therefore, an object structure having the conductive line is formed.
    Type: Grant
    Filed: September 25, 2011
    Date of Patent: March 10, 2015
    Assignee: Getac Technology Corporation
    Inventor: Cheng-Hung Chiang
  • Publication number: 20150059172
    Abstract: A method for making a touch panel is provided. A number of first transparent conductive layers are formed on an insulative substrate. Each of the first transparent conductive layers is resistance anisotropy. A number of adhesive layers are formed on the insulative substrate with each to cover only part of one of the first transparent conductive layers. A carbon nanotube layer is formed on the number of adhesive layers. The carbon nanotube layer is patterned to obtain a number of second transparent conductive layers spaced from each other and with each corresponding to one first transparent conductive layer. A number of first electrodes, a first conductive trace, a number of second electrodes, and a second conductive trace are formed contemporaneously.
    Type: Application
    Filed: December 10, 2013
    Publication date: March 5, 2015
    Applicant: TIANJIN FUNAYUANCHUANG TECHNOLOGY CO.,LTD.
    Inventor: HO-CHIEN WU
  • Publication number: 20150062455
    Abstract: The present invention discloses a touch Screen panel and a method for manufacturing the same, and a display device. The method comprises: forming a pattern of a touch electrode layer on a substrate; forming a pattern of an insulating layer on the touch electrode layer; and then forming the patterns of a bridging layer and a peripheral wiring on the insulating layer by one patterning process. In the invention, the patterning of the bridging layer and the peripheral wiring is accomplished simultaneously in one patterning process, thereby the number of patterning times during the manufacture process can be reduced, the manufacture efficiency of the touch screen panel can be improved, and the production cost can be lowered.
    Type: Application
    Filed: December 17, 2013
    Publication date: March 5, 2015
    Inventors: Guangye Hao, Yunsik Im
  • Publication number: 20150060676
    Abstract: An x-ray detector assembly is disclosed that includes a mounting substrate having a plurality of electrical contacts, the mounting substrate comprising one of an integrated circuit and a circuit board. The x-ray detector assembly also includes a first electrode patterned on a first portion of a top surface of the mounting substrate, wherein the first electrode is electrically coupled to the plurality of electrical contacts. An organic photodiode layer is formed atop the first electrode and has a bottom surface electrically connected to the first electrode. A second electrode is coupled to a top surface of the organic photodiode layer and a scintillator is coupled to the second electrode.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: General Electric Company
    Inventors: Aaron Judy Couture, Marc Schaepkens, Abdelaziz Ikhlef
  • Publication number: 20150062507
    Abstract: A thin film transistor array panel includes a substrate. A data line is formed on the substrate. A color filter covers at least a portion of the data line. A shielding electrode is formed on the color filter and is disposed over the data line. A pixel electrode is formed on the color filter and is separated from the shielding electrode. The shielding electrode has a low reflection characteristic.
    Type: Application
    Filed: February 6, 2014
    Publication date: March 5, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: JE HYEONG PARK, SU WAN WOO, KYUNG SEOP KIM
  • Patent number: 8966750
    Abstract: A method of manufacturing a multilayered printed wiring board including forming a multilayered core substrate including insulation layers and one or more stacked via structures formed through the insulation layers, the stacked via structure including vias formed in the insulation layers, respectively, the insulation layers in the multilayered core substrate including at least three insulation layers and each of the insulation layers in the multilayered core substrate including a core material impregnated with a resin, and forming a build-up structure over the multilayered core substrate and including interlaminar insulation layers and conductor circuits, each of the interlaminar insulation layers including a resin material without a core material.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 3, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Tomoyuki Ikeda, Naoaki Fujii, Seiji Izawa
  • Patent number: 8969736
    Abstract: A cover insulating layer is formed on a base insulating layer. One of write wiring traces includes first to third lines, and the other write wiring trace includes fourth to sixth lines. The one and other write wiring traces constitute a signal line pair, the second and fifth lines are arranged on an upper surface of the cover insulating layer, and the third and sixth lines are arranged on an upper surface of the base insulating layer. At least parts of the second and fifth lines are respectively opposed to the sixth and third lines with the cover insulating layer sandwiched therebetween. The second and third lines are electrically connected to the first line, and the fifth and sixth lines are electrically connected to the fourth line. The fourth line is electrically connected to at least one of the fifth and sixth lines through a jumper wiring on a lower surface of the base insulating layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: March 3, 2015
    Assignee: Nitto Denko Corporation
    Inventor: Daisuke Yamauchi
  • Patent number: 8966748
    Abstract: The invention relates to a method for manufacturing an arrangement with a component on a carrier substrate, wherein the method encompasses the following steps: Manufacturing spacer elements on the rear side of a cover substrate, arranging a component on a cover surface of a carrier substrate, and arranging the spacer elements formed on the carrier substrate so as to situate the component in the at least one hollow space and close the latter. In addition, the invention relates to an arrangement, a method for manufacturing a semi-finished product for a component arrangement, as well as a semi-finished product for a component arrangement.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 3, 2015
    Assignee: MSG Lithoglas AG
    Inventors: Jürgen Leib, Simon Maus, Ulli Hansen
  • Patent number: 8966747
    Abstract: A method of encapsulating a panel of electronic components such as power converters reduces wasted printed circuit board area. The panel, which may include a plurality of components, may be cut into one or more individual pieces after encapsulation with the mold forming part of the finished product, e.g. providing heat sink fins or a surface mount solderable surface. Interconnection features provided along boundaries of individual circuits are exposed during the singulation process providing electrical connections to the components without wasting valuable PCB surface area. The molds may include various internal features such as registration features accurately locating the circuit board within the mold cavity, interlocking contours for structural integrity of the singulated module, contours to match component shapes and sizes enhancing heat removal from internal components and reducing the required volume of encapsulant, clearance channels providing safety agency spacing and setbacks for the interconnects.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: March 3, 2015
    Assignee: VLT, Inc.
    Inventors: Patrizio Vinciarelli, Michael B. Lafleur, Sean Timothy Fleming, Rudolph Mutter, Andrew T. D'Amico
  • Patent number: 8966746
    Abstract: A method of fabricating a cavity capacitor embedded in a printed circuit board including two conductive layers to be used as a power layer and a ground layer, respectively, and a first dielectric layer, placed between the two conductive layers, the method including: removing an upper conductive layer and the first dielectric layer excluding a lower conductive layer of the two conductive layers to allow a cavity to be formed between the two conductive layers, the lower conductive layer being supposed to be used as any one of electrodes of the cavity capacitor; stacking a dielectric material on the cavity to allow a second dielectric layer having a lower stepped portion than the first dielectric layer to be formed in the cavity; and stacking a conductive material on an upper part of the second dielectric layer and side parts of the cavity to allow the upper conductive layer to be used as the other electrode of the cavity capacitor.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Han Kim, Je-Gwang Yoo, Chang-Sup Ryu
  • Patent number: 8969730
    Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch
  • Patent number: 8970242
    Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: March 3, 2015
    Assignee: Rohm Co, Ltd.
    Inventors: Goro Nakatani, Masahiro Sakuragi, Koichi Niino
  • Patent number: 8966729
    Abstract: In sputter etching to improve the adhesion between upper electrodes and lead electrodes, the sputter etching of surfaces of the upper electrodes under an Ar gas flow at a flow rate of 60 sccm or more can reduce the residence time of Ar ions on the surfaces of the upper electrodes because of the Ar gas flow. This can prevent the charging of the upper electrodes due to the buildup of ionized Ar gas on the surfaces, reduce the influence of charging on piezoelectric elements, and provide a method for manufacturing a piezoelectric actuator that includes the piezoelectric elements each including a piezoelectric layer having small variations in hysteresis characteristics and deformation characteristics.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 3, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Hironobu Kazama, Takahiro Kamijo, Masato Shimada, Hiroyuki Kamei, Yuka Yonekura, Motoki Takabe
  • Patent number: 8966731
    Abstract: A method for manufacturing a switching element which has enough resistance to repeat switching operations and which can be miniaturized and have low power consumption, and a display device including the switching element are provided. The switching element includes a first electrode to which a constant potential is applied, a second electrode adjacent to the first electrode, and a third electrode over the first electrode with a spacer layer formed of a piezoelectric material interposed therebetween and provided across the second electrode such that there is a gap between the second electrode and the third electrode. A potential which is different from or approximately the same as a potential of the first electrode is applied to the third electrode to expand and contract the spacer layer, so that a contact state or a noncontact state between the second electrode and the third electrode can be selected.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Honda
  • Publication number: 20150053463
    Abstract: A rigid flex board module includes a rigid flex circuit board and a high-density interconnected circuit board. The rigid flex circuit board includes a flexible circuit board, a first rigid circuit board and a first adhesive layer. The flexible circuit board includes a bending portion and a jointing portion connected to the bending part. The rigid flex circuit board is disposed on the jointing portion to expose the bending portion. The first rigid circuit board electrically connects with the flexible circuit board. The first adhesive layer connects the first rigid circuit board and the jointing portion. The high-density interconnected circuit board is disposed in the first rigid circuit board and is electrically connected to the first rigid circuit board.
    Type: Application
    Filed: December 2, 2013
    Publication date: February 26, 2015
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: CHI-SHIANG CHEN, HSIU-CHING HU, KUN-WU LI, FANG-PING WU
  • Publication number: 20150053664
    Abstract: A method for providing an electrical connection for conductive ink includes direct writing a bus bar onto areas of a desired electrical connection of the conductive ink. The conductive ink is screen printed onto a dielectric film to create a conductive circuit. An aircraft heated floor panel includes at least one floor panel of an aircraft. The one floor panel includes a conductive circuit having a conductive ink including a bus bar directly written onto areas of a desired electrical connection of the conductive ink. The conductive ink is screen printed onto a dielectric film to create a conductive circuit.
    Type: Application
    Filed: February 27, 2014
    Publication date: February 26, 2015
    Applicant: Goodrich Corporation
    Inventor: Jin Hu
  • Publication number: 20150052747
    Abstract: A manufacturing method of touch substrate includes steps of: providing a substrate, a photosensitive film of Nano-Silver particles being formed on a surface of the substrate; performing an exposure process to the film of Nano-Silver particles of the surface of the substrate; performing a development process to the film of Nano-Silver particles of the surface of the substrate to form a nontransparent sensing electrode layer and a nontransparent electrode wiring layer in the form of a mesh on the surface of the substrate; and performing a high electrical conductivity treatment and a stabilization treatment to the nontransparent sensing electrode layer on the surface of the substrate. So, the nontransparent sensing electrode layer and nontransparent electrode wiring layer can be formed on the surface of the substrate at the same time. Therefore, the manufacturing process is simplified. Moreover, the surface resistance is lowered and the wiring space is enlarged.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Inventor: Chih-Chung Lin
  • Patent number: 8959757
    Abstract: In one embodiment, a shielded electronic module is formed on a substrate. The substrate has a component area and one or more electronic components attached to the component area. One set of conductive pads may be attached to the component area and another set of conductive pads may be provided on the electronic component. The conductive pads on the component area are electrically coupled to the conductive pads of the electronic component by a conductive layer. A first insulating layer is provided over the component area and underneath the conductive layer that may insulate the electronic component and the substrate from the conductive layer. A second insulating layer is provided over the first insulating layer that covers at least the conductive layer. In this manner, the conductive layer is isolated from an electromagnetic shield formed over the component area.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: February 24, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Thong Dang, Mohsen Haji-Rahim, Mark Charles Held
  • Patent number: 8959756
    Abstract: A method of manufacturing a core substrate having an electronic component, including providing a core substrate having a first surface and a second surface on an opposite side of the first surface, forming a through hole extending from the first surface to the second surface in the core substrate, attaching an adhesive tape to the second surface of the core substrate such that the through hole formed in the core substrate is closed on the second surface, attaching an electronic component to the adhesive tape inside the through hole, filling the through hole with a filler, and removing the adhesive tape from the second surface of the core substrate.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: February 24, 2015
    Assignee: IBIDEN Co., Ltd.
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 8959761
    Abstract: A method of manufacturing a polymer electrode is provided. The method includes adhering a shadow mask onto a substrate, forming a hydrophilic electrode pattern on the substrate, coating the hydrophilic electrode pattern of the substrate with a conductive polymer water solution, removing the shadow mask, and drying the conductive polymer water solution, thus forming the polymer electrode.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-dong Jung, Seung-Tae Choi
  • Patent number: 8959760
    Abstract: A method for manufacturing a printed wiring board, including providing a support board having a metal foil secured to the support board, forming a resin insulation layer on the metal foil, forming openings in the resin insulation layer, forming a conductive circuit on the resin insulation layer, forming in the openings via conductors to electrically connect the conductive circuit and the metal foil, separating the support board and the metal foil, and forming from the metal foil external terminals to electrically connect to another substrate or electronic component.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 24, 2015
    Assignee: Ibiden Co., Ltd.
    Inventors: Ayao Niki, Kazuhisa Kitajima
  • Patent number: 8959734
    Abstract: An interactive card or the like employs a piezoelectric charge generator (piezo-strip) for temporarily driving an indicator. The piezo-strip may be displaced (bent) in order to generate charge to drive the indicator. Printed electronic processes are utilized to produce the indicator and/or the piezoelectric charge generator. An indicator is formed on a substrate by way of a printed electronics process. A displaceable region of piezoelectric material associated with the said substrate is formed by way of a printed electronics process. Electrical interconnections are formed on said substrate by way of a printed electronics process. The electrical interconnections connecting said indicator and said first region of piezoelectric material such that displacement of said first region of piezoelectric material generates a voltage therein that is provided to said indicator in order to actuate said indicator and thereby indicate the displacement of said first region of piezoelectric material.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 24, 2015
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Tse Nga Ng
  • Publication number: 20150050028
    Abstract: A structured substrate for optical fiber alignment is produced at least in part by forming a substrate with a plurality of buried conductive features and a plurality of top level conductive features. At least one of the plurality of top level conductive features defines a bond pad. A groove is then patterned in the substrate utilizing a portion of the plurality of top level conductive features as an etch mask and one of the plurality of buried conductive features as an etch stop. At least a portion of an optical fiber is placed into the groove.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: International Business Machines Corporation
    Inventors: Russell A. Budd, Paul F. Fortier
  • Publication number: 20150049441
    Abstract: A method of manufacturing is provided that includes singulating a circuit board from a substrate of plural of the circuit boards, wherein the circuit board is shaped to have four corner hollows. The corner hollows may be various shapes.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 19, 2015
    Inventors: Suming Hu, Neil McLellan, Andrew K.W. Leung, Jianguo Li
  • Publication number: 20150049409
    Abstract: A display panel is provided including a first substrate, an upper structure, and a first conductive pattern. The first substrate may include an upper surface and a lower surface on opposite sides of the first substrate, the upper and lower surfaces facing away from each other. The upper structure may be on the upper surface of the first substrate. A first conductive pattern layer may be on the lower surface of the first substrate. The first conductive pattern layer may be configured to absorb and discharge static electricity input from outside the display panel.
    Type: Application
    Filed: August 6, 2014
    Publication date: February 19, 2015
    Inventors: Min-Hee CHOI, Hyun-Chol BANG
  • Publication number: 20150047187
    Abstract: This invention provides a method and apparatus for manufacturing electronic devices. The method includes: providing a substrate having a first surface; providing an electronic device having bumps; mounting the bumps to the first surface to form an integrated unit; applying a capillary underfill to multiple sides of the electronic device, enabling the underfill to creep along and fill the gap between the electronic device and the substrate; placing the integrated unit into a processing chamber; raising the temperature in the chamber to a first predetermined temperature; reducing the pressure in the chamber to a first predetermined pressure of a vacuum pressure, and maintaining the vacuum pressure for a predetermined time period; raising the pressure in the chamber to a second predetermined pressure higher than 1 atm, and maintaining the second predetermined pressure for a predetermined time period; and adjusting the temperature in the chamber to a second predetermined temperature.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 19, 2015
    Inventor: Shu-Hui Hung
  • Publication number: 20150049447
    Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.
    Type: Application
    Filed: August 15, 2014
    Publication date: February 19, 2015
    Inventors: Bum Mo Ahn, Seung Ho Park, Kyoung Ja Yun
  • Publication number: 20150047977
    Abstract: The present invention provides an automatic encoding device including a first electrode, a second electrode, and a third electrode. The first electrode and the second electrode are connected through a connecting point, so that an electric parameter between the first electrode and the second electrode changes according to a parameter needing to be corrected. The present invention further provides a method for applying the automatic encoding device to various biosensors and a method for manufacturing the automatic encoding device. Positions and the number of contacts for connecting the automatic encoding device and a detection system are fixed. Therefore, connection sites on the detection system are effectively utilized. On the other hand, the automatic encoding device in the present invention can provide different parameter information by only changing the positions of the connecting points on the electrodes, the process is simple and stable, and the probability of human errors is reduced.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 19, 2015
    Inventors: Tao Liu, Huanxi Ge, Chia-Lin Wang, Yun Ye
  • Patent number: 8957322
    Abstract: A patterned transparent conductor including a conductive layer coated on a substrate is described. More specifically, the transparent conductor has low-visibility patterns.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: February 17, 2015
    Assignee: Cambrios Technologies Corporation
    Inventors: Jeffrey Wolk, Michael R. Knapp
  • Patent number: 8957323
    Abstract: An electrical connecting element, a method of fabricating the same, and an electrical connecting structure comprising the same are disclosed. The method of fabricating the electrical connecting structure having twinned copper of the present invention comprises steps of: (A) providing a first substrate; (B) forming a nano-twinned copper layer on part of a surface of the first substrate; (C) forming a solder on the nano-twinned copper layer of the first substrate; and (D) reflowing the nano-twinned Cu layer and solder to produce a solder joint, wherein at least part of the solder reacts with the nano-twinned copper layer to produce an intermetallic compound (IMC) layer which comprises a Cu3Sn layer, This invention reduces the voids formation in the interface between the intermetallic compound and the solder, and then enhances the reliability of solder joints.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: February 17, 2015
    Assignee: National Chiao Tung University
    Inventors: Chih Chen, Wei-Lan Chiu
  • Patent number: 8955219
    Abstract: The invention relates to a method for fabricating a bond by providing a body including a metallic surface provided with an inorganic, dielectric protective layer. The protective layer covers at least one surface zone of the metallic surface in which the metallic surface is to be electrically conductive bonded to a contact conductor. To fabricate the bond, a portion of a provided contact conductor above the surface zone is pressed on to the protective layer and the body so that the protective layer is destroyed above the surface zone in achieving an electrically conductive bond between the metallic surface and the contact conductor.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Roman Roth, Dirk Siepe
  • Patent number: 8955216
    Abstract: A compliant printed circuit semiconductor package including a compliant printed circuit with at least a first dielectric layer selectively printed on a substrate with first recesses. A conductive material is printed in the first recesses to form contact members accessible along a first surface of the compliant printed circuit. At least one semiconductor device is located proximate the first surface of the compliant printed circuit. Wirebonds electrically couple terminals on the semiconductor device to the contact members. Overmolding material seals the semiconductor device and the wirebonds to the first surface of the compliant printed circuit. Contact pads on a second surface of the compliant printed circuit are electrically coupled to the contact members.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: February 17, 2015
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Publication number: 20150041180
    Abstract: Disclosed herein are a printed circuit board including: an insulating layer; and a metal circuit layer formed on at least one surface of the insulating layer, wherein the metal circuit layer has surface roughness on only its one surface, and a method of manufacturing the same.
    Type: Application
    Filed: December 12, 2013
    Publication date: February 12, 2015
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Jae LEE, Kyung Moo HAR, Young Do KWEON, Jin Gu KIM
  • Publication number: 20150045980
    Abstract: A power monitoring system comprises an input module, a plurality of switches, a plurality of power supply ports, a detecting module, a control module, and a wireless transmission module. The each switch was set in between the input module, and each switch has an address. The detecting module generates a power loading value by set in between the input module and each power supply port. The control module connects to switches, the detecting module and the wireless transmission module, thus, the control module can read the power loading values from the detecting module, and control each switch which corresponds to the address by a preset rule or a command from the wireless transmission module. It will not only save energy but also improve the electricity security for the household.
    Type: Application
    Filed: March 28, 2014
    Publication date: February 12, 2015
    Inventor: Cheng-Tsuen Hsu
  • Publication number: 20150041188
    Abstract: A power module substrate includes a circuit layer, an aluminum layer arranged on a surface of an insulation layer, and a copper layer laminated on one side of the aluminum layer. The aluminum layer and the copper layer are bonded together by solid phase diffusion bonding.
    Type: Application
    Filed: March 29, 2013
    Publication date: February 12, 2015
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo, Yoshirou Kuromitsu
  • Publication number: 20150040391
    Abstract: A method of forming a control module for an electrical stimulation system, the control module including an electronic subassembly disposed in an inner space of a casing and a feedthrough housing disposed along a portion of the casing, includes: forming an RF-diverting assembly having capacitive elements electrically-coupled to a feedthrough ground; electrically-coupling the capacitive elements to conductive pathways extending along a non-conductive substrate; electrically-coupling the conductive pathways to feedthrough pins extending through the feedthrough housing from a location external to the casing to a location within the inner space of the casing; electrically-coupling the conductive pathways to the electronic subassembly such that the conductive pathways electrically-couple the feedthrough pins to the electronic subassembly; electrically-coupling the feedthrough ground to an electrically-conductive portion of the feedthrough housing; and electrically-coupling the electrically-conductive portion of the
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Inventors: Zdzislaw B. Malinowski, Salomo Murtonen, Mizan Rahman
  • Publication number: 20150045643
    Abstract: The present technology relates generally to intraocular pressure (“IOP”) monitoring systems and associated devices and methods. In some embodiments, an intraocular pressure monitoring system configured in accordance with the technology comprises an implantable intraocular assembly and an external unit configured to transmit power to and receive data from the intraocular assembly. The intraocular assembly can include an IOP sensing device embedded within a flexible, expandable annular member. The IOP sensing device can include an antenna, a pressure sensor, and a microelectronic device encapsulated by an elastomer.
    Type: Application
    Filed: September 16, 2013
    Publication date: February 12, 2015
    Inventors: Cagdas Varel, Tueng T. Shen, Karl F. Bohringer, Brian Otis, Buddy D. Ratner