Abstract: In order to realize the object of the present invention, which is to provide a noise detection circuit which is capable of coping with any pulse width of noise, and also of properly detecting the noise pulses which are consecutively generated, the noise detection circuit comprises a level monitoring circuit for monitoring the logic level of a signal input to a peripheral circuit within a microcomputer that needs to receive an input signal having a logic high level constantly for a certain period; wherein the level monitoring circuit further comprises a NOT circuit that inverts the polarity of a level monitoring signal input from the peripheral device for determining a signal level monitoring period, and an OR circuit that performs an OR operation between the output from the NOT circuit and the signal input to the peripheral device.

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node.

Abstract: A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: An input signal preconditioning circuit receives at least first and second digital input signals. The input signals are modified to provide first and second preconditioned input signals which cannot simultaneously transition in opposite directions.

Abstract: The present invention addresses the foregoing needs by providing a circuit implemented in SOI (silicon on insulator) CMOS, which includes a first node precharged to an activated level, a first transistor coupled between the first node and the second node, a second transistor coupled between the second node and a ground potential, and a third transistor coupled to the second node and operable for preventing the second node from rising to the activated level. The third transistor prevents the parasitic bipolar effect from raising this second node to the activated level. Essentially, the third transistor maintains the second node substantially at a ground level.

Abstract: A semiconductor integrated circuit including an input circuit constituted as a single-input differential circuit which has a first MOSFET to whose gate a reception signal with a small amplitude with respect to a power supply voltage is supplied and a second MOSFET to whose gate a reference voltage corresponding to an intermediate value of the reception signal is supplied. A dummy circuit is provided and transmits substantially the same power supply noise as the power supply noise transmitted to the gate of the first MOSFET through a electrostatic protection circuit provided to an external terminal which receives the reception signal.

Abstract: A fail-safe interface circuit comprises at least one semiconductor switching circuit (1) with a first link terminal (2), a second link terminal (4) and a control terminal (6). To connect a first and second circuit (8, 10) attached to the first and second link terminal (2, 4), respectively, a potential difference between the control terminal (6) and one of the link terminals (2, 4) is raised above a predetermined threshold value. To avoid any flow of current from the second circuit (10) to the first circuit (8) or vice versa when the interface circuit is powered off, the maximum potential at the first and second link terminal (2,4) is actively fed back to the control terminal (6) of the semiconductor switching circuit (1).

Abstract: A crow-bar current reduction circuit for use with a NMOS output circuit a gate voltage control circuit (GVC). The GVC receives a data signal and an output enable signal and generates control signals to drive the gates of the output transistors of the output circuit. When enabled, the GVC delays the rising edges of the gate control signals so as to help ensure that during a transition of the output signal generated by the output circuit, the NFET that was conductive before the transition is "turned off" to become non-conductive before the NFET that was non-conductive before the transition is "turned on" to become conductive. When adapted for a CMOS output circuit, the GVC delays the rising edge of the gate control signal provided to the NMOS pull-down transistor and delays the falling edge of gate control signal provided to the PMOS pull-up transistor.

Abstract: A LVDS receiver (200) converts a differential input signal (15) at an input (201/202, e.g., voltage difference V.sub.1 -V.sub.2) to a single output signal (20) at an output (295). The receiver (200) has a signal distributor (205), first and second transistor pairs (220,210), a combiner (260), and an output trigger (250). The distributor (205) either forwards the differential input signal (15) to the first transistor pair (220) when the common mode portion of the input signal (15, e.g., V.sub.CM =(V.sub.1 +V.sub.2)/2) of the first and second input signal components is in a first magnitude range (e.g., V.sub.CM >V.sub.REF) or to the second transistor pair (210) when the common mode portion is in a second, different magnitude range (e.g., V.sub.CM <V.sub.REF). The transistors of both pairs (210 and 220) are of the same conductivity type. This approach provides substantially constant input transconductances (g.sub.m) over the whole common mode input signal range.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.

Abstract: In a digital circuit, a method for avoiding a bus contention condition which results from an overlap of active phases of multiple bus drivers. The method avoids such bus contention condition by including holding amplifiers in the data bus and by turning on respective bus drivers only for durations sufficient to establish a data value on the data bus.

Abstract: A control circuit for a low-voltage bus switch where the control circuit keeps the bus switch open by stealing power from switch I/O terminals during the loss of supply voltage and thereby maintaining bus isolation. The control circuit also provides a good high level and presents a low switch impedance.

Abstract: A semiconductor integrated circuit is constructed with composite pass-transistor logic circuits serving as elementary circuit units each including a plurality of pass-transistor logic trees and a multiple-input logic gate. A wide variety of logical operations, even complex opearations, can be efficiently expressed using the composite pass-transistor logic circuit, and the resultant logic circuit can operate at a high speed. Thus, the semiconductor integrated circuit of the present invention can realize various logic functions required for various users in an efficient fashion. The present invention is particularly useful when applied to a field-programmable gate array integrated circuit, since complex logical operations can be expressed in a simple and efficient fashion by the composite pass-transistor logic circuits. The gate array integrated circuit obtained in accordance with the present invention can operate at a high speed with low power consumption.

Abstract: Erroneous operation protection circuits (EOPs) are provided between a plurality of precharge type data bus wirings which are set to predetermined potential beforehand and to which a plurality of circuit blocks are connected to transfer signals. Accordingly, an increase in stray capacitance of the data bus wirings can be suppressed to the lowest minimum to thus prevent erroneous operation due to coupling noises between the data bus wirings. The EOP comprises a coupling noise detector (CND) for detecting whether or not data transition on a first data bus wiring is caused by coupling noises due to capacitance between the first data bus wiring and a second data bus wiring being aligned in close vicinity to the first data bus wiring, and a precharge device for shifting potential of the first data bus wiring to return to predetermined potential if the coupling noise detector has detected the coupling noises.

Abstract: An integrated circuit output driver provides high speed communication, such as between integrated circuits in spite of appreciable interconnection capacitance. The output driver reduces the current sourced or sunk from a circuit node during its switching as its voltage approaches power supply or ground voltages. This reduces the voltage swing and ringing at the circuit node during high speed communication, thus reducing switching time. The output driver provides full voltage swing under quiescent conditions, preserving minimum leakage currents in steady state.

Abstract: Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Abstract: A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven.

Abstract: A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Abstract: An impedance adjusting apparatus of a controlling chip on a computer mainboard. When a computer is turned on, BIOS automatically detects the actual usage of the memory sockets, and then sends corresponding control signals to adjust the impedance of the impedance adjusting apparatus for a better impedance matching between the controlling chip and the memory sockets. The signal reflection is dramatically reduced and the operation bandwidth is widened.

Abstract: Briefly, in accordance with one embodiment of the invention, a slew rate control circuit for a processor includes: a circuit configuration to produce a signal representing the speed of fabricated transistors; and a circuit configuration to adjust, based at least in part on the signal representing the speed of fabricated transistors, the amount of current produced by a pre-driver stage for an output buffer of the processor. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a slew rate control circuit for a buffer including: a register capable of storing at least one binary digital signal, a pre-driver, and at least one pre-driver cell coupled to the pre-driver. The at least one pre-driver cell is coupled to the pre-driver and register so as to modify the amount of current produced by the pre-driver based, at least in part, on the at least one binary digital signal.

Abstract: A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.

Abstract: A circuit configured with MOSFETs having a first range of subthreshold conduction, is provided with at least one switchable pathway between the circuit and a power or ground node, such that the switchable pathway is operable to substantially reduce leakage current through the circuit. In a further aspect of the present invention, the switchable pathway is a FET having substantially the same subthreshold conduction characteristics as the FETs in the circuit to which the switchable pathway is coupled, the FET being configured to be driven into both inversion and accumulation.

Abstract: A circuit and method for clocking for logic circuits use delay line techniques to time the clock signal. The inputs into a logic circuit are associated with a validity signal, which is delayed by a delay line for at least the propagation delay of the logic circuit. The delayed validity signal is used to latch an output signal produced by the logic circuit in response to the inputs.

Abstract: A semiconductor integrated circuit has an integrally formed logic circuit that is controlled by clock signals. The semiconductor integrated circuit includes a clock signal delay device that generates a plurality of clock signals having phases that are shifted from each other by a small amount with respect to a reference clock signal. The logic circuit is divided into a plurality (N number) of circuit blocks so that each of the circuit blocks is controlled by each of the associated plurality of clock signals to reduce noises. Noises in a CMOS integrated circuit are also reduced by controlled reference clock signals. A CMOS integrated circuit includes at least one CMOS gate with an input terminal being commonly connected to gates of a PMOS transistor and an NMOS transistor, and a latch circuit for transmitting data to the input terminal of the CMOS gate by clock signal control.

Abstract: In one aspect of the present invention, a bus buffer is provided. The bus buffer includes at least one buffer group having first and second groups of control input terminals. The first and second groups of control input terminals control different operational characteristics of the buffer group. The bus buffer includes first and second capture registers and first and second update registers. The data output terminals of the first update register are connected to the first group of control input terminals. The data output terminals of the second update register are coupled to the second group of control input terminals. The data input terminals of the first and second update registers are coupled to the data output terminals of the first and second capture registers, respectively. The bus buffer includes a new settings register having data output terminals coupled to the data input terminals of the capture registers.

Abstract: A constant slew rate amplifier has a precision internal slew rate control reference, that generates respective positive-going and negative-going voltages, associated with corresponding excursions in the input signal. These slew rate-defining voltages are decoupled from the line, making it possible to drive the line with an amplified output signal that faithfully follows the input signal and conforms with prescribed slew rate and rise/fall time specifications, irrespective of the capacitance of the line. In addition, the constant slew rate amplifier of the present invention is configured to minimize power dissipation during non-transitional signal conditions, while providing substantial current to rapidly drive the line from one state to another in accordance with the input signal.

Abstract: A hot-swappable, point-to-point connection between a high speed transmitter on a transmitter card and a high speed receiver on a receiver card is provided. The transmitter card and the receiver card can be inserted into a backplane, the backplane forming the connection between the transmitter and the receiver. The system includes a power indicator on the transmitter card and the receiver card, with each power indicator asserting a power signal to respective switch control inputs on the transmitter and receiver cards when the respective cards are inserted into the backplane. The assertion or unassertion of a power signal to the control inputs allows for the disabling of the receiver when the transmitter is not connected to the backplane and the disabling of the transmitter when the receiver is not connected to the backplane, thereby preventing transmitter output EMI and ringing and receiver input oscillation.

Abstract: Embodiments of the invention include a method and arrangement of integrated circuit components for enhancing the integrity of communication signals transmitted through a multi-device communication system. Embodiments of the invention provide controllable impedance arrangements for coupling to one or more integrated circuit components coupled along a bus transmission line within the communications system. The coupled impedance arrangements establish damping impedances for selected devices between the signal transmitting component and the signal receiving component along the bus transmission line to advantageously reduce distortion and ringing associated with the LC parasitic network behavior of the devices. Typically, a damping impedance is coupled to the integrated circuit component immediately adjacent to the signal transmitting component along the bus transmission line between the signal transmitting component and the signal receiving component.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes circuitry for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing device for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A method and dynamic circuit selectively controls the amount of feedback that is supplied to the dynamic node to provide more feedback when more is needed to enhance functional operation and less feedback when less is needed to enhance performance. The additional feedback inhibits the detrimental effects of charge loss due to leakage and noise mechanisms. The circuit may, for example, selectively control the amount of feedback in response to a test signal. The test signal can be manipulated to cause the circuit to provide more feedback when the circuit is undergoing reliability stress testing and less feedback when the circuit is in normal operation as part of an electronic device.

Abstract: A high speed bus circuit system according to the present invention includes a bus having alternately connected resistors and transmission lines, and integrated circuits. Each of the resistors has a predetermined resistance value. The transmission lines are mounted on print circuit boards. The bus is connected in a loop form as a whole. Each of the integrated circuits has a driver and a receiver. The driver and receiver are connected to respective one of the resistors. As a result, DC power dissipation in the terminal resistor of the bus circuit is suppressed. In addition, high speed signal transfer causing less waveform distortion is made possible.

Abstract: An input circuit provided in a semiconductor integrated circuit, comprises an nMOS transistor having a source connected to an input node receiving a transmission signal, a drain connected to a first node and a gate connected to a reference potential, and a pMOS transistor having a source connected to a power supply voltage, a drain connected to the first node, a first inverter having an input connected to the first node and an output connected to an output terminal, and a second inverter having an input connected to the first node and an output connected to a gate of the pMOS transistor, so that when the nMOS transistor is turned on, the pMOS transistor is rendered off, whereby no steady input current flows.

Abstract: A buffer having an output slew rate which is relatively insensitive to loading and supply voltage. The output buffer includes an output node, a first half-circuit and a second half-circuit. The first half-circuit is for slewing the output node from a first voltage to a second voltage. The first half-circuit includes a first output transistor connected between the output node and a second voltage reference node, a first switching device connected from a gate of the first output transistor to the second voltage reference node, a second switching device connected from the gate of the output transistor to a first node, a first current source connected from a first voltage reference node to the first node, and a first capacitor connected from the output node to the first node. The second half-circuit is for slewing the output node from the second voltage to the first voltage.

Abstract: A single event upset (SEU) sensitivity control system (42) dynamically hardens a digital circuit (48) to single event upsets. The sensitivity control system (42) includes an upset rate sensor (66) for detecting a quantity of particles (38) that cause single event upsets. A noise margin control circuit (70) is configured to adjust a noise margin (46) of the digital circuit (48) in response to the quantity of particles (38). Noise margin (46) is increased when a particle density (34) is high to decrease the sensitivity of the digital circuit (48) to single event upsets. Additionally, noise margin (46) is decreased when a particle density (36) is low to decrease the power consumption level of digital circuit (48).

Abstract: A driver circuit for supplying an electric current to a device having a pair of power FET's connected in series between the device and a power supply.

Abstract: An integrated circuit driver chip includes an on-board precision current reference source, a pull-up FET and a pull-down FET having a common node connected to a transmission line. A variable switching edge pre-driver drives at least one of the pull-up FET and pull-down FET in accordance with a push-pull fast edge mode and a wired-OR slow edge mode and includes a weak FET and a strong FET selectively connected in parallel with the weak FET to implement the push-pull fast edge mode while the weak FET operating alone implements the wired-OR slow edge mode. A switched current source selectively sources current through the pull-up FET to the transmission line in accordance with the data signal and includes a trickle current FET switch for maintaining charge stored on a parasitic capacitance when the pull-up FET is off thereby preventing current spikes during turn-on switching of the pull-up FET.

Abstract: A high-speed receiver is disclosed for gathering data from an information signal carried on a superconducting transmission line. The high-speed receiver includes triggers that carry trigger pulses, and a plurality of superconducting sensors magnetically coupled to the transmission line. The sensors respond to the trigger pulses by capturing data from the information signal. The sensors may operate in a variety of capacities, including comparators, A to D converters, and logic functions.

Abstract: There is provided a bus receiver including a first differential amplifier comparing an input signal to a first reference voltage, and transmitting a first pulse signal accordingly, a second differential amplifier comparing the input signal to a second reference voltage, and transmitting a second pulse signal accordingly, an exclusive OR circuit transmitting an exclusive OR pulse signal indicative of exclusive OR of the first and second pulse signals, a first flip-flop circuit receiving the exclusive OR pulse signal as clock, and receiving the second pulse signal as data, and a selector selecting one of the first and second pulse signals in accordance with an output of the first flip-flop circuit. The bus receiver readily eliminates noises. The bus receiver may further include a second flip-flop circuit receiving external clock as clock, and receiving an output of the selector as data.

Abstract: A digital interface circuit has two inverters with different switching points, one below and one above the nominal transition point of the circuit. Each inverter controls both pull-up and pull-down output transistors. The inverter with the low switching point controls the low-to-high signal transition, while the inverter with the high switching point controls the high-to-low signal transition. Pass gates responsive through delay elements to either the circuit input, an inverter output, or the circuit output isolate the other inverter from the output transistors. The pass gates may also be tristatable by means of a logical combination of the delayed pass gate enable signals with output enable signals. In yet another embodiment, the pair of inverters are replaced by a single inverter with dual switching points.

Abstract: The integrated circuit includes an input path circuit with an address path having an input buffer for providing address signals to a register. A separate clock path having an input buffer provides a clock signal for clocking the register. The input path circuit also includes one or more decode units each having a number of logic gate cells such as NAND gate cells or NOR gate cells. Circuitry is provided within the logic gates for reducing timing delay differences between propagation of multiple bit binary signals, such as address signals, through the logic gates. In an exemplary NAND gate described herein, reduction in timing delay differences is achieved by positioning an additional PMOS device along a current path between a power source and an output path otherwise including only a pair of parallel PMOS devices.

Abstract: Circuit for immunizing an integrated circuit from noise affecting external enable signals of the integrated circuit generated during switching of circuit blocks internal to the integrated circuit, comprising first means for detecting a switching of said circuit blocks and for driving second means for forcedly activating internal enable signals of the integrated circuit depending on said external enable signals, in order to forcedly maintain said internal control signals activated during said switching of said circuit blocks.

Abstract: First current is conducted through a first path to adjust a voltage at a node toward a predetermined level in response to the voltage being within a first subrange of voltages. Second current is conducted through a second path to adjust the voltage at the node toward the predetermined level in response to the voltage being within a second subrange of voltages.

Abstract: A method and apparatus for a circuit physically realizing a CMOS buffer with a controlled slew rate at the output and using no additional standby power to achieve the slew rate control is described. A feedback path from the output is coupled to transistors comprising a differential pair, the transistors are further coupled to a capacitance. The discharge rate of the capacitance and the size choices of the transistors in the circuit are used with the feedback path to control the high-to-low and low-to-high transition rate of the output. The circuit of the invention allows a system designer to construct a buffer for driving a bus with excellent on chip and bus signal noise characteristics using standard digital CMOS technology and having excellent standby and active power characteristics. An open drain buffer and a push-pull buffer are described. An integrated circuit implementing application logic coupled to input/output and output buffers embodying this circuit is disclosed.

Abstract: A noise detection and delay receiver circuit includes a circuit input and output and a plurality of individual receiver circuits connected to the input having trip points which range from a low trip point to a high trip point. Edge detect circuitry and delay circuitry are used to prevent the output from changing back to the previous state for a period of time immediately after it has just changed state. Multiple transitions of the input voltage across the trip points of the individual receivers are used to delay the response until noise has settled out of the input signal.

Abstract: A true/complement integrated circuit device is disclosed for reducing an amount of simultaneous switching on a bus between a current state and a next state. The device includes a current state register connected to the bus for outputting the current state onto the bus during a first clock cycle. A next state register is provided for containing the next state, wherein the next state is a pending state of the bus intended for a next clock cycle. A comparison circuit compares a current state value in the current state register with a next state value in the next state register on a bit-by-bit basis to determine if the current state value and the next state value are of a same polarity or of an opposite polarity. A circuit is provided for determining a ratio of switching signals from an output of the bit-by-bit comparisons by the comparison circuit.

Abstract: A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.