Abstract: Techniques for adaptive gain adjustment in a signal processing path to achieve greater dynamic range. In an exemplary embodiment, a digital gain is applied to a digital input signal based on a detected level of the digital input signal. A corresponding analog gain is applied to the output of a digital-to-analog converter for converting the digital input signal to an analog signal, the product of the digital gain and the analog gain being kept constant. In an exemplary embodiment, a zero cross detector is employed to update the digital and analog gains only in the vicinity of zero crossings detected in the signal. In a further exemplary embodiment, a peak detector is employed to instantaneously adjust the digital and analog gains to avoid clipping in the signal path.

Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 10. The integrating circuit 10 includes an amplifier circuit 20, a capacitive element C, a first switch SW1, and a second switch SW2. The second switch SW2 is provided between a reference potential input terminal to which a reference potential Vref is input and a terminal of the capacitive element C on the inverting input terminal side of the amplifier circuit 20, and the second switch is opened or closed according to the level of a second reset signal Reset2, and is capable of applying the reference potential Vref to the terminal of the capacitive element. Thus, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.

Abstract: Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.

Abstract: A signal level conversion circuit 1 includes a first differential amplifier circuit 10 and a second differential amplifier circuit 20. The first differential amplifier circuit 10 multiplies a potential difference between a first input signal and a second input signal by G1 thereby providing an output signal. The second differential amplifier circuit 20 multiplies a potential difference between the output signal of the first differential amplifier circuit 10 and the second input signal by G2 thereby providing an output, where the two gains satisfy the relation of G1×G2<0 and 0<?(G1+1)×G2<2.

Abstract: A method and an electronic circuit, the electronic circuit includes: a first circuit; a leakage measurement circuit arranged to determine a leakage level of the first circuit when the first circuit is in a standby mode, and to determine an information maintenance level of a supply voltage in response to the leakage level; and a voltage supply circuit arranged to provide to the first circuit a supply voltage of a functional level when the first circuit is in a functional mode, and to provide to the first circuit a supply voltage of the information maintenance level when the first circuit is in the standby mode; wherein the first circuit is arranged to maintain information when provided with the supply voltage of the information maintenance level.

Abstract: An electronic device which includes a first stage having an input capacitance, a switch, a buffer and a second stage having an input sensitive to charge injection and/or voltage glitches. An input of the buffer and the input of the second stage are coupled together at a first node which is configured to be coupled to a voltage source for supplying a reference voltage to the input of the first stage having the input capacitance. In a first configuration of the switch, the switch is arranged to either connect the input of the first stage to the first node and to disconnect the input of the first stage from an output of the buffer. In a second configuration of the switch, to connect the input of the first stage to the output of the buffer and to disconnect the input of the first stage from the first node.

Abstract: A hysteresis device produces an output signal in accordance with hysteresis characteristics that changes at a plurality of thresholds with respect to an input signal. The hysteresis apparatus includes an input signal adjusting section that outputs an adjustment signal in which an offset level corresponding to each of the plurality of thresholds is added to the input signal, a comparator that outputs a first signal based on the adjustment signal, the first signal being binarized, and a determining section that controls the input signal adjusting section to switch the offset level for each of the plurality of thresholds, that acquires the first signal for each switching of the offset level, and that produces a present output signal based on a previous output signal and the first signal corresponding to the threshold relating to a range to which the input signal is belonged.

Abstract: A waveform shaping device shapes a waveform of an externally input signal and outputs the input signal with the shaped waveform as an output signal to an equalizer for compensating a distortion of a signal, and includes a nonlinear process section for generating a nonlinear process signal (i) in which positive and negative signs of a low-frequency-free signal obtained by removing at least a direct current component from frequency components of the externally input signal are retained and (ii) which broadly monotonically increases nonlinearly with respect to the low-frequency-free signal when values of the low-frequency-free signal are at least in the vicinity of 0, the nonlinear process signal being added to the low-frequency-free signal so as to generate the input signal.

Abstract: A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.

Abstract: A compensation circuitry of gate driving pulse signal is adapted to receive a gate driving pulse signal and includes a pre-processing circuit, a peak detector, a discharge circuit, a voltage buffer and a charge pump circuit. The pre-preprocessing circuit performs a pre-processing operation to the gate driving pulse signal to adjust a voltage thereof. The pre-processed gate driving pulse signal then is transmitted to the peak detector for obtaining a peak voltage after a charging operation, and also is transmitted to the discharge circuit to determine whether to enable the discharge circuit so that providing the peak detector with a discharge loop when the discharge circuit is enabled. The charge pump circuit acquires the peak voltage through the voltage buffer and then modulates a waveform of the gate driving pulse signal according to the peak voltage. A display device using the above compensation circuitry also is provided.

Abstract: For voltage interpolation amplifiers used in digital-to-analog converter architecture, the number of input differential pairs required by the voltage interpolation amplifier may be reduced such that an N-bit voltage interpolation amplifier comprises N+1 input differential pairs connected through a resistor attenuation network to provide a binary-weighted effective transconductance. In comparison to conventional voltage interpolation amplifier designs, the number of input differential pairs and power consumed by the circuit is significantly reduced, thereby creating a more area- and power-efficient voltage interpolation amplifier.

Abstract: A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node.

Abstract: A relay circuit for relaying signal transmission between a first circuit driven by a first voltage and a second circuit driven by a second voltage different from the first voltage, the relay circuit includes: a waveform shaping circuit that obtains a shaped voltage by shaping a waveform of the second voltage in order to make a change of the second voltage steeper; and a buffer circuit that is driven by the first voltage and interrupts a signal transmission by the buffer circuit if the shaped voltage obtained by the waveform shaping circuit falls to or below a predetermined value, the shaped voltage being input to the buffer circuit as a control signal.

Abstract: A semiconductor integrated circuit includes a selector to selectively output and supply to a monitoring target voltage terminal one of a power supply voltage from an outside of the semiconductor integrated circuit and a predetermined reference voltage depending on an adjusting mode signal, a voltage monitoring circuit to monitor a voltage fluctuation at the monitoring target voltage terminal and converting the voltage fluctuation that is monitored into a control signal, and an input and output circuit to output the control signal to the outside.

Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Abstract: A voltage adjusting circuit includes a voltage adjusting chip, a processor, first and second voltage converting circuits, and a control circuit. The voltage adjusting chip converts a first voltage to a second voltage. The processor receives the second voltage and a control signal. The second voltage converting circuit converts the second voltage to a third voltage. The first voltage converting circuit converts the third voltage to the second voltage according to the control signal from the processor for supplying the second voltage to the processor and the control circuit. The control circuit is connected between the first voltage converting circuit and the voltage adjusting chip. The control circuit deactivates the voltage adjusting chip when receiving the second voltage from the first voltage converting circuit.

Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads.

Abstract: A multi-voltage level, multi-dynamic circuit structure device and method are disclosed. In a particular embodiment, the method includes discharging a first dynamic node at a first discharge circuit of a first dynamic circuit structure in response to receiving an asserted discharge signal. The first dynamic circuit structure includes the first dynamic node at a first voltage level and a first keeper circuit that is disabled when the asserted discharge signal is received. The asserted discharge signal has a second voltage level that is different from the first voltage level. A second keeper circuit of a second dynamic circuit structure is enabled responsive to discharging the first dynamic node to maintain a second dynamic node of the second dynamic circuit structure at the first voltage level.

Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: Lightweight automatic gain control (AGC) methods and systems reduce usage of often scarce computing resources in ambulatory monitoring systems through an AGC algorithm that relies on lightweight calculations and judicious constraints on gain reevaluations and adjustments. Statistical range sampling is used to adjust the gain of a physiological signal to keep the signal within a target amplitude range and may be coupled with dynamic range control to prevent gain adjustments from occurring too frequently. Moreover, gain reevaluations and adjustments may be temporarily suspended when the physiological signal is noisy.

Abstract: A transmitter includes a capacitor from one end of which a charge voltage is derived; a first constant current source to generate a charge current for the capacitor; a second constant current source to generate a discharge current for the capacitor; a charge/discharge controller to perform charge/discharge control of the capacitor based on a logic level of a transmission input signal and a comparison result between the charge voltage and a reference voltage; an output stage to generate the transmission output signal, wherein a slew rate of which is set in response to the charge voltage, and wherein an amplitude of the transmission output signal is set in response to an output side power source voltage; a reference voltage generator to fluctuate the reference voltage depend on the output side power source voltage; and a constant current controller to fluctuate a current value of the charge current and the discharge current depend on the reference voltage.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract: Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range.

Abstract: In accordance with various aspects of the present invention, a method and circuit for reducing power consumption of a power module during idle conditions is provided. In an exemplary embodiment, a power module is configured for reducing power during idle mode by disengaging at least one power output from a power input. A power module may include one or more power outputs and one or more power module circuits, with power input connected to the power outputs through the power module circuit(s). The power module circuit may include a current measuring system, a control circuit, and a switch. The current measuring system provides an output power level signal that is proportional to the load at the power output. If current measuring system behavior indicates that a power output is drawing substantially no power from the power input, the switch disengages the power input from the power output.

Abstract: A radio receiver includes a down-converter 110 for receiving a radio multiplexed signal containing a first signal and a second signal, multiplying the first signal and the second signal by a mixer 104 to thereby down-convert the radio multiplexed signal and generate an intermediate frequency signal 5e. The mixer 104 has a control section for controlling an operating bias of the mixer 104 in response to a signal strength of at least either one of the first signal or the second signal. Thus, the dynamic range of the mixer can be widened so that stable image characteristics can be obtained over a wide range of transmission distance.

Abstract: A parameter setting circuit and method for an integrated circuit apply a pulse current to a pin of the integrated circuit during a programming mode of the integrated circuit, and then extract the difference between the voltage on the pin and the DC component of the voltage on the pin to determine a setting signal for parameter setting to an internal circuit of the integrated circuit. By this way, an input pin, an output pin or an input/output pin of the integrated circuit may be used as the pin implementing the parameter setting function.

Abstract: An integrated circuit comprises a digitally-controlled power generation stage (DPA) for converting an input signal to a radio frequency (RF) carrier, the DPA comprising a plurality of selectable switching devices capable of adjusting an envelope of the RF carrier; and a pulse width modulator (PWM) generator arranged to generate a PWM control signal and operably coupleable to the plurality of selectable switching devices of the DPA. The PWM generator inputs the PWM control signal to a subset of the plurality of the selectable switching devices such that a PWM signal adjusts the envelope RF carrier output from the DPA.

Abstract: Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled to a common-mode pre-emphasis module, the center-swing signal generator to receive a low swing current mode logic (CML) signal and output a center-swing signal, and a full-swing cross-coupled inverter coupled to the center-swing signal generator, the full-swing cross-coupled inverter to receive the center-swing signal and output a full-rail single-ended swing signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A level control circuit that generates output signal for level control includes: a control information storage that stores control information corresponding to a signal level, a control information circuit that outputs the output signal for level control corresponding to the signal level of a first input signal based on the control information stored in the control information storage; and an information update circuit that updates the control information of the control information storage according to the signal level of a second input signal.

Abstract: A readout electronics scheme is under development for high resolution, compact PET (positron emission tomography) imagers based on LSO (lutetium ortho-oxysilicate, Lu2SiO5) scintillator and avalanche photodiode (APD) arrays. The key is to obtain sufficient timing and energy resolution at a low power level, less than about 30 mW per channel, including all required functions. To this end, a simple leading edge level crossing discriminator is used, in combination with a transimpedance preamplifier. The APD used has a gain of order 1,000, and an output noise current of several pA/?Hz, allowing bipolar technology to be used instead of CMOS, for increased speed and power efficiency. A prototype of the preamplifier and discriminator has been constructed, achieving timing resolution of 1.5 ns FWHM, 2.7 ns full width at one tenth maximum, relative to an LSO/PMT detector, and an energy resolution of 13.6% FWHM at 511 keV, while operating at a power level of 22 mW per channel.

Abstract: An alternating-current (AC) coupling integrated circuit (IC) suppresses signal errors introduced by a steady-state input signal. The IC includes an operational amplifier, a true direct-current (DC) bias network, a complimentary DC-bias network and first and second feedback elements. The operational amplifier has an inverting input, a non-inverting input and an output. The true DC-bias network has first and second branches that are coupled to one another and the non-inverting input. The complimentary DC-bias network has third and fourth branches that are coupled to one another and the inverting input. First and second feedback elements generate first and second control signals in response to a characteristic of one of the true input signal and the complimentary input signal. The control signals prevent the voltage at the inputs to the operational amplifier from reaching an equivalent, steady-state, DC-bias voltage.

Abstract: A peaking circuit for adjusting peaking of a high-frequency signal, comprises: a first inductor; a second inductor which is electromagnetically coupled with the first inductor; a signal input section which receives an input signal; a transistor which adjusts electric current passing through the second inductor according to the input signal inputted via the signal input section; and a signal output section which outputs a signal whose peaking has been adjusted by the first inductor. Mutual inductance of the electromagnetically coupled first and second inductors is changed by the adjustment of the electric current passing through the second inductor, according to the input signal inputted via the signal input section, with the use of the transistor, thereby adjusting the peaking of signal waveform of electric current passing through the first inductor, and the signal subjected to the peaking adjustment is outputted from the signal output section.

Abstract: A circuit block which comprises a non-linear capacitor with two different values of capacitance dependent on a value of a voltage of a resonant signal on the capacitor; a plurality of second capacitors each coupled to a respective switch to enable a said second capacitor to be switched in or out of parallel connection with the nonlinear capacitor; and a tuning control, coupled to the second capacitor switches, and sensing an amplitude of the resonant signal. The tuning control circuit is configured to control the second capacitor switches to successively switch the second capacitors in/out of parallel connection with the non-linear capacitor dependent on the amplitude of the resonant signal until the non-linear capacitor has substantially a single one of two different values, such that in a resonant circuit the circuit block then behaves as a fixed value capacitor.

Abstract: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generating circuit produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Abstract: A trimming circuit is provided. The trimming circuit had at least a trimming cell, and each of the at least trimming cell includes three current paths and a fuse. A first one of the current paths is interrupted when a second one of the current paths is uninterrupted, and the first one of the current paths is uninterrupted when the second one of the current paths is interrupted. When a trimming control signal is at an enable state, a third one of the current paths is uninterrupted, such that the fuse is blown. Based on the status of the fuse, the trimming circuit is capable of trimming an output voltage or an output current of an electric apparatus.

Abstract: A method for automatic gain control comprising the steps of measuring a signal using compressed sensing to produce a sequence of blocks of measurements, applying a gain to one of the blocks of measurements, adjusting the gain based upon a deviation of a saturation rate of the one of the blocks of measurements from a predetermined nonzero saturation rate and applying the adjusted gain to a second of the blocks of measurements. Alternatively, a method for automatic gain control comprising the steps of applying a gain to a signal, computing a saturation rate of the signal and adjusting the gain based upon a difference between the saturation rate of the signal and a predetermined nonzero saturation rate.

Abstract: An embodiment of regulation and shaping circuit includes a first input terminal for receiving a first input signal with a first frequency; a second input terminal for receiving a second input signal with a second frequency higher than the first frequency; a first circuital branch coupled to the first input terminal and, through first coupling means active at the first frequency, to an output terminal for providing an output signal; a second circuital branch coupled to the second input terminal and to the output terminal, wherein said second circuital branch comprises a negative feedback circuital loop adapted to control the output signal according to the second input signal.

Abstract: A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to generate an internal voltage having a level corresponding to the signal delay characteristic.

Abstract: An output circuit (12) converts a pair of current signals supplied to a pair of common nodes (NCa and NCb) into a pair of voltage signals (VOa and VOb). In each of input buffer circuits (11, 11, . . . ), a constant current generation section (101) generates, in an output mode, a pair of constant currents in a pair of current paths going from a pair of intermediate nodes (NMa and NMb) to a reference node (VDD1), and stops the generation of the pair of constant currents in a cutoff mode. A voltage-to-current conversion section (102) generates, in the output mode, a pair of input currents corresponding to a pair of input signals (Sa and Sb) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to a reference node (GND) to thereby generate a pair of current signals (Ia and Ib) in a pair of current paths going from the pair of intermediate nodes (NMa and NMb) to the pair of common nodes (NCa and NCb), and stops the generation of the pair of input currents in the cutoff mode.

Abstract: The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor.

Abstract: A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

Abstract: A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.

Abstract: To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.

Abstract: Power consumption is increased in an interface circuit having a signal processing function for waveform shaping due to influence of a circuit added for waveform shaping. Also, since a plurality of boards are connected to a backplane in a system, they are not exchanged in accordance with distances while there are boards being far or near are mixed, but a common board is used. Thus, it is necessary to prepare a configuration of an interface circuit meeting the longest transfer distance. An interface circuit disabling a part of or all of operations of a waveform shaping circuit is provided. Accordingly, in accordance with transfer distances, switching of operation ranges of waveform shaping circuit inside the interface circuit is possible, and operation ranges of the waveform shaping circuit can be limited, and power consumption of the interface circuit, an LSI including the interface circuit, and a server device can be reduced.

Abstract: An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.

Abstract: A signal processing circuit includes a waveform shaping section that applies a first gain to an input signal and generates a first signal when an absolute value of a level of the input signal falls within a first input range from a first level to a second level, a variable gain section that adjusts an amplitude of the first signal and amplifies the first signal by a gain to generate an output signal, and a control section that reduces the gain of the variable gain section so that the output signal is prevented from occurrence of clipping when the amplitude of the first signal falls within a second input range. The second input range includes a range of the level of the first signal output from the waveform shaping section corresponding to the first input range of the input signal.