Abstract: A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the peak signal according to time detection position; a complex filter section limiting the weighted peak signal within a band of the input signal; a filter coefficient calculation section calculating filter coefficients of the complex filter section; a delay adjustment section delaying another of the branched input signals by a time period required for calculating the band-limited peak signal; and a subtraction section subtracting the band-limited peak signal from the other of the branched input signals subjected to delay.

Abstract: A single ended to a differential signal converter. The single ended signal is passed through a high pass filter to block DC components. A positive and a negative version of the filtered signal are used collectively as the differential output of the converter. To allow accurate measurements on the input signal without waiting for the output of the high pass filter to settle, the differential outputs are offset by a dynamically generated signal representative of the midpoint of the filtered signal. That offset is generated by capturing a value representing the midpoint when a signal is first applied. This captured value is allowed to change with a time constant matching a time constant of the high pass filter. The converter may be used to connect a test instrument to a unit under test that generates test signals in a format that the test instrument is not specifically configured to measure.

Abstract: A semiconductor device includes a high voltage generator for generating a high voltage by raising a power source voltage, a transfer circuit for transferring the high voltage to an internal circuit in response to a transfer signal, and a first discharge circuit for discharging the high voltage of an output node of the high voltage generator or the high voltage of an input node or output node of the transfer circuit when the power source voltage drops.

Abstract: An internal voltage generation method includes the steps of: setting first to third sections by using a reference voltage; determining to which section an internal voltage level corresponds, among the first to third sections; and generating the internal voltage by controlling a voltage pumping amount according to a section corresponding to the internal voltage level.

Abstract: A signal converter equipped with an overvoltage protection mechanism includes a pulse width modulation unit, a timing processing unit, an overvoltage detection unit, a pulse width control unit and a multi-level conversion unit. The pulse width modulation unit converts an analog signal into a pulse signal. The timing processing unit converts the pulse signal into a digital signal and outputs the digital signal to the overvoltage detection unit. When the digital signal is higher than the maximum limitation or less than the minimum limitation, the overvoltage detection unit outputs an over-threshold signal to the pulse width control unit to allow the pulse width modulation unit to perform feedback adjustment and prevent the multilevel conversion unit connected to the timing processing unit from causing burnout of downstream circuits because the multilevel conversion unit outputs maximum power intensity of signal over a long time.

Abstract: The delay circuit, such as a clock circuit, of an integrated circuit operates with tolerance of variation in temperature. For example, the delay circuit has a temperature dependent current generator that has an adjustable temperature coefficient, such that a range of temperature coefficients is selectable at a particular current output. Also, the clock circuit of an integrated circuit operates with multiple versions of a current that controls a discharging rate and/or a charging rate between reference signals of timing circuitry.

Abstract: Methods and apparatus for lowering the capacitance of an interconnect, are disclosed. An example apparatus may include an interconnect formed in at least one integrated circuit and configured to pass a signal through at least a portion of the at least one integrated circuit. The apparatus may include a transmitter to operate at a first voltage and a second voltage, and to output to an end node of the interconnect a reduced swing signal ranging from the first voltage to a third voltage. The third voltage may be between the first and second voltages, and the reduced swing signal may operate to reduce a capacitance of the interconnect when compared to operating the transmitter at the second voltage. Additional apparatus and methods are disclosed.

Abstract: A communication circuit facilitating communication between a first equipment and a second equipment including a conversion circuit, an input port, an output port, and a communication port is disclosed. The conversion circuit converts an input signal to a first intermediate signal, and converts a second intermediate signal to an output signal. The input port inputs the input signal to the first conversion circuit. The output port outputs the output signal to the control unit. The communication port inputs the second intermediate signal to the conversion circuit, and outputs the first intermediate signal to the second equipment. A voltage of the first intermediate signal is determined based on a voltage of a power source if the first intermediate signal is logic high, and a voltage of the second intermediate signal is determined based on the voltage of the power source if the second intermediate signal is logic high.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC.

Abstract: Apparatus and methods are provided for calibrating and operating a receiver circuit. An exemplary method comprises the steps of applying a first voltage offset to a first input of an amplifier circuit, generating an output signal at an output of the amplifier circuit based on the first voltage offset and a second voltage offset at a second input of the amplifier circuit, adjusting the second voltage offset based on the output signal, and maintaining the second voltage offset at a constant voltage when the output signal is indicative of the second voltage offset cancelling the first voltage offset.

Abstract: Electronic component protection power supply clamp circuits comprising a plurality of p-type channel metal-oxide-semiconductor (PMOS) and n-type channel metal-oxide-semiconductor (NMOS) transistors are described. These clamp circuits use a feedback latching circuit to retain an electrostatic discharge (ESD)-triggered state and efficiently conduct ESD current that has been diverted into the power supply, in order to dissipate ESD energy. The feedback latching circuit also maintains a clamp transistor in its off state if the clamp circuit powers up untriggered, thus enhancing the clamp circuit's immunity to noise during normal operation. Passive resistance initialization of key nodes to an untriggered state, as well as passive resistance gate input loading of a large ESD clamping transistor, further enhances the clamp circuit's immunity to false triggering.

Abstract: Described embodiments provide for a regulated voltage supply to a Universal Serial Bus (USB) system. The regulator comprises a pass device that might be coupled to a host device providing a bus voltage. An integrated USB physical layer (PHY) is coupled to the pass device through a control voltage signal pin. A regulation circuit is coupled to the integrated USB PHY, and the regulation circuit supplies about 3.3V from the bus voltage.

Abstract: According to embodiments of the present invention, a circuit arrangement is provided.

Abstract: An amplitude-stabilized second-order predistortion circuit includes a main cell having a differential input for receiving a differential input voltage, a differential output for providing a differential output voltage, and a load control input for receiving a load control voltage; a replica cell having a differential input for receiving a differential level of peak input voltage, a differential peak output voltage, and a load control input; and a control circuit coupled to the differential output of the replica cell and driving the load control inputs of the main cell and the replica cell. The main cell and the replica cell are multiplier cells each having a variable load. The control circuit includes a first amplifier for generating a single-ended peak signal and a second amplifier for generating the load control voltage from the difference between the replica cell single-ended peak output signal and a single-ended peak reference signal.

Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.

Abstract: An integrated circuit device comprising at least one calibration module for calibrating an impedance of at least one on-die interconnect line driver in order to adaptively match an impedance between the at least one on-die interconnect line driver and at least one on-die interconnect line conjugated thereto. The at least one calibration module is arranged to receive an indication of an output signal of the at least one line driver, compare the received indication of an output signal to a reference signal and detect a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, and upon detection of a presence or an absence of a voltage overshoot of the output signal of the at least one line driver, cause the adjustment of power supply of the at least one line driver, to be decreased or increased correspondingly.

Abstract: A second driver is provided in addition to a first driver outputting an output signal in accordance with a voltage of an input signal. When the output signal changes from a first voltage level to a second voltage level in accordance with a voltage change of the input signal, a control part controls the second driver to assist the signal change during a period from a change start time until the output signal exceeds a third voltage level. The control part controls the second driver to suppress the signal change during a period from the time when the output signal exceeds the third voltage level until it reaches the second voltage level.

Abstract: According to one embodiment, a semiconductor switch includes a voltage generator, a driver, a switch section, and a power supply controller. The voltage generator is configured to generate a first potential and a negative second potential. The first potential is higher than a power supply voltage supplied to a power supply terminal. The driver is connected to an output of the voltage generator and is configured to output the first potential in response to input of high level and to output the second potential in response to input of low level. The switch section is configured to switch connection between terminals in response to an output of the driver. The power supply controller is configured to control the output of the voltage generator.

Abstract: A power control circuit includes a voltage output terminal, a control chip, a converter, and a comparator. A voltage input pin of the control chip is connected to a first power source. A voltage pin of the converter is connected to a second power source. A pulse input pin of the converter is connected to a pulse output pin of the control chip. An output pin of the converter is connected to the voltage output terminal. An inverting input terminal of a comparator is connected to a voltage output pin of the control chip. A non-inverting input terminal of the comparator is connected to the second power source through a first resistor and grounded through a second resistor. An output terminal of the comparator is connected to a detecting pin of the control chip and connected to the non-inverting input terminal of the comparator through a third resistor.

Abstract: In one embodiment a signal conversion circuit includes; first hysteresis comparator configured to receive a differential signal having first and second input signal components, to compare in magnitude between voltages of the first and second input signal components, and to output the comparison result as a first output signal; a second hysteresis comparator configured to receive the first and second input signal components, to compare in magnitude between the voltages of the first and second input signal components, and to output the comparison result as a second output signal that is an inversion signal of the first output signal; and a conversion buffer configured to convert the first and second output signals into a single-end signal.

Abstract: Differential signal detection circuitry with an integrated reference voltage. The reference voltage is added as an offset to the output voltage, and its integration ensures that variations in the reference voltage closely track variations in the signal. Accordingly, the detection threshold for the signal being detected remains more consistent over variations in the circuit manufacturing process, power supply voltage and operating temperature.

Abstract: Systems and methods are provided for converting analog data to digital data that can include a discharge capacitor coupled to a voltage source. The voltage source supplies an initial data charge to the discharge capacitor; an amplifier coupled to the discharge capacitor; a divider circuit coupled to the amplifier; and a comparator coupled to the amplifier and the divider circuit. The divider circuit includes a first capacitor, a second capacitor, and a switch that is operated to alternately divide a remaining charge Q by 2N using the first and second capacitors until the remaining data charge Qin at the amplifier is below a threshold value in the process of converting analog data to digital data.

Abstract: The disclosure relates to a countermeasure method in an electronic microcircuit, comprising successive process phases executed by a circuit of the microcircuit, and adjusting a power supply voltage between power supply and ground terminals of the circuit, as a function of a random value generated for the process phase, at each process phase executed by the circuit.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: A differential amplifier generates an offset correction signal based on a rotation detection signal from a rotation detector apparatus and an offset signal. A comparator compares the offset correction signal with a threshold voltage, and outputs a binarized signal representing the comparison result. An average value signal generator circuit generates an average value signal representing the average value of the offset correction signal. The offset signal generator circuit generates the offset signal so that the signal voltage of the average value signal has a voltage value between a threshold voltage and a threshold voltage.

Abstract: A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.

Abstract: A source-measure unit (SMU) may be implemented with respective digital control loops for output voltage and output current. The digital control loop associated with the output that is being regulated may be the setpoint control loop while the digital control loop associated with the other output may be the compliance control loop. The digital loop controller may switch between the setpoint control loop and the compliance control loop without generating a mode-change glitch, by maintaining a single integrator. The compliance methods may differ in how and when the decision is made to select which of the measured signals provides the error signal to the integrator. Thus, there may be no issue with integrator wind-up, which might be the case if there were two complete control loops operating continuously.

Abstract: Provided are a trimming circuit which does not need a dedicated terminal to which a current for cutting a fuse is input, and also a semiconductor device including the trimming circuit. The trimming circuit includes: an input terminal connected to a pad which is an external terminal of an internal circuit; a fuse provided between a power supply terminal and an output terminal; and a diode provided between the input terminal and the output terminal. The trimming circuit performs trimming by applying, to the pad, such a voltage that the diode is biased in the forward direction.

Abstract: A level control circuit that generates output signal for level control includes: a control information storage that stores control information corresponding to a signal level, a control information circuit that outputs the output signal for level control corresponding to the signal level of a first input signal based on the control information stored in the control information storage; and an information update circuit that updates the control information of the control information storage according to the signal level of a second input signal.

Abstract: A switch controller is provided that uses one or more capacitors to generate a slow turn on/slow turn off switch control signals to suppress audible switching noise in an audio switch. In some embodiments, an analog inverter and a capacitor are used to generate the switch control signals, while in other embodiments two capacitors are used to generate the switch control signals. To conserve power between switching states, routing logic is provided that ties the switch control signals to respective voltage rails and disables selected portions of the switch controller.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: A method for converting a sampled analog signal into digital is provided. An input signal is sampled at a sampling instant to generate a sample voltage. A first current is then applied to a node to change a voltage on the node, and a first interval to change the voltage on the node to a reference voltage from the sample voltage using the first current is determined. A second current is then applied to the node to change a voltage on the node prior to a subsequent sampling instant, and a determination of a second interval to change the voltage on the node to the reference voltage from the sample voltage using the second current is made.

Abstract: Methods and circuitry for lowering the capacitance of interconnects, particularly Through Wafer Interconnects (TWIs), using signal level adjustment are disclosed. Embodiments of the invention seek to bias the midpoint voltage level of the signals on the TWIs towards inversion, where at high frequencies capacitance is at its minimum. In one embodiment, reduced swing signals are used for the data states transmitted across the TWIs, in which the reduced swing signals use a midpoint voltage level tending to bias the TWI capacitance towards inversion. In another embodiment, signals are AC coupled to the TWI where they are referenced to an explicit bias voltage directly connected to the TWI. This allows signals to propagate through the TWI while the TWI is biased towards inversion. In a third embodiment, the potential of the substrate is explicitly lowered with respect to the TWI potential.

Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.

Abstract: An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit generates the first enable signal and a second enable signal in response to the first detection signal and the second detection signal. The voltage pumping unit generates the internal voltage in response to the second enable signal.

Abstract: According to one embodiment, a circuit comprises a first resistor configured to have one end to which a first voltage is input and the other end which outputs a second voltage and a first amplifier configured to have an inverting input connected to the other end of the first resistor and a noninverting input to which a third voltage is input. The circuit further comprises a first capacitor configured to have one end to which an output of the first amplifier is input and the other end to which the other end of the first resistor is connected. An output of the first amplifier or an output of a second amplifier connected to the other end of the first resistor is a fourth voltage. In the circuit, the first resistor and a mirror capacitance composed of the first capacitor and the first amplifier constitute a low-pass filter.

Abstract: A sensor control circuit according to the present embodiment is provided with an autonomous-oscillation loop part configured to generate a sensor-modulated signal having a carrier signal and an alternating signal output by a sensor and superposed on the carrier signal having the same frequency as the alternating signal, and an amplitude adjustment loop part configured to generate a control signal for amplitude adjustment of the carrier signal, by digital processing of a result of comparison between the carrier signal and a reference voltage level. The autonomous-oscillation loop part includes an amplifier configured to perform amplitude adjustment of the carrier signal, and a switched capacitor having a switch configured to be switched by the control signal, the switched capacitor configured to be capable of controlling a gain of the amplifier in accordance with a switching frequency of the switch.

Abstract: A signal shaping circuit that shapes a drive signal and includes a main-signal amplifying circuit that amplifies the drive signal; a preemphasis generating circuit that symmetrically emphasizes a rising portion and a falling portion of the drive signal; a current source that is provided in the main-signal amplifying circuit; and a condenser that couples the main-signal amplifying circuit and the preemphasis generating circuit.

Abstract: A method and apparatus to regulate voltage used to power an ASIC comprising an ASIC having a signal source and a modulator. The modulator establishes a characteristic of a signal created by the signal source to indicate a voltage level to be used to power the ASIC. The signal is communicated to a voltage regulator to apply an optimal voltage to the ASIC.

Abstract: An apparatus, a method, and a system are provided to calibrate an offset in an amplifier. The apparatus can include an amplifier, a voltage control unit, a comparator, and a processing unit. The amplifier can have four terminals: a positive differential input (VIN+), a negative differential input (VIN?), a positive differential output (VOUT+), and a negative differential output (VOUT?). The voltage control unit can be configured to adjust a first voltage on VOUT+ and a second voltage on VOUT?. The comparator can be configured to compare the first voltage on VOUT+ to the second voltage on VOUT? when VIN+ and VIN? are coupled to a common voltage. Further, the processing unit can be configured to provide a control signal to the voltage control unit based on the comparison of the first and second voltages on VOUT+ and VOUT?, respectively.

Abstract: The common-mode voltage of a switched-capacitor system is controlled by determining a current common-mode voltage of the switched-capacitor system, converting (in a flow-through conduction cell) the difference between the current common-mode voltage and a desired common-mode voltage into a resultant current, and reinjecting this resultant current into the switched-capacitor system via a resistive path.

Abstract: A semiconductor device includes an internal circuit to perform a predetermined function at a plurality of different supply power voltages, a power supply voltage region detector to detect a supply power voltage to output a detection signal, a latch to store the signal output from the power supply voltage region detector and output the stored signal as a power supply voltage region signal, and a reset circuit to generate a reset signal to perform a predetermined reset operation on the internal circuit. The latch stores the output signal from the power supply voltage region detector just after the reset operation for the internal circuit is released, and the internal circuit changes an internal setting according to the power supply voltage region signal output from the latch.

Abstract: An apparatus comprises an integrated circuit (IC) and a resistor external to the IC. The IC includes a current output digital-to-analog converter (IDAC) circuit configured to provide an adjustable specified current to a resistor external to the apparatus, a voltage sensing circuit configured to sense the voltage of the external resistor, and an automatic gain control (AGC) circuit configured to receive threshold information using the adjustable specified current.

Abstract: A dynamic voltage scaling system for a packet-based data communication transceiver includes a constant voltage supply, a variable voltage supply, and a voltage control unit. The constant voltage supply is configured to supply a constant voltage to at least one parameter-independent function of the transceiver, and the variable voltage supply is configured to supply a variable voltage in accordance with a control signal to at least one parameter-dependent function of the transceiver. Parameter-independent transceiver functions perform operations independent of a predetermined parameter and parameter-dependent transceiver functions perform operations dependent on the predetermined parameter The voltage control unit is configured to generate the control signal based on information provided by at least one parameter-independent transceiver function about the predetermined parameter.

Abstract: An image driver includes an adjustment signal module, a multiplexer, and a conversion module. The adjustment module generates at least a first adjustment signal and a second adjustment signal. The multiplexer is connected to the adjustment signal module and selectively outputs one of the adjustment signals. The conversion module includes a plurality of conversion units, wherein each of the conversion units receives the selected adjustment signal and generates a driving signal based on the adjustment signal received.

Abstract: A stimulating medical device, comprising a plurality of electrodes, and a current source and a current sink connected to each one of the electrodes. The medical device also comprises a calibration arrangement configured to compare the current provided by a selected one of the current sources to the current sunk by a selected one of the current sinks, and configured to adjust an operational parameter of at least one of the source and sink based on said comparison such that the current provided by the selected current source is substantially the same as the current sunk by the current sink.

Abstract: An integrated circuit supports auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Abstract: An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another.

Abstract: A circuit and a method for controlling multi-channel power are disclosed. The method includes: according to a channel selection signal in the previous clock cycle, select one channel signal from the received at least one channel signal in the previous clock cycle; according to an amplification factor control signal in the previous clock cycle, amplify the selected one channel signal to acquire a first signal; perform A/D conversion on the first signal to acquire a second signal; and according to the second signal, generate an amplification factor control signal in the next clock cycle, so that according to the amplification multiple control signal in the next clock cycle, amplify the selected one channel signal in the next clock cycle when the next clock cycle comes. The scheme can be used to detect the multi-channel optical power and its circuit implementation is simple.

Abstract: An integrated circuit includes: a circuit pin; a detecting circuit coupled to the circuit pin, and arranged to detect a signal level value of the circuit pin when the integrated circuit operates in a first operational mode; a storage circuit coupled to the detecting circuit, and arranged to store the signal level value; and a controlling circuit coupled to the storage circuit, and arranged to set a voltage level of the circuit pin according the signal level value when a processing circuit of the integrated circuit operates in a second operational mode.