Abstract: A method and apparatus are directed to emulating an emitter follower with a small PNP transistor that is arranged in a PNP multiplier configuration. The PNP multiplier includes a PNP emitter follower and a current mirror. The PNP follower is coupled between the input and the output. A current mirror is coupled to the collector of the PNP follower such that mirror produces a current that is a scaled version of the collector current from the PNP follower. The current mirror is arranged to scale the PNP collector current by a factor of N. The effective output current from the PNP multiplier circuit corresponds to &bgr;·IIN·(N+1), where &bgr; corresponds to the large signal forward gain of the PNP follower. By multiplying the output current by a scaling factor, the effective forward gain of the PNP transistor is increased while utilizing a small geometry PNP device.

Abstract: A circuit for measuring the power supplied by a voltage source supplying a sine-shaped voltage by averaging the multiplication of the instantaneous value of the current supplied by the voltage source and a square-wave that is synchronized with the sine-shaped voltage, and by multiplying the result by the actual value of the voltage.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

Abstract: A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated based on matching an internal impedance generated by transistors with an impedance of the external impedance element, and then the reference impedance code can be shifted to generate new impedance codes according to impedance requirements of various different circuits that require compensation. Use of the single external impedance element for compensation of multiple circuits reduces motherboard and packaging costs. Chip area is also conserved since simpler compensation circuits can be used.

Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second operational current, which is smaller than the first operational current, a first power source regulator for stepping down a predefined output power supply voltage from an input power supply voltage and having a current supply ability corresponding to the first operational current of the internal circuit and a second power source gulator having a current supply ability corresponding to the second operational current are combined in order to, under the control of a power supply control unit, operate the first step-down type regulator in response to a first control signal instructing the first operation mode in the internal circuit and to operate the second step-down type regulator in response to a second control signal instructing the second operation mode.

Abstract: A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer.

Abstract: A semiconductor device includes an input and output section, an internal circuit section, and a capacitance section. A signal is inputted to or outputted from the input and output section. The internal circuit section receives the signal inputted to the input and output section or outputs the signal via the input and output section. The capacitance section includes a capacitance connected to the input and output section. The signal is outputted on a signal transmitting line from the internal circuit section to the input and output section. The capacitance section is provided on a conductive line different from the signal transmitting line.

Abstract: The present invention is related to an apparatus comprising an active circuit, said circuit synthesising a self-induction. The invention is characterised in that said active circuit comprises only one Operational Amplifier.

Abstract: A relatively compact trimming circuit for hypothetically breaking a fuse includes a resistance bypass circuit connected to a node between a resistor and a fuse. The bypass circuit selectively performs ordinary breakage and hypothetical breakage of the fuse in accordance with a control signal and a data signal. An output changeover circuit connected to the node generates a first output signal in accordance with a state of the fuse during the ordinary breakage. The output changeover circuit generates a second output signal in accordance with the data signal during the hypothetical breakage.

Abstract: An importance matching circuit for a semiconductor memory device includes an impedance detector for generating a voltage divided by a medium resistance value between a maximum resistance value and a minimum resistance value and an external resistance during a predetermined cycle as a first comparison voltage, and for generating a voltage divided by a resistance value varied in response to a counting output signal and the external resistance after the predetermined cycle as the first comparison voltage; a first comparator for comparing the first comparison voltage with a reference voltage to generate a first comparing output signal; a second comparator for comparing the first comparison voltage with the reference voltage to generate a second comparing output signal; a counter for generating the counting output signal in response to the first comparing output signal; and a plurality of output drivers for establishing an initial resistance value in each of the output drivers in response to the second comparing o

Abstract: A semiconductor device of the invention comprises: an external terminal; an internal circuit connected to the external terminal; a MOS transistor whose gate terminal or common terminal of the drain and source is connected to the external terminal; and a bonding pad for applying a predetermined voltage to a terminal which is not connected to the external terminal of the MOS transistor.

Abstract: A method and circuit are provided to perform current-to-voltage conversions. The circuit is operational in one linear mode based on channel-length-modulation effects in the saturation region and two non-linear modes based on a current operation overrunning the saturation region and a logarithmic function of drain current versus gate-to-source voltage, respectively. An adaptive process is provided to set-up the quiescent point of the circuit. The conversion gain is variable with respect to the conversion mode, the current range, and the length of the converting transistor.

Abstract: A variable capacitance circuit enables electrostatic capacity to be adjusted as a trimmer capacitor, and that enables a temperature characteristic to be set variably. An input voltage is made to lead by a phase angle of 90° due to a differentiating circuit, before being amplified by an in phase amplifier, thus a current with phase angle of 90° shifted is obtained in such a manner as to take out the output while passing through a resistor. Gain and/or an output resistance of the amplifier are made to set variable. If a thermistor is combined with the circuit as a resistance of the differentiating circuit, temperature coefficient can be made to set variable.

Abstract: A semiconductor device includes an input and output section, an internal circuit section, and a capacitance section. A signal is inputted to or outputted from the input and output section. The internal circuit section receives the signal inputted to the input and output section or outputs the signal via the input and output section. The capacitance section includes a capacitance connected to the input and output section. The signal is outputted on a signal transmitting line from the internal circuit section to the input and output section. The capacitance section is provided on a conductive line different from the signal transmitting line.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: A signal processor circuit which receives an input signal and two control words and is programmable to vary the level and the output voltage range of the output signal is provided. The signal processor includes a converter circuit and a level circuit which provide the output circuit with intermediate signals based on input control signals, e.g., input digital words. The output circuit receives an additional control signal and the intermediate signals and is programmable to modify the output voltage range and level of the output signal based on the additional control signal, e.g., a digital word.

Abstract: A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.

Abstract: A connecting arrangement includes a number of NMOS transistors that can be activated or deactivated by means of a control voltage, serving as a control signal, connected to the gate terminals of transistors, to be able to form a circuit connected between two conductors, the circuit presenting resistive properties. The circuit is equipped with a signal receiver and it is regulated by an analog control voltage. The control voltage is connectable to one or several of a number of available control connections. Each control connection is connected to the gate terminals of a group of transistors where the drain and source terminals are connected to the conductors. The control voltage is selected so that the operating point of the transistors will be within, or at least close to, the region where the transistor presents resistive properties.

Abstract: An integrated circuit includes a self-calibrating resistor circuit comprising a resistor string, a comparator, a state machine, a reference voltage source, and a reference current source. The current source typically comprises a voltage reference, typically a bandgap reference, and a temperature-independent resistor having a value REXT. In operation, a reference current IREF flows through the resistor string. During a calibration period, the voltage across the string is compared to the bandgap reference voltage, VBG, by the comparator, which controls the state of the state machine. The outputs of the state machine turn on or off the resistors in the string until the voltage across the string, VR, is approximately equal to the reference voltage. The resistance of the resistor string is then equal to RBG=VBG/IREF, which is proportional to REXT, and thus is typically independent of process and temperature.

Abstract: An object is to reduce the offset voltage between the input and output in a wide range of output current with a simple circuit configuration. Transistors (Q1), (Q2) and (Q3) have a size ratio of m:n:1, transistors (Q6) and (Q7) have a size ratio of 1:p, and transistors (Q4) and (Q5) have a size ratio of {(m+n+1)/p:}). Accordingly a current which is (m+n+1) times the current flowing in the transistor (Q3) is supplied to the emitter electrodes of the transistors (Q1) and (Q2). Since the ratio between the currents flowing in the transistors (Q1) and (Q2) is the same as their size ratio m:n, the emitter-base voltages are equal between the transistors (Q1) and (Q2). As a result, the offset voltage between the voltage signal inputted to the input signal line (IN) and the voltage signal outputted from the output signal line (OUT) can be suppressed in a wide range of output current.

Abstract: A variable capacitance circuit enables electrostatic capacity to be adjusted as a trimmer capacitor, and that enables a temperature characteristic to be set variably. An input voltage is made to lead by a phase angle of 90° due to a differentiating circuit, before being amplified by an in phase amplifier, thus a current with phase angle of 90° shifted is obtained in such a manner as to take out the output while passing through a resistor. Gain and/or an output resistance of the amplifier are made to set variable. If a thermistor is combined with the circuit as a resistance of the differentiating circuit, temperature coefficient can be made to set variable.

Abstract: A fuse trim circuit includes: a fuse 40; and a logic gate 55 having a first input coupled to the fuse 40 and a second input coupled to a logic code such that the logic code bypasses the fuse 40 to avoid prestressing the fuse 40.

Abstract: A cell incorporated in an integrated circuit and having an input node behaves as a capacitor vis-a-vis the relation between the current entering the input node and the pseudo-voltage at the input node. The cell comprises a variable pseudo-conductance, including a control terminal, connected between the input node and a node, the pseudo-voltage of which is zero (pseudo-ground) and a differentiator having an input connected to the input node and an output connected to the control terminal of the variable pseudo-conductance to control them in accordance with the voltage at the input node. Applications include a photo-sensitive array forming an artificial retina.

Abstract: A transmitter system having an adjustable monolithic frequency stabilization and tuning internal capacitor circuit. The transmitter system has a transmitter for generating and transmitting a transmitter oscillator frequency signal. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. A variable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The variable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.

Abstract: A method for manufacturing a probabilistic switch using multiplicative noise, which can be used in a probabilistic computer is disclosed. The probabilistic switch, in which the probability varies with the initial condition and multiplicative noise intensity, is realized by applying the multiplicative noise whose intensity varies with the state of a nonlinear device to the nonlinear device. When the switch is applied to a probabilistic computer, a complicated problem can be solved rapidly in shorter time.

Abstract: A loading device for use in a tester for testing a semiconductor integrated circuit device (DUT) includes a programmable voltage source for providing a selected voltage at an output terminal thereof and multiple resistive elements each having at least a first state, in which the resistive element is conductive, and a second state, in which the resistive element is substantially non-conductive. The resistive elements are connected as a two-terminal network between the output terminal of the programmable voltage source and a tester pin for connection to a pin of the DUT. A selection device selects the state of each resistive element, whereby the resistance between the output terminal of the programmable voltage source and the tester pin can be selectively varied.

Abstract: Signal generating apparatus comprises a linear series of Hall-effect switches (44) arranged as a plurality of linear arrays in discrete probes (46a, 46b . . . 46n) which are butted end to end. Each switch is closed when in proximity of an actuating magnet (40) movable along the series of switches. In each array a resistance chain (66) is linked at intervals to the switches. Movement of the magnet along an array thereby gives a progressively changing voltage on an output line (5) from the resistance chain as a cumulative signal indicating the position of the magnet. When the magnet moves from one array to the succeeding array after generating a maximum cumulative signal from said one array, that signal is maintained by a latch connection (56) between the two arrays. A cumulative signal representing the magnet position relative to the complete series of switches can thus be generated.

Abstract: A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Abstract: Disclosed is a variable gain semiconductor circuit enjoying a low insertion loss, good distortion characteristic, and large variable gain range. The variable gain semiconductor circuit comprises: a first kind of variable gain circuit that inputs an input signal and changes a gain on the basis of a first control signal; a second kind of variable gain circuit, installed in a stage succeeding the first kind of variable gain circuit, for changing a gain on the basis of a second control signal; and a control signal producing unit for producing the first and second control signals using an attenuation value control signal. When the attenuation value control signal falls within one of two variation ranges instructing a large gain, the control signal producing unit produces the first and second control signals so that the first kind of variable gain circuit decreases a gain according to the variation of the attenuation value control signal, and the second kind of variable gain circuit produces a constant gain.

Abstract: A boost type equalizing circuit, being an equalizing circuit used in a signal reproducing circuit of memory device such as an optical disk drive and hard disk drive, and comprising boost units 4, 6, which is used for compensating distortion caused in reproduced signal of information recording medium, and compensating frequency characteristic of reproduced signal. The boost units 4, 6 are composed so that the numerator of the transfer function may have an even-number order term of fourth power or more of Laplace operator s. A boost equalizing circuit of excellent cut-off characteristic in high frequency range can be presented.

Abstract: Circuit blocks for integrating/differentiating input signals in the form of sampled currents include coupled current memories where the second current memory has a plurality of scaled outputs which feed switching arrangements. Resistors are provided in the current memories, the resistance of the resistors being equal to the "on" resistance of the switching arrangement multiplied by any multiplying factor applied to this output to which the switching arrangement is coupled.

Abstract: A weighted addition circuit contains a plurality of resistances, each of which is connected to a common output at one terminal and to different input voltages at the other terminal. The voltage at the common output terminal is a balance voltage of the input resistances. The common output terminal is connected to an amplifier having an odd number of stages of inverters and a feedback resistance connecting the output of the last inverter stage to the input of the first inverter stage. Grounded low pass capacitors and/or balance resistors are also be included in the amplifier to improve the stability of the circuit and prevent undesirable oscillation. Providing a circuit containing a balance voltage of the parallel-connected input resistances allows for precise weighted addition of any number of inputs while still maintaining a small and simple circuit structure.

Abstract: An apparatus for performing logic and leakage current tests on a logic circuit device under test (DUT) includes a local module for each terminal of the DUT. For performing logic test, each local module has a driver for supplying a logic signal input to the DUT terminal, a comparator for detecting the DUT output at the terminal, and a clamping circuit for limiting the voltage swing at the DUT terminal during the logic test. For performing a leakage current test, each local module includes a source for supplying a parametric signal to the DUT terminal. The voltage the parametric signal produces at the DUT terminal, as detected by the comparator, indicates the terminal's leakage current. The parametric signal source and the clamping circuit are connected to the DUT terminal through Schottky diodes. During a logic test the parametric signal source is isolated from the DUT terminal by reverse biasing the Schottky diodes linking the parametric signal source to the DUT terminal.

Abstract: A serial interface includes a first port capable of transmitting and receiving data in a serial fashion. A first p-channel transistor is coupled to the a first port. A first n-channel transistor is coupled to the a first port. A first control circuit is coupled to the first p-channel transistor for disabling the first p-channel transistor so that the first port can operate in a first serial data transfer mode wherein the first n-channel transistor operates in an open-drain fashion. A second port is capable of transmitting and receiving a clock signal which is used to control data transfer through the first port. A second p-channel transistor is coupled to the a second port. A second n-channel transistor is coupled to the a second port. A second control circuit is coupled to the second p-channel transistor for disabling the second p-channel transistor so that the second port can operate in the first serial data transfer mode wherein the second n-channel transistor operates in an open-drain fashion.

Abstract: The integrated circuit includes at least one conductance (6) which is adjustable by a digital control signal (17) which encodes steps in value for quantizing an exact value to within a fixed relative accuracy .DELTA.p. The conductance (6) includes elementary conductances which each define a step in value such that each elementary conductance is dimensioned so that a single level in value of the conductance (6) corresponds to two successive levels of the value of the digital control signal (17). If the result from the first of the two levels of value of the digital control signal (17) is a value which is lower, or respectively higher, than the exact value, the corresponding elementary conductance is enabled, or respectively disabled. Accordingly, the adjusted total value of the conductance (6) is equal to the exact value to within the same relative accuracy .DELTA.p, without oscillating between two values straddling this exact value.

Abstract: Electronic circuit comprising at least one first second-generation current conveyer consisting of a mixed translinear loop and a plurality of current mirrors. The conveyer includes a high impedance reference port, an input port with an intrinsic resistance equivalent to the output resistance of the equivalent Thevenin generator, seen by the input port and polarized by a polarization current, an output port with a current corresponding to that of the input port and a current controller for controlling the intensity of the polarization current to determine the ohmic value of the intrinsic resistance. The invention's reference and output ports are directly connected to one another.

Abstract: In an integrated circuit an effective admittance is adjusted. The adjustment uses an admittance element in combination with a current multiplier circuit. The current multiplier circuit provides current I.sub.p proportional to a reference current I.sub.ref through the admittance element: I.sub.p =.alpha.I.sub.ref. The current I.sub.p flows through a terminal in parallel with the current I.sub.ref through the admittance element. This reduces the effective admittance to ground seen at the terminal. The proportionality coefficient .alpha. is modulated using a control circuit which sets the coefficient .alpha. in a non-linear dependence (a+bM)/(c+dM), or P(M)/Q(M), where P and Q are polynomials, on a control signal M. In this way various electronic parameters which depend non-linearly on the effective admittance can be given a linear dependence on the control signal.

Abstract: There is disclosed a rectangular filter which has a simple configuration and is capable of producing an improved rectangular wave. An input step wave is differentiated by a differentiator circuit and amplified by a first amplifier. The output from the amplifier is inverted by an inverting amplifier having a gain of -1. The output from the first amplifier is integrated by an integrator circuit having a time constant equal to the time constant of the differentiator circuit. The output from the inverting amplifier and the output from the integrator circuit are summed up by an adding circuit. The input signal is faithfully reproduced at the output of the adding circuit. After a given time passes since the input signal has been applied, the capacitor of the integrator circuit is shorted out. In this way, a rectangular wave is obtained. There is also disclosed a filter amplifier comprising this rectangular filter and a gated integrator for integrating the output from the rectangular filter for a predetermined time.

Abstract: Automatic test equipment including a circuit to measure average current consumed by a device under test. The circuit operates during the execution of a test pattern which is not dedicated to measuring average current. The average current measuring circuit sets the measurement interval to account for a lag between the current drawn by the device under test and the current being measured.

Abstract: The voltage reference generator of the present invention includes a plurality of p-channel transistors configured to act as resistors. Switching transistors, responsive to input signals, are utilized to bypass the resistors when in the "on" state, and enable the resistor when in the "off" state. Thus, when enabled, the resistors become part of a total resistance value in a branch of a voltage divider circuit. A minimum amount of space is used on an integrated circuit because the switching transistors are of the same type as the transistors which are configured to act as resistors.

Abstract: Electronic circuitry for simulating the resistance characteristics of a variable resistance temperature sensing element includes a multiplier that multiplies the difference between a reference voltage and a desired value of a control voltage times the voltage across a precision resistor at the output of the circuitry. The multiplier product output signal is integrated and a voltage value of the integrator output controls the gate terminal of a field effect transistor. The drain and source terminals of the transistor are connected in series with the precision resistor. The combination of the current through the precision resistor and the transistor (or the voltage across the precision resistor), together with the voltage value of the control signal, controls the voltage input value to the integrator, which, in turn, controls the resulting resistance across the output terminals of the transistor.

Abstract: In a switched capacitor amplifier circuit of an offset cancellation type, a capacitor is arranged between a reverse input terminal of an operational-transconductance amplifier and a reference voltage. Only in an offset cancelling operation in which a first group of switches are on, the capacitor functions as a load of the amplifier. The capacitor hence does not exert any influence upon transfer of charge. With provision of the circuit, the phenomenon of oscillation is suppressed in the operation to cancel the offset voltage.

Abstract: An impedance matching circuit which includes an RC network placed at the end of the transmission line and which will absorb reflections. The values of the resistor and capacitor are selected such that the output voltage at the end of the transmission line is attenuated only during the duration of the reflected waves and the overall gain from the incident signal to the end of the transmission line is 1:1. The values of the resistor and capacitor selected are based upon the impedance mismatch and the length of the transmission line.

Abstract: A semiconductor emulation of a vacuum tube with one or more of the following characteristics: non-linear output, non-linear transfer, non-linear input, reverse transfer, and second harmonic generation. Also an emulator with a second output to emulate a phase splitter, a semiconductor emulator of a cathode follower, and a compressor emulating the effects of a power supply droop and screen grid behavior are disclosed.

Abstract: A series of squarer circuits each providing an ideal square law transfer character comprises at least one backward diode and a compensating resistor connected in series therewith. A second backward, diode can be included connected front to back with the one diode.

Abstract: Internal to the transistor, an additional, direct connection is made from the internal collector to the external collector of the transistor by a fixed shunt inductance. The external power supply V.sub.s is applied to the transistor collector through an adjustable external shunt element. The adjustable external shunt element allows the user to finetune the impedance matching circuit such that the transformation ratio of the output matching circuitry is minimized.

Abstract: A folder circuit maps an analog input voltage to an analog output voltage in accordance with a folding function having at least one folding point. The folder circuit includes a power supply node and at least one input differential stage. Each input differential stage has a first input node to which is applied the input voltage, a second input node to which is applied a first reference voltage corresponding to that stage's folding point, and two differential output nodes. A resistive network is connected between the power supply node and the two differential output nodes, and a current source draws a predefined current from each input differential stage. An output network generates an analog output voltage as a function of the highest voltages on the differential output nodes of all the stages of the folder circuit. A current injection circuit provides a level-shifting current to each input differential stage through the two differential output nodes.