Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: Memory modules and methods for fabricating and implementing memory modules wherein unique device parameters corresponding to specific memory devices on the memory modules are accessed from a database such that the device parameters may be implemented to improve system performance. The device parameters may include sizes, speeds, operating voltages, or timing parameters of the memory modules. Memory modules comprising a number of volatile memory devices may be fabricated. Device parameters corresponding to the specific memory devices on the memory module may be stored in a database and accessed during fabrication or during implementation of the memory modules in a system. System performance may be optimized by implementing the unique device parameters corresponding to the specific memory devices on the memory modules.

Abstract: A signal sampling apparatus for a DRAM memory comprises a phase delay circuit adapted for receiving a data signal and delaying the data signal by a predetermined time to generate a delay signal; and a sampling circuit for sampling the data signal according to the delay signal.

Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.

Abstract: Apparatus in accordance with at least one embodiment of the present invention includes a data storage cartridge and/or a receiver configured to receive the cartridge in facilitation of data transfer to and/or from the cartridge. The cartridge and the receiver each include respective connector portions configured to connect when the cartridge is inserted into the receiver. The cartridge and/or the receiver also include guide features configured to facilitate alignment of the connector portions for connection as the cartridge is inserted into the receiver.

Abstract: Described herein is a point-to-point memory communications architecture, having a point-to-point signal line set associated with each of a plurality of connectors or module positions. When the system is fully populated, there is a one-to-one correspondence between signal line sets and memory modules. In systems that are not fully populated, the system is configurable to use a plurality of the signal line sets for a single memory module.

Abstract: A semiconductor storage device including a first latch circuit for latching stored data and a storage cell part including a plurality of second latch circuits that operate with inverted logic from the first latch circuit and receives the stored data from the first latch circuit to output the received data using the second latch circuit selected in accordance with a selection signal.

Abstract: Circuit modules, systems and devices for controlling voltages across capacitors.

Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: A stacked memory is configured such that a ratio between data and ECC bits, a ratio between quantities of data layers and ECC layers, and a ratio between quantities of data activated mats and ECC activated mats are equal to each other. The memory chip has a greater quantity of mats than the quantity of stacked layers. The stacked memory is thus allowed to establish a desired ratio between the quantities of data bits and ECC bits.

Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Abstract: Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on an optical pick-up unit. Each device includes a serial interface, a device enable number (DEN) that differs from the DEN of each other device, and a plurality of registers, with at least one register being designated a device select register (DSR). The DSRs of the plurality of devices share a common address. The plurality of serial interfaces are collectively enabled and collectively disabled (e.g., via the SEN line). However, only one of the plurality of serial interfaces can be selected at one time, with the remaining of the plurality of serial interfaces being deselected. The serial interface of a device is selected when the DEN of the device is the same as the content of the DSR of the device, and deselected when the DEN of the device is not the same as the content of the DSR of the device.

Abstract: A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free running clock that may be passed serially through a subset of memory units in the architecture. Sending of data is delayed over the point to point links based on proximity of the memory units to the buffer chip to accommodate delay in the multidrop clock signal.

Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Abstract: Memory devices are described along with manufacturing methods. An embodiment of a memory device as described herein includes a bottom electrode, a thermal protect structure on the bottom electrode, and a multi-layer stack on the thermal protect structure. The thermal protect structure comprises a layer of thermal protect material, the thermal protect material having a thermal conductivity less than that of the bottom electrode material.

Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon including a plurality of high-speed bus interface pills arranged on said card for communicating with a plurality of high-speed busses. The high-speed bus interface pins associated with a single high-speed bus are located on one side of the card with respect to a midpoint of the length of the card, thus the pin assignments are defined such that the performance of the DIMM in a system is optimized for high frequency operation.

Abstract: One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Abstract: A system comprises a board, memory units that are arranged on the board, a control unit configured to control memory access to the memory units, at least one control/address bus configured to transmit control/address signals from the control unit to a first group of the memory units, and at least one clock bus configured to transmit a clock signal from the control unit to a second group of the semiconductor memory units. A length of the at least one control/address bus corresponds to the length of the at least one clock bus. The second group of memory units comprises fewer memory units than the first group of memory units.

Abstract: A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in the memory module when a capacitor of the memory module incurs an aggravated current leakage due to the temperature rise. Next, the control circuit adjusts the refresh rate in response to the temperature change signal and refreshes the memory module at the refresh rate.

Abstract: A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with a column address, which is defined only in the DDP mode, in a single chip mode; and a read operation control unit configured to output a bank read signal latched in an active bank in a read mode of the DDP, and to selectively activate a first address control signal and a second address control signal for activating a bank selected from the single chip or the DDP in response to the bank read signal.

Abstract: Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values corresponding to the specific memory devices on the memory module may be stored in a database and accessed during fabrication or during implementation of the memory modules in a system. System performance may be optimized by implementing the unique operating current values corresponding to the specific memory devices on the memory modules.

Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to the

Abstract: A programmable logic, a memory and a microcontroller. The memory is coupled to the programmable logic circuit via the microcontroller. The programmable logic circuit, the memory and the microcontroller are fabricated as a single integrated circuit.

Abstract: A memory chip suitable for use in a daisy chain of memory chips. The memory chip receives an address/command word on a first input, determines if the address command word is directed to the memory chip; if so, the memory chip accesses an array on the memory chip. If not, the memory chip re-drives the address/command word on a first output. Write data is received as part of the address/command word or from a first data bus port. A bus clock is received and is used to receive and transmit information on the first input, the first output, the first data bus port and the second data bus port. The memory chip is incorporated into a design structure that is embodied in a computer readable medium used for designing, manufacturing, or testing the memory chip.

Abstract: Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Abstract: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of the plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals.

Abstract: A rescue whistle, end surfaces of two ends of which are respectively concaved with a holding space, a circuit board main body at one end of a flash drive storage unit is positioned within one of the holding spaces, and a USB connector at another end of the flash drive storage unit protrudes outside the holding space. A whistle is connected to the other holding space, forming a sealed space, within which is deposited a strip of paper with health information on an individual written thereon. Accordingly, when an accident occurs, rescue workers can access the pieces of health information on the individual stored in the flash drive storage unit, or refer to the health information of the individual written on the strip of paper, thereby facilitating carrying out the most appropriate first aid and care.

Abstract: A memory card system is disclosed. The memory card system comprises at least one flash memory card and a module for holding the at least one memory card. The module comprises a plurality of supports. The supports include rails to guide the at least one memory card in place and a latch system for securing the at least one memory card to the module. The present invention provides a modular flash memory card expansion system using any standard Secure Digital card; the flash memory card can be any flash-based memory card, such as SD, Compact Flash (CF), MMC, Memory Stick or others.

Abstract: An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.

Abstract: A shunt activation signal is transmitted by an external control terminal through an external transmission interface to switch a flash memory controller in a shunt mode. The shunt activation signal of the external transmission interface can set up a switch as shunt. When the flash memory controller is defective due to errors or damage, the shunt mode enables the external control terminal to directly process data saving/retrieving to the flash memory chip or testing through the external transmission interface. Thus, the user need not purchase a new flash memory to replace the defective flash memory with the damaged flash memory controller.

Abstract: A memory card module includes a first circuit board, and a second circuit board. On one surface of the first circuit board, there are flash memories and a controller. The second circuit board is installed at one end of the first circuit board and is electrically connected with the first circuit board so as to form a transmitting interface port. On a first surface of the second circuit board, there are a plurality of interface connecting points. On a second surface of the second circuit board, part of the second surface is hollowed out. A space formed between the hollowed out area and the corresponding first circuit board increases the area for circuit layouts and the mounting components for the first circuit board. Therefore, quantity of accommodated memory components may be increased so as to increase the total storage capacity of the memory card under limitation of small dimensions.

Abstract: In a carrier unit, a posture-stabilizing member 30 for stabilizing a bare chip to be generally parallel to a flat surface of an electrode sheet 32 is placed on the electrode sheet 32 in a carrier unit 21.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

Abstract: A semiconductor memory module includes a control component connected via various buses to semiconductor memory components on the top and bottom of a module board. Depending on the storage capacity and the rank configuration of the semiconductor memory module, address terminals are actuated via selection circuits either with address signals or control signals. According to an embodiment of the control component, control terminals are actuated with different control signals. The multiplexing of address and control signals allows the control component to control semiconductor memory components, in a semiconductor memory module, with different memory configurations without requiring an increased number of control terminals.

Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

Abstract: A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an electrical property of the memory cell and for thereby effecting an altered programming state of the memory cell.

Abstract: A semiconductor device (400) for improved charge dissipation protection includes a substrate (426), a layer of semiconductive or conductive material (406), one or more thin film devices (408) and a charge passage device (414). The thin film devices (408) are connected to the semiconductive or conductive layer (406) and the charge passage device (414) is coupled to the thin film devices (408) and to the substrate (426) and provides a connection from the thin film devices (408) to the substrate (426) to dissipate charge from the semiconductive/conductive layer (406) to the substrate (426).

Abstract: An apparatus and method for storage and retrieval of memory content including a storage structure containing a plurality of memory elements addressable as a two-dimensional array of memory content values, a reading circuit capable of retrieving the memory content values from a region of the two-dimensional array varying in size according to the desired memory readout resolution, an aggregating circuit capable of totaling the memory content values of the memory elements addressed by the reading circuit to produce an aggregate memory content value and a normalizing circuit capable of scaling the aggregate memory content value according to the number of memory elements in the contiguous region to produce an average memory content value of the desired memory readout resolution.

Abstract: Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.

Abstract: An apparatus, system, and method for a tray to receive and couple a nonvolatile memory device to an electronic device disposed within a housing, are disclosed herein.

Abstract: A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub controller through any intervening memory modules. The signals are coupled to and from the memory modules through high-speed bit-lanes. In the a bit-lane connected to any of the memory hubs is inoperative, the memory hub re-routes signals that would be coupled through the inoperative bit-lane to an adjacent bit lane. When the signal reaches a memory hub in which the bit-lane is no longer inoperative, the memory hub routes the signal back to the original bit lane. In this manner, multiple bit-lane failures can be accommodated using a signal extra bit-lane.

Abstract: An operation switch circuit receives a command specifying operational specifications from a host. An operation control circuit controls the time of voltage application to a plate line based on an output signal from the operation switch circuit, to attain volatile-mode operation in a first memory region and nonvolatile-mode operation in a second memory region, for example.

Abstract: A data transmission system, particularly as part of a DDR-III memory chip communication circuit, performs a data transmission operation without preamble. The data transmission system includes at least one data line with an on die termination that can be turned on and turned off, and the chip end of the data line is connected to a positive or to a less positive, grounded, or negative supply voltage line by a pull-up or pull-down resistor. Alternatively, a data transmission system is operated with a timing by which the termination circuits to be turned on for respective operating state are not turned on until the drivers to be activated for the respective operating state have been activated.

Abstract: Memory modules and methods for fabricating and implementing memory modules wherein unique operating current values corresponding to specific memory devices on the memory modules are accessed from a database such that the operating current values may be implemented to improve system performance. Memory modules comprising a number of volatile memory devices may be fabricated. Operating current values corresponding to the specific memory devices on the memory module may be stored in a database and accessed during fabrication or during implementation of the memory modules in a system. System performance may be optimized by implementing the unique operating current values corresponding to the specific memory devices on the memory modules.

Abstract: Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.