Abstract: A method of generating a hypothesis and estimating a CFO includes receiving a signal including a set of radio frames, dividing each received radio frame of the set into a set of received sub-sequences, dividing, each of reference radio frames from a reference signal stored in the receiver into a set of reference sub-sequences, correlating the set of received sub-sequences with the set of reference sub-sequences to obtain a set of correlation values, generating, a first value set and a second value set of hypothesis based on the correlation values, generating a first and a second hypothesis based on the first value and the second value set, and averaging the first and the second hypothesis to obtain an averaged hypothesis, performing a DFT on the averaged hypothesis to obtain a DFT sequence, determining a peak position of the DFT sequence, and estimating the CFO based on the peak position.

Abstract: A receiver performs interference mitigation under blind or semi-blind conditions using diversity present in the signal of interest or in the interferer. A first path interference mitigation procedure extracts training information from received signals, performs interference mitigation on the training information and estimates the channel. The second path interference mitigation procedure uses data extracted from the received signal and the channel estimate to perform interference mitigation. Each interference mitigation process can take the form of a lossy compression followed by decompression.

Abstract: Methods, systems, and devices are described for equalizing data from an optical signal. Samples are filtered with at least one filter to compensate for polarization mode dispersion in an optical path. The filtered samples may be used to determine errors based on a difference between a radius of a recovered symbol and a target radius. A parameter may be assigned to one or more of the errors and properties of the at least one filter may be updated based on the assigned parameters. The parameter may be assigned from a small set of parameters based on at least one threshold value. Outputs generated from the filtered samples may also be assigned a parameter from a different set of parameters. The parameter assigned to the output may be used to update the particular set of taps of the at least one filter from which the output was generated.

Abstract: A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Abstract: An apparatus for encoding data signals includes a transmitter configured to encode and transmit a data signal over a communication channel, the transmitter including a precoder; a signal shaper configured to adjust the data signal by applying an equalization setting to the data signal, the equalization setting including an amplitude and offset and transmit the adjusted data signal to the precoder; and a processing unit. The processing unit is configured to perform: receiving channel coefficients associated with the communication channel; for each of a plurality of amplitude settings and a plurality of offset settings, calculating whether a modulo amplitude level would occur at a receiver using a modulo operation; selecting the equalization setting from the plurality of amplitude settings and the plurality of offset settings based on the calculation; and transmitting a control signal specifying the equalization setting to the signal shaper.

Abstract: The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission.

Abstract: Disclosed are various embodiments for a symbol level Krylov method equalizer implemented in a wireless communications device. An HSDPA or WCDMA signal is input to the wireless communications device. A conjugate gradient method is applied to symbol-level samples of the signal until a termination condition is met. The termination condition may comprise having zero residual error, residual error below a threshold, or a specified number of iterations. Additionally, a preconditioning matrix may be applied to the inputs of the conjugate gradient method.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: Generating updated coefficients for an adaptive equalizer involves generating phase tracking information using asynchronous detection strategy (ADS) based on resolved data, and equalized signals, and estimating a phase corrected error based on the equalized signals, the phase tracking information and the resolved data. An inhibit signal is generated to inhibit updating of the equalization coefficients, the inhibit signal representing a likelihood of the phase corrected error being accurate, determined according to the phase corrected error, and the equalized signals. The equalization coefficients for the equalizer are adapted based on the received signals, and on the phase corrected error, and the adapting is inhibited according to the inhibit signal. Compared to conventional ADS, the new combination with the inhibit signal can enable improved convergence of coefficient adaptation. This is particularly useful for coherent receivers for optical systems.

Abstract: Embodiments of the claimed subject matter provide a method for supporting network monitoring of user equipment events. Some embodiments of the method include receiving, at a home subscriber server (HSS) in a public land mobile network (PLMN), a request to monitor one or more events associated with one or more users. The request is used to configure, activate, or deactivate delivery of reports from one or more entities in the PLMN to a monitor collection entity in response to the event(s). Some embodiments of the method also include configuring one or more profiles in the HSS associated with the user(s) based on the request and providing the request to monitor the event(s) associated with the user(s) to one or more serving nodes for user equipment associated with the user(s).

Abstract: A technique for a reconditioning equalizer filter for non-constant envelope signals is described. The input to a transmitter chain is modified by a reconditioning equalizer filter, prior to being applied to the transmitter. The reconditioning equalizer filter modifies and smoothens the amplitude of the signal. The modified and smoothened signal has its peaks reduced which results in lower Crest Factor. The input to the reconditioning equalizer filter could be a baseband, intermediate frequency (IF) or radio frequency (RF) signal. When the signal is an IF or RF signal, it needs to be down-converted to baseband before being applied to the reconditioning equalizer filter. The reconditioning equalizer filter could be performed in a digital or analog domain.

Abstract: A method includes providing a plurality of sets of equalizer taps, wherein each set is coupled to a respective one of a plurality of antenna ports; assigning a first plurality of equalizer taps of the sets of equalizer taps to a first subset; determining a first covariance measure associated with the first plurality of equalizer taps of the first subset based on a first correlation criterion; assigning a second plurality of equalizer taps of the sets of equalizer taps to a second subset; and determining a second covariance measure associated with the second plurality of equalizer taps of the second subset based on a second correlation criterion.

Abstract: Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs.

Abstract: A reconfigurable P-way parallel N-tap feed forward equalizer includes an adaptive filter configured to generate a series of coefficients (taps) and an input register for storing input symbols. A variable cursor position defined by a parameter corresponding to a position in the input register selects a set of pre-cursor and post-cursor taps for dynamic ISI correction of a like set of pre-cursor and post-cursor symbols. Multiplier banks generate partial result symbols by applying the taps to the set of input symbols, and a set of combiners or adder banks generate equalized output symbols from the partial result symbols. Two multiplexers adjust input symbols and coefficients according to the parameter, and a controller allows selection of an optimal parameter, and thus an optimal variable cursor position. The coefficient corresponding to the parameter may additionally be preset to save storage space.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for tone reduction in relation to data transmission.

Abstract: A data signal delay system may include a delay unit and a phase interpolation unit. The delay unit may include multiple delay elements that each have an element delay. The delay unit may be configured to generate multiple delay signals by delaying a data signal using the delay elements such that each of the delay signals has a different delay. The phase interpolation unit may be coupled to the delay unit and may include a mixer. The mixer may be configured to mix two of the delay signals based on mixing weights selected for the two delay signals to generate a final delayed data signal that is the data signal delayed by a final delay. The mixing weights may be selected based on the final delay.

Abstract: Feed-forward equalizer (FFE) circuits and methods are provided which implement time domain analog multiplication for adjusting FFE tap weights. For example, a method includes inputting data signals to FFE taps of a current-integrating summer circuit, wherein the data signals are time-delayed versions of an analog input data signal. A capacitance is charged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each FFE tap during an integration period of the current-integrating summer circuit. The output currents from the FFE taps collectively charge or discharge the capacitance during the integration period.

Abstract: A digital receiver equalization system has a digitized signal input derived from an analog front-end of a digital receiver and having a relatively wide bandwidth. A synthesis channelizer decomposes the digitized signal input into a plurality of time domain synthesis channels each having a relatively narrow bandwidth. An analysis channelizer recomposes the synthesis channels after digital signal processing is performed on at least a portion of the synthesis channels so as to generate a digitized output signal. A channelizer domain defines digital signal processing between the synthesis channelizer and the analysis channelizer. A least a portion of the channelizer domain digital signal processing is a cascade of multiplier arrays, and at least one of the multiplier arrays has inputs that compensate for channel distortion.

Abstract: Requests are identified for equalization coefficients and a plurality of coefficient selections are tracked relating to the requests. A matrix is maintained within a grid space that is to represent the coefficients, the matrix representing one or more of the coefficient selections. The matrix is adjusted within the grid space to obtain an adjusted matrix that is to accommodate selection of a particular coefficient outside the matrix. A final coefficient can be selected based on the adjusted matrix.

Abstract: A decision feedback equalizer that can operate at higher speed is provided. The decision feedback equalizer includes a weighting addition circuit (adder 21, coefficient units Tap1a, Tap2 to Tapn) that sums an input signal to weighted versions of feedback signals FB1 to FBn, n being an integer not less than 2. The decision feedback equalizer also includes a decision circuit 11 that decides whether or not the result of addition by the weighting addition circuit is not less than a defined threshold value and that outputs the result of the decision to outside and to a shift register (latch circuits L2 to Ln). The decision circuit operates in synchronism with a clock signal. The shift register sequentially holds the result of decision of the decision circuit 11 in synchronism with the clock signal, and outputs the contents held by its component registers as feedback signals FB2 to FBn.

Abstract: Methods and apparatus adapting equalizers for compensating for signal distortion of a received digital signal are disclosed. The method comprises deriving equalizer settings for a received signal, determining at least one signal parameter of said received signal; and storing the derived equalizer settings together with an indication of the signal parameter. The signal parameter could, for instance, comprise the data rate of the signal. If the signal parameter changes the equalizer is configured to use any stored settings which are appropriate for the new signal parameter. Thus, rather than start an entirely new equalizer adaptation routine every time the signal parameter changes the equalizer will use any stored settings which are appropriate for the changed parameter.

Abstract: A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.

Abstract: Circuits and methods characterize a receiver. The circuit includes a decision feedback equalizer (DFE) circuit, a clock and data recovery (CDR) circuit, a data checker, and an eye-scan controller. The DFE circuit generates a filtered signal from the communication signal. The filtered signal is a sum of the communication signal and a variable weighting of a symbol recently sampled from the filtered signal. The CDR circuit samples a sequence of sampled symbols from the filtered signal. The CDR circuit samples the filtered signal at a variable phase relative to a clock signal. The data checker generates an indication of an error in the sequence of sampled symbols. The eye-scan controller varies the variable weighting and the variable phase through multiple value combinations. The eye-scan controller checks for the indication of the error for each of the value combinations.

Abstract: In a data processing device and a method for analyzing stability of the data processing device, one or more sets of equalization parameters and a predetermined bit error ratio (BER) are received. Times and voltages of data points that represent a waveform of an electronic signal generated by the data processing device are read, and an output type of the electronic signal is selected to obtain a time interval of outputs of the electronic signal. Optimal equalization parameters are selected from the one or more sets of equalization parameters to compute a sample interval. Interfering voltages of the electronic signal are computed to select a frequency which is equal to the predetermined BER, and the interfering voltages corresponding to the selected frequency are obtained. An eye pattern is established using the interfering voltages corresponding to the selected frequency, and a determination is made according to the eye pattern.

Abstract: Circuits and methods are provided for efficient feed-forward equalization when sample-and-hold circuitry is employed to generate n time-delayed versions of an input data signal to be equalized. To equalize the input data signal, m data signals are input to m feed-forward equalization (FFE) taps of a current-integrating summer circuit, wherein each of the m data signals corresponds to one of the n time-delayed versions of the input data signal. A capacitance is precharged to a precharge level during a reset period of the current-integrating summer circuit. An output current is generated by each of the m FFE taps during an integration period of the current-integrating summer circuit, wherein the output currents from the m FFE taps collectively charge or discharge the capacitance during the integration period. A gating control signal is applied to an FFE tap during the integration period to disable the FFE tap during a portion of the integration period in which the data signal input to the FFE tap is invalid.

Abstract: A receiving apparatus applied to a receiving end of a communication device having an equalizer is provided. The receiving apparatus includes a filter and a channel estimator. The filter filters a received signal to reduce a multipath effect of the received signal and outputs a filtered signal. The channel estimator performs channel estimation on the received signal to generate an estimation result. The estimation result is for determining which of the received signal and the filtered signal is to be selected and sent to the equalizer.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols.

Abstract: An apparatus including a receiver having a feed forward equalizer (FFE) coupled to a communication channel. The receiver may be configured to adjust the FFE using information based on an estimate of one or more characteristics of the communication channel.

Abstract: A method of channel estimation includes receiving a signal after transmission over a media having a plurality of sub-carriers in a frequency band. The signal is preprocessed including performing a fast Fourier transform (FFT) to generate a plurality of frequency-domain samples. Channel estimating is applied to the plurality of frequency-domain samples using (i) least squares (LS) estimation, wherein the LS estimation generates intermediate LS channel estimates for each of the sub-carriers, and (ii) frequency-domain filtering and scaling the intermediate LS channel estimates. The frequency-domain filtering uses a common frequency-domain filter consisting of a single filter coefficient vector having a plurality of frequency-domain filter coefficients to generate refined channel estimates for each of the plurality of sub-carriers.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A reception device includes two antennas 1-1, 1-2 that are in an inverse correlation, a switching unit 4 which switches the signal that is to be processed among signals received by the two antennas 1-1, 1-2, and an adaptive equalizer 6 which uses equalization coefficients to perform equalizing processing on the signal considered by the switching unit 4 to be the signal to be processed, and an equalization coefficient altering unit 7 which alters the equalization coefficients used by the adaptive equalizer 6 synchronously with the timing of switching performed by the switching unit 4. In the reception device can reduce the required time for reconvergence of equalization coefficients stemming from reception system switching in selection diversity using an inverse correlation antenna.

Abstract: An equalization adaptation circuit comprises an equalizer, a transition determination circuit, a phase error circuit, a sequence recovery circuit, a phase error accumulator circuit, a transition accumulator circuit, and a controller circuit. The equalizer has adjustable parameters. The transition determination circuit determines observed transitions in an equalized signal output from the equalizer. A phase error circuit determines phase errors of the observed transitions. A sequence recovery circuit generates recovered digital data sequences. A phase error accumulator circuit accumulates the phase errors in respective association with pre-defined patterns matching the recovered digital data sequences containing observed transitions corresponding to the phase errors. A transition accumulator circuit accumulates a number of the observed transitions. A controller circuit controls the adjustable parameters of the equalizer based upon the accumulated phase errors and number of observed transitions.

Abstract: One or more embodiments describe a decision feedback equalizer with multiple cores for highly spectrally efficient communications. An equalization circuit in a receiver may include a decision feedback equalizer circuit having a first plurality of tap coefficients that are determined based on a cost function that receives as input an error signal that is an inter-symbol-correlated (ISC) signal. The decision feedback equalizer circuit may further include a second plurality of tap coefficients that are determined based on a filter with an ISC response. The cost function may determine the mean square of the error signal. The cost function is constrained or unconstrained. The error signal may represents error caused by a channel. In some embodiments, the ISC signal may be a partial response signal, and the filter with an ISC response may be a partial response filter.

Abstract: A detection process for a receiver of a wireless communication system based on Multiple-In-Multiple-Out antennas, the process involving: —a preprocessing which only depends on the channel H, said preprocessing involving: —A QRD decomposition (61) for the purpose of decomposing said channel H into two Q and R matrices, with QHQ=I and R being upper triangular; —a lattice reduction (62) for the purpose of generating (formula AA, formula BB) and a permutation matrix T; —a loading phase (63, 64, 65) comprising a linear LRA-Minimum-Mean-Square-Error equalization applied on said symbols y in accordance with the result of said lattice reduction for the purpose of generating a value (formula CC).

Abstract: Disclosed herein are a passive equalizer and a high-speed digital signal transmission system, including first and second impedances connected in series to a first transfer line, third and fourth impedances connected in series to a second transfer line, a first inductor connected in parallel between the first impedance and the second impedance, a second inductor connected in parallel between the third impedance and the fourth impedance, and a resistor connected in series between the first inductor and the second inductor.

Abstract: An equalizer is disclosed, and associated operational method. The equalizer has a configuration that balances performance and complexity by obtaining samples that are strongly correlated with future and past transmitted bits, and are weakly correlated with future and past bit transitions, and is useful for timing recovery circuits. Samples are only obtained or collected at time intervals more than one sample period away from the reference sample. Samples are shifted by a delay value less than the sample period, and are obtained at a sample period of one unit interval. A means to adjust the sampling point delay is also disclosed. In an implementation, samples that are within the sample period away from the reference sample are obtained and used for implementing a timing shift, not for equalization of the timing recovery signal. Embodiments are also disclosed for optimizing performance for data recovery.

Abstract: The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.

Abstract: Transmissions from mid-bus test equipment to a first device and from a second device to the mid-bus test equipment are equalized. Equalization instructions are passed from the first device through the mid-bus test equipment to the second device. The mid-bus test equipment changes the quality of transmissions sent to the first device in order to steer the first device to produce equalization instructions that will produce optimized transmissions from the mid-bus test equipment to the first device and from the second device to the mid-bus test equipment.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: One embodiment relates to an equalizer circuit for a data link. The equalizer circuit including a continuous-time linear equalizer, a first circuit loop, and a second circuit loop. The continuous-time linear equalizer receives a received signal and outputs an equalized signal. The first circuit loop determines a first average signal amplitude. The first average signal amplitude may be an average signal amplitude of the equalized signal. The second circuit loop a second average signal amplitude. The second average signal amplitude may be an average signal amplitude of a high-frequency portion of the equalized signal. Other embodiments and features are also disclosed.

Abstract: A method of wireless communication with improved performance employs an equalizer receiver with multiple receive antennas. Equalizer taps for linear filters of the equalizer receiver are generated by determining a conditioned covariance matrix of a first data path and a second data path based on a first gain (g0) of this first data path and a second gain (g1) of the second data path. The equalizer taps of the first data path and the second data path are determined based on the conditioned covariance matrix. The first data path and the second data path are then equalized using the equalizer taps. An equalized signal is generated by combining the equalized first data path with the equalized second data path.

Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

Abstract: A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

Abstract: Equalization techniques are provided for high-speed data communications and, more specifically, DFE (decision feedback equalizer) circuits and methods are provided which implement a high-order continuous time filter in a DFE feedback path to emulate structured elements of a channel response.

Abstract: An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

Abstract: A method of operation of a wireless communication system includes: receiving a received signal; generating concurrently a first modulation data and a second modulation data from the received signal; calculating an error energy for the first modulation data and the second modulation data; and removing a residual Direct Current (DC) offset from the received signal based on determining a minimum of the error energy for the first modulation data or the second modulation data.

Abstract: A receiver and a method for equalizing signals, the method includes: receiving input signals; sampling the input signals to provide oversampled samples; processing the oversampled samples to provide symbol spaced samples and to provide fractionally spaced samples that represent the oversampled samples; calculating taps of a fractionally spaced equalizer based on the symbol spaced samples; feeding the taps to the fractionally spaced equalizer; and filtering the fractionally spaced samples by the fractionally spaced equalizer to provide equalized samples.

Abstract: One embodiment relates to a receiver with both decision feedback equalization and on-die instrumentation. A clock data recovery loop obtains a recovered clock signal from an input signal, and a first sampler, which is triggered by the recovered clock signal, generates a recovered data signal from the input signal. A phase interpolator receives the recovered clock signal and generates a phase-interpolated clock signal. A second sampler is triggered by the recovered clock signal in a decision feedback equalization mode and by the phase-interpolated clock signal in an on-die instrumentation mode. Other embodiments and features are also disclosed.

Abstract: Various embodiments described herein are directed to methods and systems for blind mode adaptive equalizer system to recover complex valued data symbols from the signal transmitted over time-varying dispersive diversity wireless channels. For example, various embodiments may utilize an architecture comprised of a bank of estimation units, a normalizing gain estimator, a DSP unit and a feedback shift register providing the equalizer feedback state vector. The estimation unit may be further comprised of a multiplicity of adaptive algorithms providing various filtered estimates of the data symbol to the DSP unit or providing the joint estimate of the transmitted data symbol.