Abstract: Circuitry for use in a receiver may comprise: a front-end circuit operable to receive an orthogonal frequency division multiplexing (OFDM) symbol on a first number of physical subcarriers. The circuitry may comprise a decoding circuit operable to decode the OFDM symbol using an inter-carrier interference (ICI) model, the decoding resulting in a determination of a sequence of symbols, comprising a second number of symbols, that most-likely correspond to the received OFDM symbol, where the second number is greater than the first number. The sequence of symbols may comprise N-QAM symbols, N being an integer. The ISCI model may be based, at least in part, on non-linearity experienced by the OFDM symbol during transmission by a transmitter, propagation over a channel, and/or reception by the receiver. The ISCI model may be based, at least in part, on phase-noise introduced to the OFDM symbol during transmission by a transmitter, propagation over a channel, and/or reception by the receiver.

Abstract: A method of operation in a receive circuit is disclosed. The method comprises entering an initialization mode followed by receiving training data from a lossy signaling path. The training data originates from a transmit circuit. The received training data is sampled and minimax transmit equalizer coefficients are generated based on the sampled data. The minimax transmit equalizer coefficients are then transmitted back to the transmit circuit. The initialization mode is exited and an operating mode initiated, where transmit data precoded by the minimax transmit equalizer coefficients is received.

Abstract: A method and apparatus for processing input data signals transmitted in a continuous mode, or in a burst mode, of signal transmission, such as in a satellite or a computer network communications system. A receiver receives input data signals and a buffer stores the received input data. Processing circuitry generates frame timing synchronization control signals for writing the frames of the input data for storage, generates timing error control signals corresponding to a processing delay for the input data, for synchronizing reading out the stored data from the buffer based on a timing difference between the timing error control signals and the frame timing synchronization control signals to adjust for an arbitrary delay in processing the input data. The processing circuitry can include a tap gradient update circuit for generating a tap gradient corresponding to the read out data, based on equalizer error signals generated by the processing circuitry.

Abstract: A receiving circuit, use, and method for receiving an encoded and modulated radio signal is provided. The circuit comprise a demodulator and a digital filter connected downstream of the demodulator for moving averaging. The filter has at least two FIFO registers and subtractors. Whereby for subtracting an output value of the FIFO register from an input value of the FIFO register a subtractor is connected to each FIFO register. Wherein the filter has a weighting unit, which is connected downstream of each FIFO register, and wherein the filter has an integrator, which is connected downstream of the subtractors for integration.

Abstract: Techniques for operating a diversity receiver are described. A user equipment (UE) may include (i) a first receive chain having an equalizer and a first rake receiver and (ii) a second receive chain having a second rake receiver. The UE may support (i) a first mode in which only the equalizer is used to process a received transmission and (ii) a second mode in which both rake receivers are used to process the received transmission. The UE may determine a first performance metric for the first mode (e.g., based on the performance of the equalizer) and a second performance metric for the second mode (e.g., based on the performance of both rake receivers or only the first rake receiver). The UE may select the first or second mode based on the performance metrics and may power down the second receive chain if the first mode is selected.

Abstract: An example method for controlling a continuous time linear equalizer includes: developing a voltage histogram of a signal present at an output of a continuous time linear equalizer; developing a quality factor for the voltage histogram; comparing the quality factor with a prior quality factor; decreasing an equalization of the continuous time linear equalizer if the quality factor is less than the prior quality factor and increasing the equalization of the continuous time linear equalizer if the quality factor is greater than the prior quality factor.

Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.

Abstract: This invention relates to methods and apparatus for equalizer adaptation for compensating for channel distortion on received data signals. The method comprises, for each bit, forming an adjusted bit signal comprising a weighted contribution from at least one other bit period. The polarity of the adjusted bit signal is determined and the bit is categorized as a hard, i.e. high confidence, bit is the bit is above an upper threshold or below a lower threshold or otherwise is categorized as a soft bit. The weightings are adjusted based on the category of the bit wherein a first adjustment is made it the bit is categorized as a soft bit but a second, different adjustment is made if the bit is categorized as a hard bit. For a soft bit the weightings may be increased for bits which have the same polarity as the bit in question and decreased for bits of opposite polarity.

Abstract: Methods and systems are provided for coarse phase estimation for highly-spectrally efficient communications. An example method may include, equalizing, in a receiver, a received inter-symbol correlated (ISC) signal to generate an equalized ISC signal. A phase adjustment signal may be generated based on an ISC feedback signal. The ISC feedback signal may be generated using a sequence estimation process and a non-linearity function. A phase of the equalized ISC signal may be adjusted using the generated phase adjustment signal, to generate a phase adjusted partial response signal. The phase adjustment signal may be generated based on a phase difference between the equalized ISC signal and the partial response feedback signal. At least one ISC vector may be generated by buffering samples of the phase adjusted ISC signal.

Abstract: In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Abstract: An algorithm to detect single path channel conditions and reduce the span (number of taps) of the equalizer in order to mitigate the performance degradation caused by noisy equalizer taps is disclosed. The algorithm provides two novel components comprising single path scenario detection and single path scenario processing or (equalizer shortening). A single path scenario is detected when the energy concentrated in a single channel impulse response tap divided by the total energy of the taps exceeds a predetermined threshold. When a single path scenario is detected, only the equalizer taps within a variable window around the equalizer tap having concentrated energy are used to filter the received signal.

Abstract: A receiver includes an adaptive equalizer, a power detecting unit and an adjusting unit. The adaptive equalizer is for receiving a signal and generating an equalized signal. The power detecting unit, coupled to the adaptive equalizer, is for detecting the strength of the equalized signal during a first period to generate a first strength signal, and detecting the strength of the equalized signal during a second period to generate a second strength signal. The adjusting unit, coupled to the power detecting unit and the adaptive equalizer, is for adjusting the compensation strength for the adaptive equalizer according to the first and second strength signals.

Abstract: The present invention provides a signal processing device. The signal processing device includes a first feed forward equalizing unit, a first data slicing unit, a second feed forward equalizing unit, and a second data slicing unit. The first feed forward equalizing unit is utilized for performing a compensation operation according to a digital input signal so as to generate a first equalized signal. The first data slicing unit is coupled to the first feed forward equalizing unit, and utilized for generating a first output signal according to the first equalized signal. The second feed forward equalizing unit is coupled to the first data slicing unit, and utilized for generating a second equalized signal according to the first equalized signal. The second data slicing unit is coupled to the second feed forward equalizing unit, and utilized for generating a second output signal according to the second equalized signal.

Abstract: A transmitting apparatus that converts a transmission digital signal to a high-frequency analog signal and transmits the high-frequency analog signal using a plurality of transmission frequencies, the transmitting apparatus including: a dividing unit that divides a transmission signal sequence into a plurality of blocks; a sub-block generating unit that applies pre-coding processing to the blocks and further divides the blocks after the pre-coding processing into sub-blocks; a frequency allocating unit that generates a frequency signal in which the sub-blocks are allocated to the transmission frequencies; and an inverse DFT processing unit that transforms the frequency signal into a time signal, wherein the transmitting apparatus sets the time signal as the transmission digital signal.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: This invention relates to an apparatus and a method for controlling a filter coefficient. The filter coefficient control apparatus controls a coefficient of a filter of a phase recovering apparatus, and comprises a phase offset obtaining means, for obtaining a phase offset between a carrier and a local oscillation; an autocorrelation calculating means, for calculating an autocorrelation and related statistics of the phase offset; and a filter coefficient determining means, for determining the coefficient of the filter in accordance with the autocorrelation and related statistics.

Abstract: An arrangement (100) and method for RF filtering in a Node B of a UMTS TDD system by providing: a DAC converter (130) converting digital signals to analog signals; providing a narrow band analogue channel filter (150) filtering the analog signals; and providing a digital pre-equalizer FIR filter (120) coupled before the DAC (120) to filter the digital signals, the digital pre-equalizer filter means substantially correcting for non linear phase response (122) non-ideality and amplitude response non-ideality (124) in the analogue channel filter (150). This provides the following advantage(s): it enables 3GPP Node B co-location specifications to be met while providing both good transmit accuracy and acceptable ISI performance; and it allows filter center frequency to be field tuned in software, permitting a basic RF single-channel filter to used with its center frequency being field adjustable to a desired value centered on a UMTS channel.

Abstract: Methods and apparatus are provided for joint adaptation of filter values in two communicating devices, such as a link partner and a link device. The disclosed joint adaptation process initially adapts the filter coefficient values in a first of the two communicating devices until a predefined stopping criteria is satisfied. Thereafter, the filter coefficient values in a second of the two communicating devices are adapted once the predefined stopping criteria for the first communicating device is satisfied. The filter coefficient values can comprise coefficient values of a multi-tap filter. The predefined stopping criteria may determine, for example, whether the first of the two communicating devices is overequalized. The filter coefficient values can be determined by including a contribution of only certain cursor tap values of the channel impulse response.

Abstract: Decision feedback equalization (DFE) circuitry and method for equalizing data signals over a wide range of data rates. By using delayed and controlled versions of the recovered data clock to retime the equalized data signal for feedback via the DFE taps, correct feedback signal timing is maintained and jitter tolerance is increased at high data rates.

Abstract: A MMSE equaliser taking into account delays in the reception of signals from plural users. Time delays in reception of signals from plural users may be known or can be measured or estimated and can be used to for the basis for the operation of the equaliser. A low computational complexity version of the equaliser and a regularized equalizer with further reduced complexity for asynchronous reception are also disclosed.

Abstract: In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M?1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M?1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

Abstract: A method of processing digital broadcast data in a digital broadcast transmitter includes performing Reed-Solomon (RS) encoding and Cyclic Redundancy Check encoding on mobile service data to build an RS frame; dividing the RS frame into a plurality of portions; mapping one of the plurality of portions into a first data group and inserting known data sequences, transmission parameters, place holders for non-systematic RS parity data, place holders for main service data, and place holders for MPEG header data into the first data group; deinterleaving data of the first data group to output a second data group; and removing the place holders for non-systematic RS parity data and the place holders for main service data in the second data group and replacing the place holders for MPEG header data in the second data group with MPEG header data to output mobile service data packets.

Abstract: A noise abatement method and system for impulse noise in an RF receiver where the RF analog signal is converted to a digital signal prior to being connected to a demodulator. Two filters are used to detect impulse noise signals even under out-of-band interferer conditions, and prevent the impulse noise from reaching the input to the demodulator. A first of the two filters detects impulse noise using signals lower than the frequency bandwidth of the desired signal, and a second of the two filters detects impulse noise using signals higher the frequency bandwidth of the desired signal. A mean magnitude of the signal is detected over a predetermined time T and is used to select which filter to use for noise abatement.

Abstract: A receiver circuit includes an equalizer circuit that adjusts reception intensity of an input signal based on an intensity adjustment value to generate a correction input signal; a first holding unit that holds a plurality of data items sampled based on a sampling clock for sampling values of the data items transmitted by the correction input signal in a receiving order; a second holding unit that holds a plurality of values of the correction input signal sampled based on a complementary sampling clock for sampling a boundary value of the data items in a receiving order; and an equalizer control circuit that judges the strength of reception intensity of the correction input signal based on a plurality of output signals of the first holding unit and a plurality of output signals of the second holding unit to update the intensity adjustment value based on the judgment result.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: A data equalizing circuit includes an equalizer configured to output data according to a control code; and a detection unit configured to divide the data into N number of calculation periods, count data transition frequencies for the N calculation periods, calculate dispersion values of the data transition frequencies for the N calculation periods, and output the control code corresponding to a largest dispersion value, in response to a counting interruption signal and a counting completion signal, wherein n is equal to or greater than 2, N is greater than n, and the data is divided to n number of unit intervals (UI), and wherein a phase shift of each of the calculation periods with respect to its corresponding UI is different from a phase shift of any of the other calculation periods with respect to its corresponding UI.

Abstract: A noise cancellation system has a first transformer with an input side and an output side, the input side having first and second taps coupled to a signal provider, and a center tap providing a first common-mode voltage signal. A first digital subscriber line (xDSL) modem has an input coupled to the output side of the first transformer and an output coupled to customer premises equipment (CPE) for providing an xDSL signal to the CPE. A second transformer has an input side and an output side, the input side having first and second taps coupled to a signal provider, and a center tap providing a second common-mode voltage signal. A second xDSL modem is coupled to the output side of the second transformer. The difference between the first and second common-mode voltage signals is provided to at least one of the first and second xDSL modems to filter out noise from the xDSL signal provided by that modem.

Abstract: The present invention relates to a method for minimizing means square estimation error (MSEE) and bit error rate during channel estimation and equalization between a transmitter and a receiver of an orthogonal frequency division multiplexing (OFDM) systems. The method comprises transmitting from said transmitter to said receiver a training sequence for channel estimation being superimposed onto data at specific pilot to data power ratio (PDPR), receiving the OFDM signals along with the training sequence as an input, cross-correlating said received signal to a specific lag determined by the rms delay spread of the channel, with a specific known training sequence stored in a register, and which is also the sequence that is added to the data at the transmitter in the time domain having a prescribed pilot to data power ratio.

Abstract: An offset calibration method is provided. Two input terminals of an equalizer are switched to a common voltage at a first time point, wherein the equalizer generates a first equalized signal and a second equalized signal according to the common voltage. It is determined whether a first offset voltage is present in the equalizer according to the first and second equalized signals generated from the common voltage. If the first offset voltage is determined to be present in the equalizer, a first compensation voltage is provided to the equalizer.

Abstract: A waveform equalization circuit includes: a decision feedback equalization unit that feeds back and equalizes an input signal; a clock phase adjustment unit that adjusts a clock phase of a signal equalized by the decision feedback equalization unit based on a signal determined with a prescribed potential as a threshold; and a duo-binary decoder that encodes, into a duo-binary signal, the signal determined with the prescribed potential as a threshold based on a clock adjusted by the clock phase adjustment unit from the signal equalized by the decision feedback equalization unit; wherein the equalized signal is generated by adding the duo-binary signal encoded by the duo-binary decoder to the input signal. A first post-tap of the input signal is equalized by the clock phase adjustment unit without feedback equalization by the decision feedback equalization unit. Second and subsequent post-taps of the input signal are fed back and equalized by the decision feedback equalization unit.

Abstract: Disclosed is a co-channel feedback signal cancelling regenerative repeater of the Advanced Television Systems Committee (ATSC) that extracts a predetermined reference value of feedback signal to be able to cancel the feedback signal among received signals, including: a signal receiving unit; a signal demodulating unit that converts frequency of a received signal and demodulates it into a baseband signal; an interference equalizing unit that corrects characteristics of the demodulated signal and cancels feedback signal; a channel equalizing unit that compensates for channel distortion of an original signal from which the feedback signal is cancelled; a modulating unit that modulates the channel distortion-compensated original signal and converts it into an analog signal; and a signal transmitting unit that converts the frequency of the modulated signal, controls and amplifies its gain, and transmits a regenerative transmission signal.

Abstract: One embodiment relates to a receiver circuit for a data link. The receiver circuit includes at least a first signal path, a second signal path, and a path selector circuit. The first signal path includes first equalization circuitry, and the second signal path includes second equalization circuitry. The path selector circuit is configured to select one signal path of the first and second signal paths. Other embodiments and features are also disclosed.

Abstract: A method, apparatus and computer program product are configured to provide calibration accuracy in an analog filter. In this regard, a method is provided that includes estimating a cutoff frequency for an analog filter. The method further includes causing a filter tuning word to be modified based on the estimated cutoff frequency for the analog filter. The method also includes determining a residual cutoff frequency mismatch for the analog filter. The method also includes causing an equalizer configuration to be selected for a digital filter based on the determined residual cutoff frequency mismatch.

Abstract: An apparatus for equalizing channels is provided, which is generally transparent to link training. The apparatus generally includes equalization paths formed by an input circuit, a crossbar, and an output circuit and a controller. Each equalization path is coupled to at least one of the channels, and a controller has a VGA loop, a crossbar loop, and a driver loop. The AGC loop receives a first reference voltage and provides a gain control signal to the input circuit, and the gain control network comprises a replica of at least one of the equalization paths. The crossbar loop receives a second reference voltage and provides a crossbar control signal to the crossbar. The driver loop receives a third reference voltage and provides a driver control signal for the output circuit.

Abstract: Methods and apparatus are provided for equalizing a received signal. A received signal is equalized by updating one or more equalization parameters; and discarding the updated equalization parameters if one or more predefined qualifier conditions are detected during the equalizing step. The received signal can optionally be equalized using the updated equalization parameters if the predefined qualifier conditions are not detected during the equalizing step. The updated equalization parameters can optionally be stored if the one or more predefined qualifier conditions are not detected during the equalizing step.

Abstract: A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.

Abstract: An interface circuit inputting and outputting data and a clock that have multiple speeds is provided with an equalizer capable of changing a circuit parameter, a frequency detection part detecting a clock frequency, and a parameter calculation control part calculating an appropriate circuit parameter according to the clock frequency and controlling the equalizer. The frequency detection part detects at what frequency the interface circuit is operating presently and sends the frequency to the parameter calculation control part. The parameter calculation control part calculates the circuit parameter of the equalizer so that the interface circuit operates optimally at the detected frequency, and sets the circuit parameter to the equalizer. In this manner, since the circuit parameter of the equalizer in the interface circuit can be controlled appropriately according to the frequency of the input and output clock, optimum operation is always available.

Abstract: In an RF signal transmission network such as the reverse channels of a coaxial cable network, there is provided at least one adaptive equalizer for pre- or post-filtering inter-symbol interference in the transmitted signals, the adaptive equalizer having a series of coefficients for which values are required. In order to improve the transmission efficiency the preamble used in these channels is shortened by coarsely estimating the channel using a short “unique word’ placed at the beginning of the equalizer training sequence. The coarse channel estimate is crudely inverted to produce a set of equalizer coefficients which partially equalize the channel. By initializing the adaptive equalizer with these approximate coefficients, it is possible to reduce the length of the training sequence needed for the equalizer to converge.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A signal reception method includes receiving a signal over a channel, producing a first equalized signal, a first interference suppression filter and a first estimate of the channel using a portion of a the received signal, dividing the received signal into a plurality of signal blocks, and for each one of the plurality of signal blocks, producing a second equalized signal using a portion of the first equalized signal by selecting from one of a linear estimator or a non-linear estimator and estimating symbols received in the one of the plurality of signal blocks based on the second equalized signal.

Abstract: In one embodiment, a receiver circuit is provided. The receiver circuit includes a low-power equalization circuit having a first linear equalization circuit coupled to receive serial data. The receiver circuit includes a low-noise equalization circuit having a second linear equalization circuit coupled to receive the serial data, and a non-linear equalization circuit coupled to an output of the second linear equalization circuit. The receiver circuit includes a control circuit configured to enable the low-power equalization circuit and disable the low-noise equalization circuit in response to a first state of a control signal. The control circuit is configured to disable the low-power equalization circuit and enable the low-noise equalization circuit in response to a second state of the control signal.

Abstract: An apparatus comprising an analog filter, an analog to digital converter coupled to said analog filter; and a digital filter coupled to said analog to digital converter; wherein the apparatus is configured such that distortion introduced into a filtered signal by said analog filter is substantially compensated by said digital filter.

Abstract: A receiving system and method of processing a broadcast signal is provided. The receiving system includes a signal receiving unit, a known sequence detector, a channel equalizer, a block decoder, and an error correction unit and receives a broadcast signal including mobile service data and a data group including multiple known data sequences. The known sequence detector detects the multiple known data sequences. The channel equalizer repetitively updates equalization coefficients and filters up to a pre-determined number of iterations based upon the detected known data sequences and converges the equalization coefficient. The channel equalizer interpolates or extrapolates using the converged equalization coefficients and channel-equalizes the mobile service data. The block decoder performs turbo-decoding in block units on the channel-equalized mobile service data. The error correction unit performs error correction decoding on the decoded mobile service data to correct errors in the mobile service data.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i?1[0]?R?i?1[2], and the permutation code forms, with an additional bit, a twelve bit address.

Abstract: A DFE circuit for use in a semiconductor memory device and an initializing method thereof. In the method of initializing a DFE circuit used in a semiconductor memory device having a discontinuous data transmission, the DFE circuit may be used for changing a sampling reference level in response to a level of previous data and sampling transmission data. The method includes terminating a data channel having a transmission of the transmission data at a predefined termination level, and controlling a sampling start time point of the transmission data as a time point preceding a transmission time point of the transmission data by a predefined time. Further, an initialization may be performed of the previous data on the basis of initialization data obtained through a pre-sampling of the data channel at a sampling start time point of the transmission data, thereby obtaining an initialization of the DFE circuit and compensating for a feedback delay.

Abstract: A method and apparatus for transmitting and receiving a space block coding signal through Iterative Multi-user Detection is provided. The apparatus includes a multi-user interference cancellation unit which cancels multi-user interference in a received signal and outputs a first signal and a second signal that are sequentially transmitted from two transmitting antennas, a linear combiner which performs linear combination for the first signal and the second signal, and an equalizer which applies different equalization coefficients to the combined first signal and the second signal, respectively, to perform frequency-domain equalization.

Abstract: Apparatus, and an associated method, for the receive part of a receiving station, such as a mobile station or other transceiver of a cellular communication system. Selection is made of filter characteristics to be exhibited by an adaptive, input noise whitening filter. A noise estimator estimates a noise component of a noise sequence. An autocorrelation estimator estimates the noise-component autocorrelation. A determination is made as to whether the autocorrelation exceeds a threshold. If so, filter characteristics are selected to cause the input noise whitening filter to operate to inject whitening noise into the received sequence.

Abstract: A method to adjust a waveform transmitted from a field device to overcome cable bandwidth limitations by passing data to be transmitted through a channel compensation device which pre-distorts data to be transmitted to compensate for the bandwidth limitations. The predistortion may make sure that there is a good quality signal received at the control end of the cable.

Abstract: System and method for equalizing an orthogonal frequency division multiplexed signal having been encoded by spreading subcarriers in the frequency domain using orthogonal codes includes receiving the signal at a receiver (300), demodulating the signal to produce demodulated information, producing a spread frequency domain representation of the demodulated information, determining an equalized representation by adjusting the power and phase of the spread frequency domain representation at least one frequency based on adjustment values, de-spreading the equalized spread frequency domain representation using the orthogonal codes to produce a de-spread frequency domain representation including received subcarriers, determining a subcarrier value for each of the received subcarriers, orthogonally spreading the determined subcarrier values using the orthogonal codes to produce a model spread frequency representation, calculating expected error values based upon the model spread frequency representation and the equa