Abstract: A method of compensating interference of received symbols in a MIMO OFDM receiver employs MMSE equalization and LLR scaling, and a MIMO OFDM receiver includes a linear MMSE equalizer. The method provides a low-complexity, numerically robust method for compensating interference of received symbols and provides a low-cost, robust digital baseband receiver for MIMO-OFDM, achieved by merging linear MMSE equalization and scaling of the corresponding equalized symbols into a single algorithm that, for the 2×M MIMO case, completely avoids computationally extensive matrix inversion and allows for significant simplification of symbol detection as compared to separate equalization and scaling.

Abstract: Techniques are described to adaptively adjust the equalizer settings of each transmitter in a transmitter-receiver pair. The transmitter-receiver pair can be used at least with implementations that comply with 40GBASE-CR4 or 100GBASE-CR10. For implementations that comply with 40GBASE-CR4, equalizer settings of four transmitters may be independently established.

Abstract: A channel equalizer having a filter arranged to filter an input signal, the filter including a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving the coefficients and an output for outputting a filtered signal; and coefficient generating circuitry including a graduation unit arranged to receive the input signal and an error signal indicating an error in the filtered signal, to accumulate gradient values relating to each of the coefficients based on a plurality of error values of the error signal, each of the gradient values indicating a required change in one of the coefficients, and to sequentially output the gradient values; and coefficient update unit arranged to sequentially update each of the filter coefficients in turn, based on the gradient values.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A channel equalizer arranged to receive a data signal encoded by a plurality of amplitude levels, the circuitry including a filter having a plurality of taps, each tap generating an output signal based on a coefficient, an input for receiving an error signal for adapting the coefficients, and an output for outputting a filtered signal; and blind error generation circuitry arranged to generate the error signal, the blind error generation circuitry including: error estimating circuitry arranged to estimate the error of the filtered signal based on maximum likelihood; and adding circuitry coupled to the error estimating circuitry and to the output of the filter and arranged to add at least part of the filtered signal to the error estimated by the error estimating circuitry to generate the error signal.

Abstract: A Decision Feedback Equalizer (DFE) capable of preventing incremental increases of a jitter of a recovered clock and reduction of a voltage margin of decided data due to delay of feedback data. The DFE includes a combiner for combining received data with feedback data and outputting the combined data as equalization data, a decision circuit for deciding recovery data by receiving the equalization data, a feedback loop for supplying the recovery data to the combiner as feedback data and a clock recovery circuit for removing a delay data component from the equalization data through the feedback loop, recovering a clock with respect to the other equalization data except the delay data component and supplying the recovered clock for decision operation of the decision circuit.

Abstract: An embodiment of the invention pertains to demodulating a data communication into a sequence of symbols. In this embodiment, a first filter generates a first convolution between a first plurality of coefficients and the data communication. The data communication is a distortion of a first sequence of symbols selected from a plurality of symbols in a constellation. A first error circuit maps the first convolution to a second sequence of symbols. An adaption circuit adjusts the first coefficients until a convergence at a last one of the symbols in the second sequence. A second filter generates a second convolution between a second plurality of coefficients and the data communication. The second coefficients are initialized to the first coefficients from the adaption circuit. A second error circuit maps the second convolution to a third sequence of symbols.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.

Abstract: A receiver for receiving a data signal having a channel profile may include an equalizer, to which the data signal is feedable, the equalizer having a plurality of filters and a switching device coupled to the filters, a selection device, which is disposed such that it determines a first number and a second number in dependence on the channel profile, and the switching device is disposed such that it connects a number of linear filters corresponding to the first number to form a first overall filter and connects a number of linear filters corresponding to the second number to form a second overall filter.

Abstract: A method, system, and computer-readable media are provided for transmitting wireless data across a coaxial cable. In one aspect, a set of computer-readable media provides a method that includes receiving a request from a mobile device for data and transmitting the data across a coaxial cable to a cable modem. The method further includes sending the data to the mobile device through a base station, wherein the base station communicates with the cable modem in order to receive the data.

Abstract: A system is provided for determining mixed-phased real time room equalization that employs crossover filters for splitting the incoming spectrum and also re-uses the cross-over filters in the equalization filter.

Abstract: This inventions provides techniques for estimating both temporal and spectral channel fluctuations with the duration of a data symbol. Certain pulse shaping functions are Discrete Prolate Spheroidal Sequences (DPSSs) and are used primarily because of their relatively limited Inter-Symbol Interference (ISI) properties. During reception, these properties allow one or more parameters of a joint time-frequency channel model to be more easily determined. Once the one or more parameters are determined, they can be applied to received symbols to correct the temporal fluctuations, spectral fluctuations, or both of the channel over which a communication took place. The techniques may be adapted for the Multiple-In, Multiple-Out communication situation.

Abstract: Method and system for adaptive signal equalizing with alternating boost and amplitude controls. In accordance with one exemplary embodiment, data signal boost control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a higher frequency, while sliced data signal amplitude control is based on measured equalized and sliced data signal energies within a bandwidth disposed about a lower frequency.

Abstract: A data transmission method in a multiple antenna system is provided. The method includes: defining a codebook including at least one precoding matrix composed of a plurality of rows and columns, wherein the codebook is at least one of a first type in which all elements of the precoding matrix are non-zero elements, a second type in which any one column of the precoding matrix includes non-zero element and the remaining columns include at least one zero element, and a third type in which all columns of the precoding matrix include at least one zero element; precoding an input symbol by using the defined codebook; and transmitting the precoded symbol.

Abstract: A correlation image detector is provided that co-registers sonar images by finding peaks in correlation images. To obtain the peaks, the mean of the absolute values of the correlation coefficients in the correlation image is found and the Rayleigh parameter is determined from the mean. Based on the Rayleigh parameter, an appropriate threshold can be determined using a desired probability of false detection. The threshold can be chosen such that the probability of a single false detection over the expected life of the mission for which correlation detection is being performed is extremely low, e.g., one in a million. The peak value in the image is determined and a correlation is considered detected when the peak value is greater than the product of the threshold and the Rayleigh parameter. If a detection occurs, the correlation image detector returns the transformation that co-registers the two images.

Abstract: A method for compensating signal distortion in an emitting payload including determining a compensation transfer function and introducing it within the aggregate response of the payload; choosing an initial tentative compensation transfer function and introducing it within the aggregate response of the payload; acquiring an output signal of the emitting payload; based on the acquired output signal and on a reference signal, corresponding to an expected undistorted output signal, performing an estimation of a residual distortion transfer function of emitting payload; and based on the estimation of the residual distortion transfer function, computing an updated tentative compensation transfer function and introducing it within the aggregate response of the payload. The estimation can be a black-box estimating and the reference signal can be generated on-purpose, and not measured from within the emitting payload.

Abstract: There is provided a transmission system and method of operating thereof. The method comprises: dividing a data sequence to be transmitted into a plurality of data blocks; encoding one or more data blocks with one or more linear systematic cyclic codes thus giving rise to encoded data blocks; transmitting said encoded data blocks over an ISI transmission channel; upon receiving, applying a linear integer-forcing (IF) equalization to the received data blocks; processing the output of the IF equalization thereby detecting for each encoded data block a valid codeword with maximal likelihood of decoding; and reconstructing the data blocks using the respective detected valid codewords.

Abstract: Methods and apparatus are provided for adaptive link partner transmitter equalization. According to one aspect of the invention, a local transceiver adapts one or more equalization parameters of a link partner by receiving a training frame over a channel between the link partner and the local transceiver, wherein the training frame is comprised of a predefined training pattern; adjusting one or more of the equalization parameters of the link partner; and determining whether the equalization of the channel satisfies one or more predefined criteria based on whether the predefined training pattern is properly received by the local transceiver. The predefined training pattern can be a pseudo random pattern, such as a PN11 pattern Noise margins and jitters margins for the channel can optionally be improved.

Abstract: An equalizer circuit receives digital amplitude data A[N] which represents the amplitude level of the N-th (N is a nonnegative integer) signal to be transmitted via a transmission line and timing data T[N] which represents the cycle of the signal, and performs waveform shaping. The equalizer circuit includes: M (M is an integer) calculation units ECU1 through ECUm; and an adder ADD1 which adds the output data of the M calculation units ECU1 through ECUM and the amplitude data A[N] together so as to generate equalized amplitude data D[N]. A step response waveform RSTEP(t) for the transmission line is approximated by Expression RSTEP(t)=SSTEP(t)·(1?Sj=1:M fj(t)) using M (M is an integer of 2 or more) functions fj(t) (1?j?M) and a step waveform SSTEP(t) with the time t as an argument. The representative value of the function fj(t) in a range between T1 and T2 is represented by a function gj(T1, T2).

Abstract: Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding.

Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: Embodiments include a decision feedback equalizer (DFE) that includes a first comparator configured to receive as inputs a soft value and a first threshold, a second comparator configured to receive as inputs the soft value and a second threshold, a selector configured to select an output of either the first comparator or the second comparator as a DFE output based on one or more previous bits output by the selector; an error calculator configured to determine an error for the first comparator and the second comparator, and a threshold adjuster configured to adjust the first threshold and the second threshold, the first threshold and the second threshold each being a non-linear combination of one or more previous outputs of the selector.

Abstract: The present invention relates to the field of communication devices, e.g. wireless communication devices. More particularly, the present invention relates to the field of signal equalization, especially minimum mean square error equalization. The present invention especially relates to an equalizer for a communication device, a method of equalizing one or more received signals and a software program product for carrying out the method. The present invention reduces the size of a look-up table needed for a division operation and, generally, provides for a reduced complexity of the equalizer and receiver.

Abstract: An inter-carrier interference (ICI) mitigating equalizer includes a channel estimator, a channel calculator, an ICI estimator, a subtracter, and an equalizer. The channel estimator estimates a channel response from a received signal, and the channel calculator calculates a basic component of a channel response and fluctuating components of the channel response from the estimated channel response. The ICI estimator multiplies the fluctuating components of the channel response by a received signal in a frequency domain, filters the multiplication results according to filter coefficients, and estimates an ICI component included in the received signal based on the filtering results. The subtracter subtracts the ICI component from the received signal in the frequency domain. The equalizer equalizes an output signal of the subtracter based on the basic component of the channel response.

Abstract: A digital communication system, an indoor unit, and an outdoor unit in which characteristic variation due to temperature is small are provided. The digital communication system comprises an IDU 1 and an ODU 6 connected through a cable 8, in which the IDU 1 includes a slope equalizer 2 which applies a given frequency characteristic to a baseband signal, a DAC 3 which converts the baseband signal from digital form into analog form, and an AGC circuit 5 which amplifies the baseband signal converted from digital form into analog form with a given amplification factor and outputs the signal to the ODU 6, and the ODU 6 includes a power detection circuit 7 which detects a length of the cable 8, determines a frequency characteristic to be applied to the baseband signal and an amplification factor according to the detected length of the cable 8 and notifies the determined frequency characteristic and amplification factor to the slope equalizer 2 and the AGC circuit 5 respectively.

Abstract: A method for delivering control information together with sampled data between a DSP and an RF/analog front-end in a high speed communication modem, which embeds sampled data and control information in frames to be transferred over one interface. A frame may comprise various fields, each may consist of one or more bytes or octets. The frame may have a data field for carrying the sampled data, and at least one control field for transferring the control information to update RF/analog front-end registers. The control field may include an octet containing a control address, an octet containing a control command, and an octet containing control data. The frame may also provide means of synchronization, e.g., by using a sync field to identify the frame boundary.

Abstract: Methods and apparatus are provided for CDR and equalization update qualification. A block of received data comprising a plurality of multiple tone patterns is processed. Equalization adaptation and/or updates to a timing recovery process can be selectively disabled if one or more of the multiple tone patterns exceed a corresponding predefined threshold.

Abstract: A multi-mode transmitter within an integrated circuit device. The multi-mode transmitter transmits a first data sequence in a baseband signal when a first transmission mode is enabled, and transmits the first data sequence in a multi-band signal when a second transmission mode is enabled.

Abstract: An adjustable equalizer that includes a first branch including a low pass filter (LPF) and having a variable gain (?), and a second branch including a high pass filter (HPF) and having another variable gain (?). The equalizer can be implemented using CMOS technology so that the gain parameters ? and ? are independently adjustable and the equalizer is capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. In some embodiments, the equalizer includes two differential pairs of MOS transistors and a controllable current source determines the tail current for each differential pair. When the equalizer includes purely resistive impedances Z0 and Z1, the equalizer's transfer function is Z1/Z0·(?+?·(1+s·C0·Z0)), where ? is a gain parameter determined by the tail current of one differential pair and ? is a gain parameter determined by the tail current of the other differential pair.

Abstract: The present invention relates to an apparatus and method of estimating a channel based on a channel delay spread in a mobile communication system. Pilot subcarriers are inserted between data subcarriers at predetermined intervals to estimate a channel at locations of the pilot subcarriers. An approximate channel delay spread value is estimated by using an autocorrelation value of a pilot signal. Then, a channel for data subcarriers between the pilot subcarriers is estimated by using a Wiener finite impulse response (FIR) filter that has a separate coefficient according to the estimated delay spread value. Accordingly, by changing the Wiener FIR filter coefficient according to the delay spread value of the channel, it is possible to estimate the channel so as to be adaptive for a change of the channel over time. Since the filter coefficients, which are calculated in advance, are used, it is possible to reduce the amount of calculation required when calculating the filter coefficients.

Abstract: In a transmission diversity control method in which a request to start or stop transmission diversity is issued by a reception station to a transmission station having a transmission diversity function, the reception station is provided with an equalizer to reduce multipath interference on the basis of a signal correlation, a transmission diversity start request is issued from the reception station to the transmission station when an effect generated by the equalizer is small, and a transmission diversity stop request is issued from the reception station to the transmission station when the effect generated by the equalizer is large.

Abstract: An adaptive equalizer includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a modulation signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

Abstract: A technique for determining a frequency offset between components of a communication network based on a Constant Amplitude Zero Auto-Correlation (CAZAC) sequence is described. A method implementation of this technique comprises a provision of a set of correlation signals at different frequencies, with each correlation signal being indicative of a specific frequency offset hypothesis and comprising the CAZAC sequence. Once a synchronization signal comprising the CAZAC sequence is received, this synchronization signal is correlated with each of the correlation signals to obtain a correlation result for each frequency offset hypothesis. In a next step, at least one of the frequency offset hypotheses is selected based on a comparison of the correlation results. The frequency offset may then be determined based on the at least one selected frequency offset hypothesis.

Abstract: Embodiments of a broadcast receiver and method for optimizing a scale factor in a log-likelihood ratio (LLR) mapper are generally described herein. In some embodiments, the broadcast receiver includes an LLR mapper to generate LLRs from demodulated data samples, a low-density parity-check (LDPC) decoder to generate decoded data from the LLRs, and an LLR optimizer to dynamically select a scale factor for the LLR mapper based on a number of iterations for convergence of the LDPC decoder. In some embodiments, the LLR optimizer iteratively revises the scale factor during receipt of broadcast signals until the number of iterations of the iterative decoder is either minimized for convergence or minimized for convergence failures.

Abstract: A device that detects an effect which distorts a communication signal in a serial communication channel comprises an input, a detector connected to the input, a demultiplexer having a data input connected to the output of the detector, and an evaluator at each output of the demultiplexer. The input receives the distorted communication signal from the communication channel. The detector detects a feature in a symbol of the distorted communication signal and outputs the detected feature. The demultiplexer outputs the detected feature and has a plurality of control inputs. A differently delayed symbol (i?1, 1, i+1) of the communication signal is applied to each input to switch the detected feature present at the input of the demultiplexer to an output of the demultiplexer specified by the symbols present at the control inputs.

Abstract: A system for filtering a data signal includes an input configured to receive the data signal through a transmission medium and a filter configured to remove distortion from the received data signal using equalization coefficients. The system further includes a processing unit configured to determine dynamically the equalization coefficients of the filter without using a predetermined training pattern in the received data signal.

Abstract: In an embodiment, set forth by way of example and not limitation, a receiver with automatic gain includes a receiver stage, an AGC stage, and a digital processor which collectively define an AGC loop. Preferably, the AGC stage has a control circuit and a feedback circuit with matched transfer characteristics. A digital processor is operative to develop a gain control signal to set a desired gain level of the receiver stage to an optimal level based upon a waveform analysis derived from the gain feedback signal.

Abstract: A method and apparatus are provided for determining a plurality of filter tap weights or biases (or both) for a noise predictive filter used to generate one or more signal dependent branch metrics. A filter tap weight or filter bias (or both) are adaptively accumulated for each possible data condition. The data conditions may comprise, for example, each possible data pattern for a given data dependency length. The appropriate accumulated filter tap weight or bias to update can be selected based on a data condition associated with the current received data. The filter tap weights associated with a delay 0 tap can be adapted for each filter condition except for a single normalizing condition, whose corresponding delay 0 tap remains fixed.

Abstract: Embodiments of the present invention disclose an electronic equalization and electronic depolarization method, a receiving end equipment, and a communication system. According to the embodiments of the present invention, parameters required by electronic equalization and electronic depolarization are calculated by detecting a Synchronization Sequence (SS) in a received signal, and then the electronic equalization and the electronic depolarization are performed on the received signal in a frequency domain by utilizing the parameters, so as to solve a problem of the electronic equalization and the electronic depolarization in a Polarization Division Multiplexing (PDM) Orthogonal Frequency Division Multiplexing (OFDM) system. Furthermore, the realization complexity of the electronic equalization and the electronic depolarization performed in the frequency domain is greatly reduced relative to the electronic equalization and the electronic depolarization performed in a time domain.

Abstract: The invention discloses a double-estimation channel estimator for calculating a plurality of accurate channel responses from a plurality of synchronization signals. The channel estimator includes a first channel estimator, a second channel estimator, a first equalizer, and a calculation module. The first channel estimator calculates first channel responses according to a plurality of pilot signals and the synchronization signals. The first equalizer calculates first equalization signals according to the first channel responses and the synchronization signals. The second channel estimator calculates second responses according to the first equalization signals and the synchronization signals. Then the calculation module calculates third channel responses according to the first channel responses and the second channel responses.

Abstract: In accordance with the present invention, novel methods for adaptive receiver design and related parameter estimation techniques for efficient and non-coherent reception of ultrawideband signals are presented. Efficient estimation of maximum excess delay of the channel for enabling many useful adaptation techniques is additionally provided. Also, noise power estimation which significantly improves the performance of the receivers is presented.

Abstract: Methods and apparatus to provide an equalizer for analog adaptive control are disclosed. An example equalizer described herein includes a high frequency amplifier to receive an input signal and to amplify a high frequency portion of the input signal, a low frequency amplifier to receive the input signal and to amplify a low frequency portion of the input signal, and a weight factor controller to control a gain of the high frequency amplifier and a gain of the low frequency amplifier.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: An apparatus and method for correcting IQ imbalance are presented. An exemplary receiver for processing I and Q signals from a tuner includes: a non-decision directed (NDD) imbalance canceller coupled to receive the I and Q signals, and a decision directed (DD) imbalance canceller coupled to the non-decision directed imbalance canceller. The DD imbalance canceller converges after the NDD imbalance canceller converges, so as to correct IQ imbalances in the receiver. An exemplary method for processing I and Q signals from a tuner includes: (a) converging a NDD imbalance canceller to correct a majority of IQ imbalances, and (b) subsequently converging a DD imbalance canceller to correct a remainder of IQ imbalances not corrected in step (a). The apparatus and method correct frequency-dependent and frequency-independent IQ imbalances.

Abstract: Adaptation convergence in an adaptive dispersion compensation engine (ADCE) of a high-speed serial interface is detected by monitoring the output of the error amplifier of one or more adjustment loops of the ADCE. Adaptation convergence is considered to have been detected upon detection of a predetermined number of transitions in the error amplifier output, each of which occurs within a preselected interval following the previous transition. The detector may be implemented with a timer that times the preselected interval and a counter that counts transitions in the error amplifier output. The timer restarts each time a transition occurs, and the counter outputs a convergence signal when it reaches the predetermined number, but is reset each time the timer reaches the preselected interval. The serial interface may be part of a programmable integrated circuit device and in any case the preselected interval and the predetermined number may be programmable.

Abstract: A single-carrier/multi-carrier community receiver includes a discrete Fourier transform unit, a frequency-domain equalizer, an inverse discrete Fourier transform unit and an inter-symbol interference (ISI) cancellation unit. The discrete Fourier transform unit is utilized for executing a discrete Fourier transform upon a received signal to generate a frequency-domain signal. The frequency-domain equalizer is utilized for executing an equalization operation upon the frequency-domain signal to generate a frequency-domain equalized signal. The inverse discrete Fourier transform unit is utilized for executing an inverse discrete Fourier transform upon the frequency-domain equalized signal to generate a time-domain equalized signal. The ISI cancellation unit is utilized for executing an ISI cancellation operation upon the time-domain equalized signal to generate an ISI-cancelled signal.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has eleven register stages with a generator polynomial for the linear feedback shift register of R?i[10]=R?i-1[0]?R?i-1[2], and the permutation code forms, with an additional bit, a twelve bit address.