Abstract: A reception device includes: a reception unit which receives transmission data from an imaging device, the imaging device performing imaging processing at prescribed intervals, generating image data, packetizes the image data to create the transmission data, and transmitting the transmission data; a display processing unit which performs display processing of generating a display signal from the transmission data; a measurement unit which extracts a specific packet from the transmission data, measures a difference between prescribed reference timing generated at intervals in relation to display of the display signal and reception timing of the specific packet multiple times, and generates an estimated imaging timing signal in which operation timing of the imaging processing is estimated, based on the measurement result; and a processing unit which synchronizes the imaging processing and the display processing so as to be a prescribed phase with each other using the estimated imaging timing signal.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a phase-controlled clock signal to achieve phase-locking with a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking with the reference clock signal. The processor is also configured to monitor a deviation between the frequency and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with, or on the basis of, the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.

Abstract: A clock phase interpolator includes: a phase interpolation processing circuit configured to generate an interpolated clock signal whose phase is interpolated from a plurality of operation clock signals having different phases; a band adjustment element coupled to the phase interpolation processing circuit, and configured to adjust an operational frequency band of the phase interpolation processing circuit by changing a setting value of itself; and a control circuit coupled to the phase interpolation processing circuit, and configured to detect a transition state for a reference clock signal of the interpolated clock signal, and configured to control the setting value of the band adjustment element on the basis of the detected transition state.

Abstract: Interpolator and decimator apparatuses and methods are improved by the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data.

Abstract: A method for operating a device in a wireless communication system supporting Device to Device (D2D) communication system includes receiving a reference signal from each of at least one transmitting device, estimating a frequency offset between the reference signals and a comparison reference signal corresponding to the reference signals, and adjusting a transmit frequency of a voltage controlled oscillator of the device using the estimated frequency offset estimation. An apparatus for compensating for a frequency offset of a device in a wireless communication system supporting Device to Device (D2D) communication system includes a frequency offset estimator configured to receive reference signals from each of at least one transmitting device, and estimating a frequency offset between the reference signals and a comparison reference signal corresponding to the reference signals, and a voltage controlled oscillator configured to adjust a transmit frequency using the estimated frequency offset.

Abstract: An apparatus for correcting a signal, includes a correction value calculator that determines a transmission distance of a transmission path through which a timing signal is propagated, the timing signal having a periodically changing frequency, and determines a deviation between a frequency of the timing signal and a frequency of received data, as a correction value, from the transmission distance; and a corrector that corrects the frequency of the timing signal by the correction value for synchronizing transmitted data with the timing signal.

Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches.

Abstract: An apparatus includes a first clock source, a second clock source and circuitry configured to supply a clock signal to a circuit. The circuitry operates to change the clock signal from one frequency to another different frequency. This change is made in a manner whereby no clock signal is supplied during a period of time when the change from the one frequency to the another different clock frequency is being made.

Abstract: A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes.

Abstract: A method for demodulating a radio frequency signal according to one embodiment includes receiving digital signals derived from a radio frequency signal; converting the digital signals to baseband signals; generating a frequency error signal using the baseband signals during an acquisition period; and shifting a frequency of the digital signals towards zero frequency error during the acquisition period using the frequency error signal, with the proviso that the digital signals are not phase locked during the shifting. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Abstract: The present disclosure relates to a frequency difference detection device that can synchronize oscillation frequency with a master device in a network with high precision, and also relates to a frequency difference detection method and a program. A frequency difference detection device, as one aspect of the present disclosure is a frequency difference detection device that detects a difference in oscillation frequency between a master device and a slave device connected to each other via a network.

Abstract: In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.

Abstract: A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device.

Abstract: Devices, methods, and other embodiments associated with phase based preamble detection are described. In one embodiment, an apparatus includes a wireless transceiver, an evaluation logic, and a configuration logic. The wireless transceiver receives a wireless signal from a wireless device. The wireless signal includes a preamble sequence. The evaluation logic evaluates the preamble sequence by comparing phases of the preamble sequence to phases of predefined preamble sequences to identify a matching preamble sequence. The comparison is done without using amplitude information. The configuration logic configures the wireless transceiver to synchronize wireless communications with the wireless device based, at least in part, on the matching preamble sequence.

Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.

Abstract: A transmitter comprises resource mapping circuitry configured to map symbols from multiple control channels to transmission symbols in a base station of a wireless system. The resource mapping circuitry comprises a table-based mapper configured to receive the control channel symbols and to map those symbols to the transmission symbols utilizing at least a selected one of a plurality of tables providing respective distinct mappings between the control channel symbols and the transmission symbols. For example, each of the transmission symbols may comprise a plurality of resource groups and the tables may specify distinct mappings of the control channels symbols to resource groups for different sets of possible base station parameter values. In one embodiment, the control channels comprise a physical control format indicator channel (PCFICH), a physical downlink control channel (PDCCH), and a physical hybrid ARQ indicator channel (PHICH) of an LTE cellular system.

Abstract: A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter.

Abstract: Disclosed is an apparatus and method for detecting a code. The code detecting apparatus may include a detector to detect symbol synchronous timing information associated with a PSS code from a first signal received during a predetermined first period, a compensator to extract and buffer the PSS code and the SSS code based on the symbol synchronous timing information detected from a second signal received during a predetermined second period, and compensate for a frequency offset with respect to the buffered PSS code, and a processor to re-detect the symbol synchronous timing information based on the PSS code in which the frequency offset is compensated for, and extract the buffered SSS code using the re-detected symbol synchronous timing information.

Abstract: A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.

Abstract: A repeater using a digital filter is disclosed. The repeater comprises a MUX filter for filtering an RF signal received through an antenna or a signal to be transmitted through the antenna; a low noise amplifier for lowering noise of the signal filtered by the MUX filter; a down converter for converting the signal outputted from the low noise amplifier into an IF band signal to digitalize the signal; a digital filter for filtering the digital signal outputted form the down converter based on parameters inputted by a user; a filtering controller for controlling the digital filter by using a filtering coefficient calculated based on the parameters; an up converter for converting the signal filtered by the digital filter into an RF band signal; and a high power amplifier for amplifying the signal outputted from the up converter to a high power signal.

Abstract: An apparatus and method for inserting delay into a start signal of a metastable ring oscillator chain-based time-to-digital circuit (TDC). Included therein is a signal generating circuit that generates the start signal, a plurality of carry elements connected as a chain, each of the carry elements having an input to receive a stop signal, a delay chain circuit including one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs each provided in a respective one of the delay modules. The delay chain circuit generates an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay. The delay chain circuit additionally provides the selected amount of delay to the signal generating circuit, which incorporates the delay into the start signal.

Abstract: A system including a differential demodulation module that generates differentially demodulated signals based on having differentially demodulated received signals. A first summing module generates a combined signal, including a plurality of symbols, by adding the differentially demodulated signals. A second summing module generates a plurality of sums for each of a plurality of derived preamble sequences, which are derived from preamble sequences. Each of the derived preamble sequences includes a plurality of derived symbols. One of the plurality of sums generated for one of the derived preamble sequences is a sum of a first portion of one of the plurality of symbols of the combined signal and a second portion of one of the derived symbols of the one of the derived preamble sequences.

Abstract: According to one embodiment, a channel phase estimation apparatus includes a phase memory, subtractor, multiplier, and adder. The phase memory is configured to store a first phase estimation value up to a (k?1)-th (for k=1, 2, . . . , K) symbol. The subtractor is configured to calculate a difference value between a phase value of one carrier of a k-th symbol and the first phase estimation value. The multiplier is configured to multiply the difference value by a weight. The adder is configured to add a value output from the multiplier and the first phase estimation value to output a second phase estimation value up to the k-th symbol.

Abstract: A symbol clock recovery circuit is provided for a data communication system using coherent demodulation. The symbol clock recovery circuit comprises an analog-to-digital converter comprising a first input for receiving a coherent-detected baseband analog signal derived from a carrier signal, a second input for receiving an adapted symbol clock signal, and an output for outputting a digital signal comprising a frame having a preamble with at least two symbols. The symbol clock recovery circuit comprises further a phase shifting unit comprising a first input for receiving a symbol clock signal derived from the carrier signal, and a timing detector, comprising a first input for receiving the digital signal from the analog-to-digital converter and an output for providing a signal comprising information about an optimum sample phase to the phase shifting unit.

Abstract: A source-synchronous capture unit on a receiving circuit includes a first first-in-first-out (FIFO) unit operable to synchronize a write enable signal to generate a synchronized write enable signal that is synchronized with a first free running clock associated with a memory external to the receiving circuit. The write enable sign is generated in response to a read operation by the receiving circuit. The source-synchronous capture unit also includes a second FIFO unit operable to store data from the memory in response to the first free running clock and the synchronized write enable signal, and to output the data in response to a second free running clock associated with the receiving circuit and a read enable signal.

Abstract: It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol.

Abstract: Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal, and using the second clock signal to drive software timer logic and generate media timestamps.

Abstract: An automatic calibration of a clock of a wireless portable part with respect to a clock of a fixed part in a field environment. The calibration performed in the field environment negates the need to calibrate the clock during manufacture and negates the need for an initial field recalibration because of temperature differences between manufacture and the field. In performing the calibration the frequency of the clock of the portable part is varied until the portable part is synchronous with the fixed part to with in a range of timing bits. The portable part is declared calibrated after remaining calibrated for a defined number of data frames.

Abstract: In a wireless 802.15.4 communication system (300), a high-speed data frame structure (340) is provided which uses the 802.15.4 SHR structure that is spread modulated to obtain the synchronization benefits of the 802.15.4 protocol, but which uses a modified data frame structure for the payload portion without using spreading to thereby improve its transmission efficiency. The transmission efficiency can be further increased by increasing the size of the data payload (and correspondingly, the frame length size).

Abstract: Motor control circuits and associated methods to control an electric motor provide a plurality of drive signal channels at the same phase, resulting in reduced jitter in the rotational speed of the electric motor.

Abstract: A data transmission system includes a plurality of signal lines, a signal line determination unit, and a data transmission unit. The plurality of signal lines transmit data transmitted from a transmission-side device to a reception-side device. The signal line determination unit determines which signal line among the signal lines is used to transmit reception adjustment data to the reception-side device. The data transmission unit uses the signal line determined by the signal line determination unit to transmit the reception adjustment data to the reception-side device and uses another signal line to transmit transmission data to the reception-side device.

Abstract: A synchronization control apparatus is included in an arithmetic processing device. The arithmetic processing device is connected to another arithmetic processing device via a data transfer device. The synchronization control apparatus is connected to a clock divider which divides an input clock signal into N. In the synchronization control apparatus: a detecting unit detects the rising or the falling of a divided clock signal; a monitoring unit monitors the elapsed time since the rising or the falling of the divided clock signal; a clock generating unit generates a control clock by multiplying the divided clock signal by N; a synchronization request receiving unit receives a synchronization request from the other arithmetic processing device; a clock control unit outputs the control clock; a synchronization request sending unit sends a synchronization request to the other arithmetic processing device via the data transfer device.

Abstract: A transmitter includes an amplitude adjustment unit multiplying an amplitude adjustment sequence value for adjusting amplitude with a synchronization channel transmitted from a base station for establishing synchronization with a mobile station.

Abstract: A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter unit to provide filtering of noise on a phase control signal to substantially reduce a false delay lock loop state.

Abstract: A method of frame sync detection is described. A first and second differential correlation of a data stream is calculated, at a plurality of delay and conjugate multipliers. The first and second differential correlations are convolved with a previous set of differential correlations. A correlation peak is calculated, at a sync detector, using the convolved differential correlations, to detect a frame sync.

Abstract: A method and an apparatus for clocking data processing modules, with different average clock frequencies and for transferring data between the modules are provided. The apparatus includes a device for providing a common clock signal to the modules. Clock pulses are deleted from the common clock signal to individual modules in dependence on the clocking frequency required by each module. The clock pulses are applied to the modules between which the data is to be transferred at times consistent with the data transfer.

Abstract: A transmitter includes a synthesis filter bank to spread a data symbol to a plurality of frequencies by encoding the data symbol on each frequency, apply a common pulse-shaping filter, and apply gains to the frequencies such that a power level of each frequency is less than a noise level of other communication signals within the spectrum. Each frequency is modulated onto a different evenly spaced subcarrier. A demodulator in a receiver converts a radio frequency input to a spread-spectrum signal in a baseband. A matched filter filters the spread-spectrum signal with a common filter having characteristics matched to the synthesis filter bank in the transmitter by filtering each frequency to generate a sequence of narrow pulses. A carrier recovery unit generates control signals responsive to the sequence of narrow pulses suitable for generating a phase-locked loop between the demodulator, the matched filter, and the carrier recovery unit.

Abstract: The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.

Abstract: The invention relates to a method for wire bound, high precision, temporal synchronization of measured value acquisition in a measurement system designed as a space coordinate measurement apparatus having a plurality of measurement sub-units with signaling of a time for triggering the measured value acquisition by means of a trigger signal and with the respective acquisition and intermediate storage of a measured value in the measurement sub-unit at the time determined by the trigger signal. Each acquisition of the measured value is carried out in the measurement sub-units in a time quantified manner with a local timing signal of the measurement sub-unit.

Abstract: Certain aspects of the present disclosure relate to a technique for constructing a short training field (STF) sequence of a Very High Throughput (VHT) preamble in an effort to reduce a peak-to-average power ratio (PAPR). The constructed STF sequence may feature a specific repetition period.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: In a method for decoding plurality of information streams corresponding to a plurality of layers, where the plurality of information streams have been transmitted via a multiple input multiple output (MIMO) communication channel, a plurality of received signals are processed to decode information corresponding to a first layer. A plurality of modified received signals are generated using the decoded information corresponding to the first layer and the plurality of received signals. Bit metric values are generated for a second layer using MIMO maximum likelihood (ML) demodulation and using the plurality of modified received signals and channel and modulation information for interfering signals. Information corresponding to the second layer is decoded using the generated bit metric values.

Abstract: A serial-format data signal is input to a data input terminal. Each of n (n represents an integer of two or more) multiple clock input terminals is configured to receive a clock signal as an input signal. An input flip-flop latches the data signal at each timing that corresponds to the corresponding clock signal. A serial/parallel converter converts the serial-format data signal into a parallel-format intermediate data signal using the corresponding clock signal. A data selector selects one from among the n intermediate data signals according to a selection signal.

Abstract: A multi-tone transceiver including: a transform component, a tone selector, an error detector, an aggregator and an oscillator. The transform component transforms received communications from the time domain to the frequency domain. The tone selector selects a sub-set of the received tones which exhibit an elevated signal-to-noise ratio (SNR) as a clock recovery tone set (CRTS) and drops and add tones to the CRTS as required by changes in the SNR of the individual tones. The error detector detects phase errors in each received tone of the CRTS. The aggregator calculates an average aggregate phase error from all tones in the CRTS. The oscillator controls clocking of the transceiver. The oscillator is responsive to the average aggregate phase error to adjust a clock phase in a direction which reduces a phase error with a clock on the opposing transceiver.

Abstract: Synchronization for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system whose radio receiver receives periodic transmissions, includes receiving periodic transmissions; turning on a radio receiver for a limited time to detect an expected message; if an expected message is not found, turning off the receiver and turning it on again after a time asynchronous with the transmission period; and after finding an expected message, waiting for the period of the transmissions less the length of an expected message and then looking for a synchronization symbol in the expected message and synchronizing subsequent actuation of the receiver using that synchronization symbol.

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit in accordance with an embodiment of the present invention uses a hybrid phase detector that is constituted by including a linear phase detector and a binary phase detector. Since the clock and data recovery circuit basically is constituted with the linear phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a D flip flop to recover clock and data, a phase detector gain is irrelevant to the jitter of received data and recovered clock, and it is possible to make a fine adjustment of the size of up/down currents of the charge pump using the binary phase detector and a charge pump controller, thereby compensating a phase offset between the received data and the recovered clock.

Abstract: A video transmission method is provided, which includes receiving state information from at least one mobile terminal that intends to perform a video stream service through a wireless network, determining a size of an image by selecting a specified spatial layer bit stream on the basis of the state information of the mobile terminal from a plurality of spatial layer bit streams generated at different bit rates during encoding of the bit stream, selecting a specified time and an SNR layer bit stream by increasing or decreasing time of the image and a layer position of the SNR layer bit stream on the basis of network parameters included in the state information of the mobile terminal, and transmitting the bit stream generated by extracting the specified layer bit stream of the selected layer to the mobile terminal.

Abstract: A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase.

Abstract: A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase.