Abstract: A method of frame sync detection is described. A first and second differential correlation of a data stream is calculated, at a plurality of delay and conjugate multipliers. The first and second differential correlations are convolved with a previous set of differential correlations. A correlation peak is calculated, at a sync detector, using the convolved differential correlations, to detect a frame sync.

Abstract: The present invention relates to a method for improving synchronization and information transmission in a communication system, including: generating a signal with a time symmetric property based on a uniquely identifiable sequence c(l) from a set of sequences, sending the signal over a communication channel, receiving the signal, calculating and storing a correlation, finding the delay that result in a maximum correlation magnitude, detecting the unique sequence c(l) from the set of sequences. The method is distinguished by: generating the signal with a centrally symmetric part, s(k), the centrally symmetric part s(k) being symmetric in the shape of the absolute value thereof, storing the reverse differential correlation D(p) from a block of N received signal samples r(k), k=0, 1, . . . , N?1. The present invention also relates to a transmitter unit and a receiver unit of a communication system, and a radio communication system.

Abstract: The present invention relates to signal transmitting/receiving apparatuses. The signal transmitting apparatus includes an inverse discrete Fourier transform module, a cyclic prefix adding module, a preamble adding module, and a digital-analog converting module. The inverse discrete Fourier transform module receives modulated data, performs inverse discrete Fourier transform, and generates a first symbol. The cyclic prefix adding module adds a predetermined cyclic prefix to the first symbol, and generates a second symbol. The preamble adding module adds a predetermined preamble to the second symbol, and generates a third symbol. The digital-analog converting module converts the third symbol including the cyclic prefix and the preamble into an analog symbol.

Abstract: A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to share an oscillator as so to perform two-stage clock frequency resolution calibrations for generating different frequency-tuning ranges. This can bring an optimal frequency resolution and greatly reduce system complexity and save element cost.

Abstract: A differential receiver which provides for estimation and tracking of frequency offset, together with compensation for the frequency offset. Estimation and tracking of the frequency offset is undertaken in the phase domain, which reduces computational complexity and allows frequency offset estimation and tracking to be accomplished by sharing already-existing components in the receiver. Compensation for the frequency offset can be performed either in the time domain, before differential detection, or in the phase domain, after demodulation, or can be made programmably selectable, for flexibility.

Abstract: Provided is a correlation scheme selecting apparatus and method that can acquire initial synchronization efficiently by calculating frequency error criterion threshold between correlation schemes and selecting a correlation scheme for each region when a correlation value is calculated for initial sync in a communication system with carrier frequency errors. The method for selecting a correlation scheme based on a carrier frequency error includes: calculating mis-detection probability values based on a normalized frequency offset for each correlation scheme; determining as a frequency-error criterion threshold a crossing point of graphs of the calculated mis-detection probability values for each correlation scheme; and selecting a correlation scheme based on the determined frequency-error criterion threshold.

Abstract: A receiver circuit in each branch has an FFT unit that performs Fourier transform on OFDM signals. A slave branch FFT window control unit determines whether an undesired wave is a preceding wave or a delay wave, and notifies a master branch of the result. In response to the notification from the slave branch, a master branch FFT window control unit controls a position of an FFT window that indicates a time range in which Fourier transform is performed on OFDM signals.

Abstract: An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range.

Abstract: A high speed transceiver without using an external clock signal and a communication method used by the high speed transceiver which applies a clock recovery circuit including a coarse code generator, a frequency detector, and a linear phase detector to the receiver so as to solve problems such as skew between a reference clock and data that may occur during data transmission and jitter of a recovered clock while an embedded clock method of applying clock information to data is used.

Abstract: A communication apparatus having a first and second wireless communications modules is provided. The first wireless communications module includes a receiving unit receiving RF signals from an air interface, a signal processing module performing frequency down conversion on the RF signals to generate baseband signals according to a clock signal, and a processor processing the baseband signals. The processor further detects an ON/OFF status of the second wireless communications module to obtain a detection result and compensates for frequency drift of the clock signal according to the detection result.

Abstract: A data clock frequency divider circuit includes a training decoder and a frequency divider. The training decoder outputs a clock alignment training signal, which is indicative of the start of a clock alignment training, in response to a command and an address of a mode register set. The frequency divider, which is reset in response to an output of the training decoder, receives an internal data clock to divide a frequency of the internal data clock in half. The data clock frequency divider circuit secures a sufficient operating margin so that a data clock and a system clock are aligned within a pre-set clock training operation time by resetting the data clock to correspond to a timing in which the clock training operation starts, thereby providing a clock training for a high-speed system.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.

Abstract: A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The method further includes coding the periodic square wave LO signal of the first phase and the periodic square wave LO signal of the second phase synchronously with the chopping signal to generate a first set of synchronized signals (116, 118) and a second set of synchronized signals (120, 122), respectively. A phase difference between the first phase and the second phase is a predefined value. The RF signal is processed with the first set of synchronized signals (116, 118) and the second set of synchronized signals (120, 122) to obtain an in-phase intermediate frequency (IF) signal (132) and a quadrature-phase IF signal (142), respectively.

Abstract: A transponder includes a CDR section that extracts clocks from an input signal, an oscillating section that can output various frequencies to the CDR section, a frequency instruction processing section that instructs the oscillating section to output an arbitrary frequency, a detection processing section, and a frame processing section control section. The detection processing section determines whether the frequency output from the oscillating section and an input signal synchronize in frequency or not in response to an instruction by the frequency instruction processing section, and detects a synchronization frequency. The frame processing section control section operates a frame processing section based on the synchronization frequency detected by the detection processing section.

Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.

Abstract: A clock data recovery comprises a phase detector, a phase interpolator, an initial phase detector, and an initial phase decoder. The phase detector receives an incoming data stream and an interpolated clock signal and output an early/late value indicating timing relationship between the incoming data stream and the interpolated clock signal. The phase interpolator receives the early/late signal and at least one reference clock signal and generate an interpolated clock signal considering the early/late value and the at least one reference clock signal. The initial phase detector receives the incoming data stream and output a first data indicating a phase of the incoming data stream. The initial phase decoder receives data indicating a phase of the incoming data stream and select the at least one reference clock signal from a plurality of clock signals considering the data indicating a phase of the incoming data stream.

Abstract: A synchronizer circuit and method for transferring data between mutually asynchronous source and destination clock domains. An input synchronizer cell clocked at an input clock frequency receives input data from the source domain and produces a corresponding intermediate signal. A frequency divider produces a divided clock signal whose frequency is equal to the input clock frequency divided by an integer. An output synchronizer module comprises first and second cascaded synchronizer cells clocked at the divided clock frequency, receives the intermediate signal and produces a corresponding output signal for the destination clock domain.

Abstract: The present invention is an improved system and method for detecting the leading edge of a waveform. More specifically, the invention relates to detecting the leading edge of an ultra wideband waveform. The invention requires locking to the ultra wideband waveform at a lock reference time, and sampling the ultra wideband waveform during one or more time windows relative to the lock reference time to identify one or more leading edge candidate times based on one or more detection criterion. The ultra wideband signal is sampled at a band limited Nyquist rate that avoids aliasing within a band of interest of the ultra wideband waveform, but allows aliasing outside of the band of interest to minimize the number of samples for leading edge detection processing.

Abstract: An apparatus and method is disclosed for synchronizing a timing signal for a computational system to different reference clock signals without impairing the operation of the computational system. A corresponding “offset” register is provided for each of the reference clock signals (RCS) for storing signal timing differences between the timing signal and RCS. When one of the reference clock signals not used for synchronizing the timing signal, is selected as the signal for synchronizing the timing signal, the corresponding offset register R0 (for the newly selected reference clock signals) retains its last value prior to the switch, and another register R1 stores subsequent signal timing differences between the timing signal and the newly selected reference clock signals.

Abstract: A method for clock monitoring in a network is provided. The method comprises receiving a first network clock signal at a network device and comparing the first network clock signal to a local clock signal from a primary oscillator coupled to the network device.

Abstract: A signal processing circuit detects a pulsative change point of an input signal and sets a phase point which is shifted by a predetermined phase difference from the detected pulsative change point of the input signal as the timing for sampling the input signal.

Abstract: One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data stream that is converted into a parallel data stream by a demultiplexer inside the SerDes. The parallel data is stored in a bit logic unit that compares the parallel data to a second parallel data obtained in similar fashion in another SerDes from a second input signal. The time between the two pulses is then calculated as the number of cycles in the serial data stream that corresponds to the number of bits between the positions of the two events.

Abstract: In a multivalue modulation type with one pilot symbol inserted for every 3 or more symbols, signal points of each one symbol immediately before and after a pilot symbol are modulated using a modulation type different from that for pilot symbols. In this way, it is possible to suppress deterioration of the accuracy in estimating the reference phase and amount of frequency offset by pilot symbols and improve the bit error rate characteristic in the signal to noise ratio in quasi-coherent detection with symbols whose symbol synchronization is not completely established.

Abstract: The present invention provides methods and systems for allowing a receiver in a (wireless) communication system to synchronize its timing and frequency subsystems in accordance with a received signal. In accordance with one aspect, a method is provided in which a relative time of arrival of sync values provided in a received signal are determined and used to align the receiver's reference signal(s) accordingly. Other aspects of the invention will become apparent from the detailed description of exemplary embodiments that follows.

Abstract: A method for jam setting an initial frequency of a data clock recovery loop according to one embodiment includes generating a frequency error signal in a frequency error detector from sideband signals within a backscattered radio frequency signal, wherein the frequency error accumulates in a frequency error filter coupled to an output of the frequency error detector; at about an end of an acquisition period, freezing the accumulated frequency error in the frequency error filter; and using the frozen accumulated frequency error to jam set an initial frequency of a data clock recovery loop. Such methodology may also be implemented as a system using logic for performing the various operations. Additional systems and methods are also presented.

Abstract: Systems and methods providing clocking between various components or sub-components are shown. Embodiments implement an implied clock technique which reduces the number of signal lines, signaling overhead required for an encoded clock signal, and/or and power consumption for a high speed communication link. In accordance with embodiments efficient communication is provided between a core device and a remote device by the core device providing both clock and data signals to the remote device and the remote device providing a data signal at a predetermined clock rate without communicating its clock signal. The core device of this embodiment determines an “implied clock” suitable for accurately receiving data from the remote device.

Abstract: A clock synchronization buffer for a counter clock flow pipelined circuit including a cascade of processing modules that receive data from a previous module and provide output results to a following module. The clock synchronization buffer receives a clock input signal and provides clock signals to a local processing module and to the next pipeline stage. The clock synchronization buffer includes a selectable delay stage that receives a clock input signal and a delay select signal and outputs a clock signal having a selected delay. An amplifier connected to the selectable delay stage provides the delayed clock signal to a local processing module that corresponds to the clock synchronization buffer circuit. An inverting amplifier connected to the selectable delay stage provides the delayed clock signal to the next pipeline stage. A clock synchronization controller synchronizes the phases of reference clock input and synchronized clock input signals.

Abstract: A network node, a communication system, and a method for transmitting a clock packet through a tunnel are disclosed. The method includes: encapsulating a tunnel ingress clock packet received at an ingress of a tunnel in an encapsulation mode corresponding to the tunnel, and performing clock correction for the encapsulated clock packet; and sending the corrected clock packet to an egress of the tunnel. The network node for processing a clock packet includes an encapsulating module and a sending module. The communication system includes the network node for processing a clock packet, and further includes an intra-tunnel network node and a tunnel egress network node. According to the present invention, a clock packet is re-encapsulated and transmitted through a tunnel. In the subsequent process of transmitting the clock packet transparently, the node itself serves as a clock reference point, and all network nodes do not need to synchronize time absolutely.

Abstract: A method and an apparatus for new cell identification in a WCDMA network with a given neighbor set are described. Aspects of a system for new cell identification in a WCDMA network with a given neighbor set may include a baseband processor that enables determination of a primary synchronization position and at least one scrambling code based on received configuration information from one or more base stations. The baseband processor may also enable determination of a slot boundary in at least one signal received from the one or more base stations based on the determined primary synchronization position. The system may also include a multipath detector that enables unscrambling of the received at least one signal based on the determined slot boundary and at least a portion of the one or more scrambling codes.

Abstract: Improved interpolator and decimator apparatus and methods, including the addition of an elastic storage element in the signal path. In one exemplary embodiment, the elastic element comprises a FIFO which advantageously allows short term variation in sample clocks to be absorbed, and also provides a feedback mechanism for controlling a delta-sigma modulated modulo-N counter based sample clock generator. The elastic element combined with a delta-sigma modulator and counter creates a noise-shaped frequency lock loop without additional components, resulting in a much simplified interpolator and decimator.

Abstract: A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training sequence header pattern. Based on each of the first data frames, the plurality of serial lane transceivers de-skew a plurality of data frames and generate a plurality of event signals. Using the plurality of event signals, a core clock, having a first phase, is adjusted to be phase aligned with the slowest bit lane.

Abstract: A phase determination unit in a signal processing circuit generates sampling clocks with different phases in a clock generator and sequentially provides them to an analog-to-digital convertor. Then, the phase determination unit obtains differences between each adjacent two signal levels in each sampled digital signal by use of the sampling clocks, and monitors a polarity change in the differences, extracts a more inappropriate phase for use in sampling from phases of the sampling clocks on the basis of the absolute values of the differences where the polarity change is detected, and determines an antiphase of the extracted phase as a phase of the sampling clock to be provided to the analog-to-digital convertor.

Abstract: Sliding block traceback decoding of block codes. Block by block basis decoding is performed in which a single block, and its corresponding overlap portion, are processed during a given time. The traceback saves a record of decision (e.g., among possible trellis branches between various trellis stages) and constructs only the surviving paths through each individual block. Since only one block (by also employing its corresponding overlap portion) is decoded per time, the traceback through the coded block signal is short. One block of the coded block signal is decoded at a time, and certain resulting information (e.g., bit estimates and/or states) of a first decoded block can be leveraged when decoding a second/adjacent block.

Abstract: A technique for encoding digital communication signals. Data symbols are augmented in pilot symbols inserted at predetermined positions. The pilot augmented sequence is then fed to a deterministic error correction block encoder, such as a turbo product coder, to output a coded sequence. The symbols in the error correction encoded sequence are then rearranged to ensure that the output symbols derived from input pilot symbols are located at regular, predetermined positions. As a result, channel encoding schemes can more easily be used which benefits from power of two length block sizes.

Abstract: This invention discloses a self-timing method for phase adjustment. An analog signal is digitized at a first and second phase with respect to the symbols comprised in an analog signal in order to obtain first and second quantized samples. Then a first counter out of a first plurality of counters is increased if said first quantized sample has a first digital value to which said first counter is associated. Moreover a second counter out of a second plurality of counters is increased if a second quantized sample has a second digital value to which the second counter is associated. Finally the sampling phase is adjusted based on the values of the counters of the first and second plurality of counters. Moreover a digitizing, self-timing circuit is disclosed.

Abstract: A receiving apparatus includes a first receiver, a second receiver, a received signal synthesizer connected to the first and second receivers, a synchronizing signal synthesizer connected to the first and second receivers, and a synchronization detector connected to the synchronizing signal synthesizer. In this structure, synchronization determination is performed using a synchronizing signal of either the first or second receiver, and diversity reception is performed using the received signals of the first and second receivers.

Abstract: A Universal Mobile Telecommunications System (UMTS) receiver comprises an adjustable delay line, a secondary synchronization processor and a controller. The secondary synchronization processor performs frame synchronization on a received wireless signal that is provided via the adjustable delay line. The controller varies the sub-chip timing delays provided by the adjustable delay line until a measure of accuracy of the frame synchronization process exceeds a predetermined threshold, upon which frame synchronization occurs.

Abstract: A wireless base station capable of keeping an internal clock highly accurate even in a case where a malfunction occurs in an external time information notification server such as an NTP server. A wireless base station that performs wireless communication with a mobile terminal is connected to a plurality of time information notification servers. The wireless base station selects any of a plurality of pieces of time information notified from a plurality of time information notification servers, respectively, and corrects an internal clock based on the selected piece of time information. This can keep the internal clock of the wireless base station highly accurate.

Abstract: A secure information transmission system includes one or more transmitters and one or more receivers. The transmission waveform employed includes highly randomized, independent stochastic processes, and is secured as a separate entity from the information it carries. The signal, using novel modulation methodology reducing impulse responses, has a paucity of spectral information and may be detected, acquired and demodulated only by communicants generating the necessary receiving algorithm coefficients. The physical area of signal reception is restricted to that of each intended communicant, reception areas following movements of mobile communicants. A unique instant in time is used as basis for communications keys to the securing algorithms dynamically generated on a one-time basis and never exchanged or stored by communicants.

Abstract: A system for synchronizing data after they are collected and stored locally in sensor units in a distributed sensor system, so that wired or wireless communication is not required during a data-collection session. Each sensor unit has a local clock providing local-clock times before and after a data-collection session, and a data processor uses its local clock or a sensor unit's local clock as the reference to compute each sensor unit's time-scaling factor, which is the ratio of the elapsed reference local-clock time and the elapsed local-clock time. The data processor uses the time-scaling factor to convert each sensor unit's local-clock data-sampling times to the reference local-clock data-sampling times, and the data processor subsequently interpolates sensor data to approximate simultaneous sensor-data values at desired reference local-clock times. A physical-activity monitoring system can use this synchronization method to reduce the size, power consumption, and cost of the sensor units.

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A method is provided for estimating a frequency offset in a carrier signal caused by the Doppler effect. The method determines a frequency offset estimate by utilizing a multi stage estimation scheme. More specifically, the method determines the frequency offset estimate of a data frame by iteratively estimating the frequency offset by comparing different portions of the preamble. As the length of the sampled patterns varies, the frequency offset estimates vary in accuracy and range. The method may adjust frequency offset estimates that are out of range. Finally, the receiver obtains a frequency offset estimate for the data frame from a weighted combination of frequency offset estimates. This method is applicable in WiFi (IEEE 802.11a/g), WiMax (IEEE 802.16), and WAVE (IEEE 802.11p) systems.

Abstract: A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.

Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.

Abstract: A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.

Abstract: The invention relates to a method of transmitting time information relating to the clock of the source of a sending part consisting in using a fixed latency indicator signal to authorize the source to insert time information used to slave the clock of the decoder of the associated receiving part to its clock.

Abstract: A transmission device includes: a transceiving unit transceiving a serial signal generated by serially converting data based on a clock signal of a frequency selected from frequencies used as clock components of the serial signal and including the clock signal of the selected frequency; a clock recovering unit receiving the serial signal received by the transceiving unit and recovers a recovered clock signal from the serial signal; a match determination unit receiving the recovered clock signal and determines whether a frequency of the recovered clock signal matches each of the frequencies; and a frequency controller performing, if the match determination unit determines that the frequency of the recovered clock signal matches each of the frequencies, a control to determine the frequency of the recovered clock signal as the matching frequency, wherein the frequency of the recovered clock signal is switched between the frequencies until the frequency is determined by the frequency controller.

Abstract: A cooperative apparatus and a frequency synchronization method thereof for use in a wireless network are provided. The wireless network comprises a base station and a subscriber station. The cooperative apparatus retrieves a signal from the base station and calculates a frequency offset between the base station and the cooperative apparatus according to the signal. Accordingly, the cooperative receives a cooperative information from the base station and forwards the cooperative information to the subscriber station based on the frequency offset.