Abstract: Exemplary embodiments are directed to near field communication A device may include a current digital-to-analog converter (DAC) configured to convey a current to an antenna in a first near-field communication (NFC) mode and enable for load modulation in a second NFC mode.

Abstract: A wireless base station that performs wireless communication with a mobile terminal is connected to a plurality of time information notification servers. The wireless base station selects any of a plurality of pieces of time information notified from a plurality of time information notification servers, respectively, and corrects an internal clock based on the selected piece of time information. This can keep the internal clock of the wireless base station highly accurate.

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: A method for transmitting synchronization messages in a communications network including a plurality of nodes having a first node and at least one second node, wherein in order to take into account differences in a reference clock frequency of a reference clock and an internal clock frequency of an internal clock of the at least one second node, a compensation interval, with which the second clock count state is adjusted on measurement of a delay time, is subdivided into smaller compensation timespans, and the smaller compensation timespans are used to determine a compensated time value for the delay time with a high degree of accuracy, where the compensated time value is then used to update the time information in the synchronization message.

Abstract: A master unit and a remote unit is provided for a multiband transmission system for distributing and combining signals of at least one wireless communication network and at least one digital network. A reference frequency generator is arranged in the master unit, the reference frequency generator being designed to clock a master modem for converting the signals of the at least one digital network. The reference frequency signal emitted by the reference frequency signal is restored via a reference frequency receiver and is used for closing a remote modem that is located there for demodulation.

Abstract: Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.

Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

Abstract: A circuit generates an output clock signal synchronized to an input clock signal. The circuit includes a reference clock port, a phase interpolator, and a phase controller. The reference clock port receives a reference clock signal. The phase interpolator generates the output clock signal that, as a function of a variable control value, is an interpolation between two reference phases. The reference phases are generated from the reference clock signal and have a reference frequency. The phase controller generates the variable control value providing a phase rotation rate. An output frequency of the output clock signal equals a sum of the reference frequency and the phase rotation rate. The output frequency matches an input frequency of the input clock signal.

Abstract: A radio communication system has a transmitter and a receiver that transmits and receives, respectively, synchronization signals. The transmitter has a multiple-synchronization-signal generation section configured to generate the synchronization signals, a radio circuit configured to transmit the synchronization signals in a predetermined transmission cycle from a start time of the predetermined transmission cycle and with an interval shorter than the predetermined transmission cycle, and a synchronization signal sequence number generation section configured to assign a sequence number to each of the synchronization signals.

Abstract: Provided is a terminal apparatus that can suppress the increase in interference between pilot signals in the same slot, while also suppressing the degradation of the flexibility to design cell cluster structures. When hopping information indicates an inter-slot hopping, a mapping unit (212) arranges a first pilot sequences in which a group to which the sequences used in respective slots belong varies on a slot-by-slot basis. When the hopping information indicates an inter-subframe hopping, the mapping unit (212) arranges a second pilot sequences in which a group to which the sequences used in respective slots belong varies on a subframe-by-subframe basis. The sequence group to which the sequences used in any one of the subframes in the second pilot sequences belong is identical with the sequence group to which the sequence used in any one of the slots included in that one subframe in the first pilot sequences belongs.

Abstract: A network node, a communication system, and a method for transmitting a clock packet through a tunnel are disclosed. The method includes: encapsulating a tunnel ingress clock packet received at an ingress of a tunnel in an encapsulation mode corresponding to the tunnel, and performing clock correction for the encapsulated clock packet; and sending the corrected clock packet to an egress of the tunnel. The network node for processing a clock packet includes an encapsulating module and a sending module. The communication system includes the network node for processing a clock packet, and further includes an intra-tunnel network node and a tunnel egress network node. According to the present invention, a clock packet is re-encapsulated and transmitted through a tunnel. In the subsequent process of transmitting the clock packet transparently, the node itself serves as a clock reference point, and all network nodes do not need to synchronize time absolutely.

Abstract: A method and apparatus for transmitting and receiving high-bandwidth OFDM signals, while limiting the complexity of the OFDM signal processing is described. Bandwidth expansion is achieved by repetition of whole OFDM symbols with the polarity of repetitions determined by a long PN code. This technique ensures a perfectly white spectrum. Use of zero-suffix OFDM symbols allows a large tolerance to multipath channels, even while maintaining a single, low-rate RAKE finger for despreading in the receiver.

Abstract: A correlation calculating method of correlating a received code signal obtained by demodulating a received signal, which is a signal obtained by receiving a positioning satellite signal, with a replica code signal is provided which includes: correlating values of the replica code signal in a chip period with values of the received code signal at first to n-th arrival times obtained by varying an arrival time of the chip period by 1/n chip (where n is an integer equal to or greater than 2); and acquiring a correlation calculation result at a 1/n chip interval by synthesizing the correlation calculation results.

Abstract: A determining method and apparatus thereof for a transition point of a sequence which can be applied to a decoder. The determining method determines the transition point of the sequence having N numbers, wherein the sequence is composed of a first value and a second value and N is a positive integer. The determining method includes determining the position the first value appearing consecutively in the sequence to determine a first interval; determining the position the second value appearing consecutively in the sequence to determine a second interval; and determining the longer interval between the first interval and the second interval, when the first interval is longer, determining an adjacency of the first interval and the second value as the transition point according to the first interval, and when the second interval is longer, determining an adjacency of the second interval and the first value as the transition point.

Abstract: A portable electronic apparatus has a first storage section configured to store information to be communicated to the processing apparatus and formats for a frame to be transmitted to the processing apparatus, in association with one another. The processing apparatus has a second storage section configured to store information communicated by the portable electronic apparatus and the format of the frame transmitted by the portable electronic apparatus, in association with each other. The portable electronic apparatus select one of the formats stored in the first storage section based on the data to be transmitted to the processing apparatus. The processing apparatus recognize information communicated by the portable electronic apparatus based on the format of the frame received from the portable electronic apparatus.

Abstract: A communication system including a phase-locked loop, a signal division controller, a divider, and a transmitter. The phase-locked loop is configured to generate an output signal in response to a common reference clock signal. The output signal is in phase lock with the common reference clock signal. The signal division controller is configured to receive a select signal, select an edge of a rising edge of the output signal and a falling edge of the output signal in response to the select signal, and generate a divider reset signal in response to the selected edge. The divider is configured to generate a communication clock signal by performing frequency division of the output signal. The divider reset signal controls a start time of the frequency division. The transmitter is configured to operate in response to the communication clock signal.

Abstract: Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process.

Abstract: Disclosed herein is a reception apparatus including a calculation section and a storage section. The calculation section calculates correlation values between a data sequence included in a known signal and a received signal at a given point in time. The storage section has at least an area sufficient for storing the correlation values calculated for one frame using the received signal which is one frame long and to which the known signal is added.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: Embodiments of the present invention provide a method for activating a DSL. The method includes: sending, by a central office equipment, a sync frame period indication message to a customer premises equipment, where a sync frame period indicated by the sync frame period indication message is smaller than a specified sync frame period threshold; receiving a reply message sent by the customer premises equipment in response to the sync frame period indication message, where the reply message indicates whether the customer premises equipment accepts the sync frame period indicated by the sync frame period indication message; and if the reply message indicates that the customer premises equipment accepts the sync frame period, performing, by the central office equipment, vectoring training by using a corresponding sync frame within the sync frame period. The embodiments of the present invention further provide corresponding equipments, a system, and a program product.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: A data signal phase reversal correction method and system implementing the same are disclosed. In the present invention, a pilot signal of a satellite is checked to see if there is a phase reversal according to an accumulation of correction results of symbols of the received pilot signal with corresponding symbols of a known pilot sequence. It is determined whether a phase correction of a data signal of the satellite is to be executed or not by referencing the phase reversal determination result of the pilot signal.

Abstract: A medical sensor system comprises a gateway comprising a wideband receiver and a narrow band transmitter, the each gateway configured to receive a wideband positioning frame using the wideband receiver from one or more wearable sensors and to transmit acknowledgement frames using the narrow band transmitter that include timing and control data for use by the sensors to establish timing for transmission of the positioning frame; and at least one wearable sensor comprising a wideband transmitter and a narrow band receiver, the sensor configured to transmit a sensor data frame to the gateway using the wideband transmitter and to receive an acknowledgement frame from the gateway using the narrow band receiver, extract timing and control information from the frame, and adjust the timing and synchronization of the wideband transmitter using the timing and control information.

Abstract: Provided is an OFDM receiver which extracts a time sync signal from a prefix having a symmetric structure. The OFDM receiver, according to exemplary embodiments of the present invention, generates the sync signal (e.g., start point) of a symbol by using only the MSB (e.g., sign bit) of the cyclic prefix of an OFDM symbol, reducing the overhead of a logic circuit for generating the sync signal of the symbol.

Abstract: Embodiments allow for the use of the SS modulation technique (and thus for significant reduction of EMI due to clock transmission) in scenarios involving tight synchronization requirements between two devices. In particular, embodiments can be used in high-speed communication networks (e.g., high-speed Ethernet) where a clock signal embedded in the data stream at the transmitter and recovered from the data stream at the receiver is the only source for synchronization between the transmitter and the receiver (i.e., no other synchronization channel available). Embodiments are also especially useful in communication systems utilizing echo cancellers.

Abstract: Example embodiments are directed to a bandwidth synchronization circuit and a bandwidth synchronization method. The bandwidth synchronization circuit includes an upsizer and a syncdown unit. The upsizer includes a sync packer and a sync unpacker operating according to a first clock. The syncdown unit is connected to the upsizer and performs a syncdown operation on data of the upsizer in response to a second clock of a frequency lower than a frequency of the first clock.

Abstract: A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.

Abstract: It is possible to provide a highly reliable semiconductor device and a communication method in which communication can be performed between circuits with a large degree of freedom of clock frequency which can be set in each of the circuits, a decisive operation, and a small communication latency. The semiconductor device according to the present invention includes a first circuit that performs processing based on a first clock signal, the first clock signal having a frequency M/N times as large as a frequency of a second clock signal (N is a positive integer, and M is a positive integer larger than N); a second circuit that performs processing based on the second clock signal; and a communication timing control circuit that generates a communication timing signal to control a timing at which the first circuit performs communication with the second circuit.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: A signal source synchronization circuit includes: a first TDC circuit that measures a first path delay time which is a time difference between an input time of a trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal; and a second TDC circuit that measures a second path delay time which is a time difference between an input time of the trigger signal to a first input terminal and an input time of the trigger signal to a second input terminal, wherein a first phase shifter adjustment circuit sets a phase adjustment amount corresponding to the first path delay time in a first phase shifter, and a second phase shifter adjustment circuit sets a phase adjustment amount corresponding to the second path delay time in a second phase shifter.

Abstract: For estimating a difference between a frequency of a base station and a locally generated frequency of a mobile equipment in a mobile communications network, wherein at least a signal in a plurality of signals transmitted from the base station and received by the mobile equipment comprises a plurality of symbols each of which includes a cyclic prefix, a correlation between a symbol and its cyclic prefix is used for estimating the frequency difference.

Abstract: According to one embodiment, a frequency offset compensation apparatus includes a first estimation unit, a second estimation unit, a setting unit, a synthesis unit and a compensation unit. The first estimation unit estimates a first rotation. The second estimation unit estimates a second rotation. The setting unit sets a weighting factor for the second rotation to a first value if a received power is less than a threshold value, and sets the weighting factor for the rotation to a second value being smaller than the first value if the received power is not less than the threshold value. The synthesis unit calculates a compensation value. The compensation unit compensates for a frequency offset.

Abstract: The present application discloses a method in which a base station transmits a reference signal sequence in a wireless communication system. In detail, the method comprises the steps of: generating a pseudo-random sequence using a first m-sequence and a second m-sequence; generating the reference signal sequence using the pseudo-random sequence; and transmitting the reference signal to a mobile station via antenna ports different from one another. The second m-sequence has an initial value containing parameters for discriminating reference signal sequences among users.

Abstract: A radio system having multi-standard mixed mode radios is described. The mixed mode radios are used to support combining of digital baseband from a first and a second radio equipment controller. A primary clock associated with the first radio equipment controller and a secondary clock associated with the second radio equipment controller is provided. The quality of the primary clock is evaluated and the primary clock is referenced to the first radio equipment controller if the clock is determined to have appropriate quality factors. The quality of the secondary clock is then evaluated and the secondary clock is referenced to the second radio equipment controller if the secondary clock is determined to have appropriate quality factors. The second radio equipment controller is then referenced to the primary clock once the primary and secondary clocks are aligned.

Abstract: In one embodiment, the present invention includes a method for determining when a step change occurs to a control value for a numerically controlled oscillator (NCO) providing a mixing signal, mixing the mixing signal with an input radio frequency (RF) signal to obtain an intermediate frequency (IF) signal and demodulating the IF signal into a demodulated signal, generating a correction value based on the step change, and applying the correction value to the demodulated signal. Other embodiments may be used to cancel other undesired signal portions, such as impulse spikes generated from the NCO change.

Abstract: An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (?fmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.

Abstract: Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly receives a signal and calculates a differential output corresponding to a multiplication of the signal and a delayed version of the signal. A cross correlation is performed between the differential output and a known preamble pattern to produce a cross correlation output. A moving average calculation is performed on the cross correlation output to produce an average cross correlation. One or more peaks are detected in the average cross correlation when the average cross correlation has an amplitude greater than a threshold. When the one or more detected peaks meets predetermined criteria, the apparatus provides information about at least one of the detected peaks for subsequent signal processing.

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: A transmitter cyclic pattern having a pattern length of N bits is generated and converted into an M-bit transmitter parallel data stream, where N?M. A bit-sequence altered transmitter parallel data stream is generated by performing a transmitter altering process, converted into a serial data and transmitted together with a clock signal. The serial data is received and converted into an M-bit receiver parallel data stream, and a bit-sequence restored parallel data stream is generated by performing a process opposite to the transmitter altering process. A receiver cyclic pattern is generated by using bits in the bit-sequence restored parallel data stream and converted into an M-bit reference parallel data stream, and a bit-sequence altered reference parallel data stream is generated by performing a process same as the transmitter altering process and compared with the received parallel data to test if the data is correctly received.

Abstract: A method of synchronizing two electronic devices connected by a wireless link with at least one path including a transmission channel and a reception channel. The two devices are included in a network, such as a mobile telephone network. Synchronization information is transmitted directly from one electronic device to the other, as a clock pilot signal, via the channels. After recovery, the clock pilot signal is used for synchronization of a reference frequency of the receiving electronic device.

Abstract: A method for transmitting synchronization messages in a communications network including a plurality of nodes having a first node and at least one second node, wherein in order to take into account differences in a reference clock frequency of a reference clock and an internal clock frequency of an internal clock of the at least one second node, a compensation interval, with which the second clock count state is adjusted on measurement of a delay time, is subdivided into smaller compensation timespans, and the smaller compensation timespans are used to determine a compensated time value for the delay time with a high degree of accuracy, where the compensated time value is then used to update the time information in the synchronization message.

Abstract: A method and an interface unit is provided to maintain timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi-standard base station. The first REC receives a synchronization signal and synchronized data output is generated from the synchronization signal. A clock signal is then generated from the synchronized data output. At the second REC, the synchronized data output is received and a synchronization source is then reconstructed from the first clock signal. A timing and frequency component of a second clock signal is then aligned to that of the reconstructed synchronization source, such that the second REC can maintain synchronization with the first REC.

Abstract: An apparatus includes Radio Frequency (RF) circuitry and baseband circuitry. The RF circuitry is configured to receive strobe messages that are based on a system clock over a digital interface, and to communicate synchronously with the system clock based on the received strobe messages in accordance with a Radio Access Technology (RAT) that is selected from among multiple different RATs. The baseband circuitry is configured to generate the strobe messages, to delay the strobe messages by a delay that depends on the selected RAT, and to send the delayed strobe messages to the RF circuitry over the digital interface.

Abstract: A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including modulated carriers for transmitting known data and unmodulated carriers for error correction, comprising, time domain down converting the received multi-carrier signal to base-band to provide a down-converted signal, the down-converted signal including a plurality of modulated carriers for transmitting known data and unmodulated carriers for error correction. Sampling an unmodulated carrier of the down-converted signal to provide received data samples. Providing a reference signal derived from the unmodulated carrier of the down-converted signal. And, estimating phase errors from a phase difference between the ummodulated carrier and the reference signal derived from the unmodulated carrier of the down-converted signal to provide a plurality of received sample phase error estimates for each modulated carrier.

Abstract: The disclosure aims to implement an automatic frequency offset compensation of the frequency between emitter and receiver equipments, in radio frequency modules, with a frequency offset that can be larger than that the receiver can allow, without time loss and extra consumption. To solve this problem, the disclosure provides an automatic frequency offset compensation device comprising a reception front end, at least a filter, an I/Q demodulator for obtaining the I (In Phase) and Q (Quadrature) parameter, an automatic frequency control AFC unit for comparison of a received frequency with the real frequency of the equipment, and a microcontroller and a frequency synthesizer. In this device, the frequency offset is calculated by the AFC unit from the information given by the I/Q demodulator.

Abstract: A receiver includes a CDR circuit, serial-to-parallel converter, and test module. The CDR circuit is for receiving the test signal groups inputted in series and following transmitting frequency of the test signal groups to obtain a clock signal, wherein the clock signal is used to provide an operational frequency of the receiver. The serial-to-parallel converter is for receiving the test signal groups outputted by the CDR circuit and converting the serially-inputted test signal groups into a plurality of test bytes outputted in parallel, wherein each of the test bytes has multi-bit of data. The test module is for receiving the test bytes and the clock signal and comparing two adjacent bytes of the test bytes to determine whether the two adjacent test bytes are completely the same.

Abstract: Disclosed herein is a signal transmission system including: a first signal processing section configured to perform signal processing on a basis of a reference signal; a high-frequency reference signal generating section configured to generate and transmit a high-frequency reference signal having a higher frequency than the reference signal such that the high-frequency reference signal is synchronized with the reference signal; a low-frequency reference signal generating section configured to receive the high-frequency reference signal from the high-frequency reference signal generating section, and generate a low-frequency reference signal having a lower frequency than the high-frequency reference signal such that the low-frequency reference signal is synchronized with the received high-frequency reference signal; and a second signal processing section configured to perform signal processing on a basis of the low-frequency reference signal generated by the low-frequency reference signal generating section.

Abstract: A signal selection apparatus for selecting a target signal from a plurality of input signals is provided. The input signals correspond to different time indexes. The signal selection apparatus comprises a weight calculation unit for generating a corresponding weight respectively for each of the input signals, a processing unit for processing the input signals respectively to generate a plurality of processed signals according to the weights, and a selection unit for selecting a signal with a larger energy from the processed signals as the target signal, wherein the weights are used for adjusting an individual energy of the input signals such that the time index of the target signal is earlier within the input signals.