Abstract: A scheduling optimizer system, method and program product that analyzes a device for sensitivities, such as ESD sensitivities, and allows for modification of a floor schedule of the assembly unit of the device based on the sensitivity of the device while improving the overall performance of the assembly unit are disclosed. The scheduling optimizer analyzes sensitivity data for a device during operation of the assembly unit on the floor schedule. The floor schedule is then optimized based on the analyzed sensitivity data.

Abstract: A number of RF power transmission paths are defined to extend from an RF power source through a matching network, through a transmit electrode, through a plasma to a number of return electrodes. A number of tuning elements are respectively disposed within the number of RF power transmission paths. Each tuning element is defined to adjust an amount of RF power to be transmitted through the RF power transmission path within which the tuning element is disposed. A plasma density within a vicinity of a particular RF power transmission path is directly proportional to the amount of RF power transmitted through the particular RF power transmission path. Therefore, adjustment of RF power transmitted through the RF power transmission paths, as afforded by the tuning element, enables control of a plasma density profile across a substrate.

Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.

Abstract: An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: An object is to suppress a significant change in electrical characteristics of thin film transistors and a deviation thereof from the designed range due to static electricity, and to improve the yield in manufacturing semiconductor devices. In order to prevent a substrate from being charged with static electricity by heat treatment or to favorably reduce static electricity with which a substrate is charged in a manufacturing process of a semiconductor device, heat treatment is performed with a substrate provided with a thin film transistor stored in a conductive container. In addition, a heating apparatus for performing the heat treatment is electrically connected to a ground potential, and the container and the substrate are also electrically connected to the ground potential.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: A sensor arrangement including a control circuit is disclosed. In at least one embodiment, at least one sensor electrode can be charged and/or discharged therewith and a comparator unit for the comparison of a provided voltage for the at least one electrode with a reference voltage. A duration necessary for the charging/discharging of the at least one sensor electrode is determined, whereby, from the determined duration, it is determined whether a sensor event, in the form of a hybridization between trap molecules and the particles for recording, has occurred.

Abstract: According to one embodiment, a manufacturing method for a semiconductor device includes: forming a test pattern with a metal film embedded therein through a plating process; detecting a characteristic of the test pattern; and adjusting a condition for the plating process based on the detected characteristic of the test pattern. The test pattern is formed over three or more wiring layers and includes a stacked via in an intermediate layer.

Abstract: A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.

Abstract: A method of manufacturing a semiconductor module is provided. The method includes forming semiconductor chips on a bare substrate, performing a burn-in process on the bare substrate including the semiconductor chips, sorting semiconductor chips that exceed a predetermined level of operability determined by testing electrical driving in the semiconductor chips on the burned-in bare substrate, separating the semiconductor chips from one another by cutting the bare substrate, and directly mounting the module semiconductor chips on a module substrate.

Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.

Abstract: A device and method are provided for detecting stress migration properties of a semiconductor module mounted in a housing. A stress migration test (SMT) structure is formed in the semiconductor module. An integrated heating (IH) device is formed within or in direct proximity to the SMT structure. The SMT structure includes a first interconnect region in a first interconnect layer, a second interconnect region in a second interconnect layer, and a connecting region electrically connecting the interconnect regions through a first insulating layer. The IH device includes a heating interconnect region through which a heating current flows. The heating interconnect region is within or outside the first or second interconnect region or connecting region. When the heating current is applied, a measurement voltage is applied to the SMT structure, and a current through the SMT structure is measured to detect stress migration properties of the semiconductor module.

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract: Methods and apparatuses for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of impedance. The calibration curve may be an analytic function having infinite number terms, such as trigonometric, hyperbolic, and logarithmic, or a continuous plurality of functions, such as lines. High accuracy allows the omission of optical sensors, and use of eddy current sensors for endpoint detection, transition call detection, and closed loop control in which a process parameter is changed based on the measured magnetic flux density change in one or more processing zones.

Abstract: A film forming process is performed on a substrate in a deposition chamber. A first electrode is provided in the deposition chamber and is grounded. A second electrode is provided in the deposition chamber to face the first electrode. A radio frequency power supply supplies radio frequency power to the second electrode. A DC power supply supplies a DC bias voltage to the second electrode. A control unit adjusts a bias voltage to be less than the potential of the second electrode when the radio frequency power is supplied, but the bias voltage is not supplied. In this way, it is possible to improve film quality while preventing a reduction in the deposition rate of a film during deposition.

Abstract: A structure and a method for operating the same. The method includes providing a detecting structure which includes N detectors. N is a positive integer. A fabrication step is simultaneously performed on the detecting structure and M product structures in a fabrication tool resulting in a particle-emitting layer on the detecting structure. The detecting structure is different than the M product structures. The M product structures are identical. M is a positive integer. An impact of emitting particles from the particle-emitting layer on the detecting structure is analyzed after said performing is performed.

Abstract: A semiconductor process system (10) includes a measuring section (40), an information processing section (51), and a control section (52). The measuring section (40) measures a characteristic of a test target film formed on a target substrate (W) by a semiconductor process. The information processing section (51) calculates a positional correction amount of the target substrate (W) necessary for improving planar uniformity of the characteristic, based on values of the characteristic measured by the measuring section (40) at a plurality of positions on the test target film. The control section (52) controls a drive section (30A, 32A) of a transfer device (30), based on the positional correction amount, when the transfer device (30) transfers a next target substrate (W) to the support member (17) to perform the semiconductor process.

Abstract: In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size.

Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate.

Abstract: According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Abstract: In a diffractive element, its grating pattern is so configured that a diffraction angle of a diffracted light beam of a light source that is subject to the first-order diffraction in a diffraction area is matched with an angle of a light beam passing through the diffractive area emitted from a light source and a light source position is matched with a light originating point of the light source that emits a light beam to be transmitted, and the center of light intensity distribution is matched with that of the light source passing through the diffractive element by inclining an optical axis of the light source. A position of the diffractive element is adjusted based on an electric current value generated when a reflected return path light beam of the light source is diffracted by the diffractive element and enters the light source.

Abstract: The instant pulse filter according to the present invention, which may cause a malfunction or a short life span of a semiconductor device, is made using an aluminum anodic oxidation, comprising—a first step for forming an aluminum thin film layer on an upper side of an insulator substrate; a second step for forming an aluminum oxide thin film layer having a pore by oxidizing the aluminum thin film layer by means of an anodic oxidation; a third step for depositing a metallic material on an upper side of the aluminum thin film layer for filling the pore; a fourth step for forming a nano rod in the interior of the aluminum oxide thin film layer by eliminating the metallic material deposited except in the pore; a fifth step for forming an internal electrode on an upper side of the aluminum oxide thin film layer having the nano rod; a sixth step for forming a protective film layer on an upper side of the same in order to protect the aluminum oxide thin film layer and the internal electrode from the external enviro

Abstract: It is intended to provide a plasma doping method and apparatus which are superior in the controllability of the concentration of an impurity that is introduced into a surface layer of a sample. A prescribed gas is introduced into a vacuum container 1 from a gas supply apparatus 2 while being exhausted by a turbomolecular pump 3 as an exhaust apparatus. The pressure in the vacuum container 1 is kept at a prescribed value by a pressure regulating valve 4. High-frequency electric power of 13.56 MHz is supplied from a high-frequency power source 5 to a coil 8 disposed close to a dielectric window 7 which is opposed to a sample electrode 6, whereby induction-coupled plasma is generated in the vacuum container 1. A high-frequency power source 10 for supplying high-frequency electric power to the sample electrode 6 is provided. Every time a prescribed number of samples have been processed, a dummy sample is subjected to plasma doping and then to heating.

Abstract: An alignment method is provided in which a substrate including first and second layers is aligned in forming a second pattern in the second layer. The method includes storing first alignment measurement data to be used in alignment performed in forming a first pattern and a second alignment mark in the second layer, the first alignment measurement data obtained by measuring a first alignment mark provided in the first layer; obtaining second alignment measurement data by measuring the second alignment mark through a resist applied over the second layer; obtaining third alignment measurement data by measuring the first alignment mark through the resist; and performing alignment of the substrate in accordance with a first difference between the first and second alignment measurement data, or in accordance with the first difference and a second difference between the first and third alignment measurement data.

Abstract: A pixel includes an organic light emitting diode, a first transistor having a source coupled to a first power source, a control gate coupled to a first node, and a drain coupled to a second node, wherein the first transistor includes a floating gate and an insulating layer between the floating gate and the control gate, a second transistor having a source coupled to a data line, a drain coupled to the first node, and a gate coupled to a scan line, a third transistor having a source coupled to the second node, a drain coupled to the organic light emitting diode, and a gate coupled to one of a light emitting control line and the scan line, and a capacitor coupled between the first power source and the first node.

Abstract: An ion implantation system and method are disclosed in which glitches in voltage are minimized by modifications to the power system of the implanter. These power supply modifications include faster response time, output filtering, improved glitch detection and removal of voltage blanking. By minimizing glitches, it is possible to produce solar cells with acceptable dose uniformity without having to pause the scan each time a voltage glitch is detected. For example, by shortening the duration of a voltage to about 20-40 milliseconds, dose uniformity within about 3% can be maintained.

Abstract: A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside.

Abstract: [Problems] There are provided a chip separation method and a chip transfer method using features of dry etching. [Means for Solving the Problems] In the chip separation method, a multiple number of semiconductor devices or semiconductor integrated circuits are separated from a wafer 100 on which the multiple number of semiconductor devices or semiconductor integrated circuits are formed. The method includes forming, on a surface of the wafer 100, a mask layer through which a line-shaped pattern to be removed for separating the semiconductor devices or semiconductor integrated circuits is exposed; and etching the exposed pattern to a depth equal to or larger than about ? of a thickness of the wafer. One group of separated semiconductor devices or semiconductor integrated circuits has a distinguishable shape from another group of separated semiconductor devices or semiconductor integrated circuits.

Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: Various semiconductor devices and methods of testing such devices are disclosed. In one aspect, a method of manufacturing is provided that includes forming a bore from a backside of a semiconductor chip through a buried insulating layer and to a semiconductor device layer of the semiconductor chip. A conductor structure is formed in the bore to establish an electrically conductive pathway between the semiconductor device layer and the conductor structure. The conductor structure may provide a diagnostic pathway.

Abstract: A method for manufacturing an image sensor includes forming first to third photodiodes and first to third color filters corresponding thereto; forming a photoresist film including photosensitive materials on the upper surfaces of the first to third color filters; forming a first exposed part by exposing the photoresist film with a first exposure energy using a first pattern mask with a first light transmitting part having a first width at boundaries between the individual color filters; forming a second exposed part overlapping a portion of the first exposed part by exposing the photoresist film with a second exposure energy smaller than the first exposure energy using a second pattern mask with a second light transmitting part having a second width wider than the first width; and forming microlenses by developing the photoresist film.

Abstract: A method of processing a wafer in a plasma, in which target values of two different plasma process parameters are simultaneously realized under predetermined process conditions by setting respective power levels of VHF and HF power simultaneously coupled to the wafer to respective optimum levels.

Abstract: A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.

Abstract: A method and apparatus for data analysis according to various aspects of the present invention is configured to automatically select one or more outlier identification algorithms for identifying statistical outliers in test data for components.

Abstract: The invention can provide apparatus and methods for processing substrates and/or wafers in real-time using at least one Direct Current (DC)/Radio Frequency (RF) Hybrid (DC/RFH) processing system and associated Direct Current/Radio Frequency Hybrid (DC/RFH) procedures and DC/RFH process parameters and/or DC/RFH models.

Abstract: An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOMC of a semiconductor chip is defined as the product of a term represented by electrical performance of a substrate S and a term represented by a semiconductor chip cost CC; the FOMC of each of the semiconductor chips on substrates SS, SC of different type is determined by calculation of the product thereof. Based on the magnitudes of the calculation results, a desired substrate is selected from the substrates SS, SC and then a semiconductor chip is fabricated by forming a semiconductor element on the desired substrate selected.

Abstract: A semiconductor oxidation apparatus is provided with a sealable oxidation chamber defined by walls, a base provided within the oxidation chamber and configured to support a semiconductor sample, a supply part configured to supply water vapor into the oxidation chamber to oxidize a specific portion of the semiconductor sample, a monitoring window provided in one of the walls of the oxidation chamber and disposed at a position capable of confronting the semiconductor sample supported on the base, a monitoring part provided outside the oxidation chamber and capable of confronting the semiconductor sample supported on the base via the monitoring window, and an adjusting part configured to adjust a distance between the base and the monitoring part.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: A method for forming an electrical heating element by flame spraying a metal/metallic oxide matrix, wherein a flame sprayed metal/metallic oxide matrix is deposited onto an insulating or conductive substrate such as to have a higher resistance than is required for a designed use, and an intermittently pulsed high voltage DC supply is applied across the matrix such as to produce continuous electrically conductive paths through the matrix which permanently increase the overall conduction and simultaneously reduce the overall resistance of the metal/metallic matrix to achieve a desired resistance value.

Abstract: A method for polishing a substrate having a metal film thereon is described. The substrate has metal interconnects formed from part of the metal film. The polishing method includes performing a first polishing process of removing the metal film, after the first polishing process, performing a second polishing process of removing the barrier film, after the second polishing process, performing a third polishing process of polishing the insulating film. During the second polishing process and the third polishing process, a polishing state of the substrate is monitored with an eddy current sensor, and the third polishing process is terminated when an output signal of the eddy current sensor reaches a predetermined threshold.

Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity corresponds to the target band discontinuity.

Abstract: A method for manufacturing a semiconductor device, the semiconductor device including an integrated circuit having plural connection terminals arranged on a predetermined local region of the integrated circuit, plural metal bumps, and a wiring layer connected to at least a portion of the connection terminals via the plural metal bumps, the method includes the steps of a) measuring an impedance value of the predetermined local region of the integrated circuit, b) determining whether the measured impedance value matches a predetermined impedance value, c) determining positions of the plural metal bumps in accordance with the determination result of step b), d) forming the plural metal bumps on the positions determined in step c), and e) forming the wiring layer on the plural metal bumps.

Abstract: A method and apparatus is provided for use in an integrated circuit or printed circuit board for reducing or minimizing interference. An inductance is formed using two or more inductors coupled together and configured such that current flows through the inductors in different directions, thus at least partially canceling magnetic fields. When designing a circuit, the configuration of the inductors, as well as the relative positions of portions of the circuit, can be tweaked to provide optimal interference or noise control.

Abstract: A plasma reactor includes a vacuum enclosure including a side wall and a ceiling defining a vacuum chamber, and a workpiece support within the chamber and facing the ceiling for supporting a planar workpiece, the workpiece support and the ceiling together defining a processing region between the workpiece support and the ceiling. Process gas inlets furnish a process gas into the chamber. A plasma source power electrode is connected to an RF power generator for capacitively coupling plasma source power into the chamber for maintaining a plasma within the chamber. The reactor further includes at least a first overhead solenoidal electromagnet adjacent the ceiling, the overhead solenoidal electromagnet, the ceiling, the side wall and the workpiece support being located along a common axis of symmetry.

Abstract: In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor.

Abstract: Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

Abstract: Disclosed is an apparatus and method for plasma processing, which facilitates to constantly control a RF voltage supplied to a substrate supporting member by precisely detecting an inductive RF voltage induced to the substrate supporting member for a plasma, the apparatus comprising: a substrate supporting member for supporting a substrate, installed in a reaction room of a processing chamber; a RF generator for supplying a RF voltage to the substrate supporting member so as to form plasma in the reaction room; and a matching device for matching impedance of the RF voltage to be supplied to the substrate supporting member from the RF generator, wherein the matching device comprises: a matching unit for matching the impedance of RF voltage; and an inductive RF detecting unit which an inductive RF detecting voltage by removing noise frequency elements except a waveform of the RF voltage from a waveform of an inductive RF voltage induced to the substrate supporting member, and supplies the detected inductive RF

Abstract: Methods for detecting the breakdown potential of a semiconductor device having a thin dielectric layer are disclosed. The method includes measuring a spectroscopy of the thin dielectric layer and determining whether the spectroscopy exhibits the presence of a breakdown precursor (H2, H interstitial radical, H attached radical, and H attached dimer). Preferably, the method is carried out in the presence of a substantially significant applied electric field across dielectric layer. A semiconductor device tested in accordance with this method is also disclosed. Additionally, methods for reducing dielectric breakdown of a semiconductor device having a thin dielectric layer involving the substitution of a second molecule for H2 molecules present in the dielectric. This second molecule preferably does not react with Si or O to form an undesired attached state and may be an inert gas having a molecular size approximating that of a Hydrogen atom, such as Helium.