Abstract: The present invention provides a signal transmitting/receiving method comprising: disposing a ferromagnetic film between a semiconductor device having an inductor and an external device which includes an external inductor provided in a position corresponding to the inductor of the semiconductor device; disposing the inductor and the external inductor so as to face each other via the ferromagnetic film therebetween; and in a state in which the inductor and the external inductor face each other, transmitting and receiving the signals between the inductor and the external inductor by electromagnetic induction.

Abstract: Systems and methods for detecting and monitoring Nickel-silicide process and induced failures. In a first method embodiment, a method of characterizing a Nickel-silicide semiconductor manufacturing process includes accessing a test chip including a parallel coupled chain of transistors, wherein the transistors are designed for inducing stress into Nickel-silicide features of the transistors, and for increasing a probability of a manufacturing failure of the Nickel-silicide features. A biasing voltage is applied to one terminal of the parallel coupled chain, all other terminals of the parallel coupled chain and grounded, and current is measured at each of the all other terminals of the parallel coupled chain. This process is repeated for each terminal of the parallel coupled chain. The measured currents from all possible conduction paths are compared to determine a manufacturing defect in the parallel coupled chain of transistors.

Abstract: A thermal treatment apparatus having a first light source emitting a first light having light diffusion property, a reflectance measuring unit irradiating a treatment target with the light from plural directions by the first light source and determining a light reflectance of the treatment target, a light irradiation controller adjusting an intensity of a second light of a second light source on the basis of the light reflectance, the second light has diffusion property, and a thermal treatment unit irradiating the treatment target with the second light having adjusted the intensity of the second light by the light irradiation controller.

Abstract: The invention concerns a method of processing a wafer in a plasma reactor chamber by controlling plural chamber parameters in accordance with desired values of plural plasma parameters. The method includes concurrently translating a set of M desired values for M plasma parameters to a set of N values for respective N chamber parameters. The M plasma parameters are selected from a group including wafer voltage, ion density, etch rate, wafer current, etch selectivity, ion energy and ion mass. The N chamber parameters are selected from a group including source power, bias power, chamber pressure, inner magnet coil current, outer magnet coil current, inner zone gas flow rate, outer zone gas flow rate, inner zone gas composition, outer zone gas composition. The method further includes setting the N chamber parameters to the set of N values.

Abstract: The ion implantation apparatus includes a source head, an extraction electrode having a slit trough which a part of an ion beam outputted from the source head passes, a magnet for curving a trajectory of the ion beam passed through the slit, a target to be irradiated with the ion beam outputted from the magnet, an electric current measuring device facing an ion exit port of the source head through the slit of the extraction electrode, and a control portion for controlling a position of the extraction electrode based on a measured result of the current measuring device in a state that production of a magnetic field from the magnet is stopped.

Abstract: A method for controlling the plasma etching of semiconductor wafers determines the impedance of a plasma chamber using values representing voltage, current, and the phase angle between them, as provided by a sensor. All or less than all of the data during a first time period may be used to calculate a model. During a second time period, real time data is used to calculate a version of the instant impedance of the chamber. This version of impendence is compared to a time-projected version of the model. The method determines that etching should be stopped when the received data deviates from the extrapolated model by a certain amount. In some embodiments a rolling average is used in the second time period, the rolling average compared to the model to determine the end point condition.

Abstract: A semiconductor die includes proximity connectors proximate to a surface of the semiconductor die. This semiconductor die is configured to communicate signals with another semiconductor die via proximity communication through one or more of the proximity connectors. In particular, the proximity connectors include a first group of proximity connectors that is configured to facilitate determining a first separation between the semiconductor die and the other semiconductor die by comparing coupling capacitances between the semiconductor die and the other semiconductor die. Note that the first group of proximity connectors includes a first proximity connector and a second proximity connector, and the second proximity connector at least partially encloses an in-plane outer edge of the first proximity connector.

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber.

Abstract: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

Abstract: A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus.

Abstract: In the nitride based semiconductor optical device LE1, the strained well layers 21 extend along a reference plane SR1 tilting at a tilt angle ? from the plane that is orthogonal to a reference axis extending in the direction of the c-axis. The tilt angle ? is in the range of greater than 59 degrees to less than 80 degrees or greater than 150 degrees to less than 180 degrees. A gallium nitride based semiconductor layer P is adjacent to a light-emitting layer SP? with a negative piezoelectric field and has a band gap larger than that of a barrier layer. The direction of the piezoelectric field in the well layer W3 is directed in a direction from the n-type layer to the p-type layer, and the piezoelectric field in the gallium nitride based semiconductor layer P is directed in a direction from the p-type layer to the n-type layer. Consequently, the valence band, not the conduction band, has a dip at the interface between the light-emitting layer SP? and the gallium nitride based semiconductor layer P.

Abstract: An approach for predicting dose repeatability in an ion implantation is described. In one embodiment, an ion source is tuned to generate an ion beam with desired beam current. Beam current measurements are obtained from the tuned ion beam. The dose repeatability is predicted for the ion implantation as a function of the beam current measurements.

Abstract: Methods and systems for in situ process control, monitoring, optimization and fabrication of devices and components on semiconductor and related material substrates includes a light illumination system and electrical probe circuitry. The light illumination system may include a light source and detectors to measure optical properties of the in situ substrate while the electrical probe circuitry causes one or more process steps due to applied levels of voltage or current signals. The electrical probe circuitry may measure changes in electrical properties of the substrate due to the light illumination, the applied voltages and/or currents or other processes. The in situ process may be controlled on the basis of the optical and electrical measurements.

Abstract: In one embodiment, a method of forming a high voltage element includes forming a sense element overlying at least a portion of a semiconductor substrate, and also includes operably coupling a first circuit to use a sense signal formed by the sense element for one of detecting a line under-voltage condition, detecting a line over-voltage condition, determining input power, limiting input power, power limiting, controlling standby operation, a line feed-forward function for current mode ramp compensation, regulating an output voltage, or detecting an energy transfer state of an energy storage element.

Abstract: Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching.

Abstract: In remote plasma cleaning, it is difficult to locally excite a plasma because the condition is not suitable for plasma excitation different from that at the time of film formation and a method using light has a problem of fogginess of a detection window that cannot be avoided in a CVD process and is not suitable for a mass production process.

Abstract: The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step.

Abstract: A method for producing an integrated circuit including a semiconductor is disclosed. In one embodiment, crystal defects are produced by irradiation in the material of the underlying semiconductor substrate which crystal defects form an inhomogeneous crystal defect density distribution in the vertical direction of the semiconductor component and lead to a corresponding inhomogeneous distribution of the carrier lifetime.

Abstract: Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation.

Abstract: An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability.

Abstract: A substrate processing method is used to polish a substrate. The substrate processing method includes rotating a substrate 13 by a motor 12, polishing a first surface of a peripheral portion of the substrate 13 by pressing a polishing surface of a polishing mechanism 20 against the first surface, determining a polishing end point of the first surface by monitoring a polished state of the first surface, stopping the polishing according to the determining the polishing end point, determining a polishing time spent for the polishing, determining a polishing time for a second surface of the peripheral portion based on the polishing time of the first surface, and polishing the second surface for the determined polishing time.

Abstract: A method of responding to voltage or current transients during processing of a wafer in a plasma reactor at each of plural RF power applicators and at the wafer support surface. For each process step and for each of the power applicators and the wafer support surface, the method includes determining an arc detection threshold lying above a noise level. The method further includes comparing each transient with the threshold determined for the corresponding power applicator or wafer support surface, and issuing an arc detect flag if the transient exceeds the threshold.

Abstract: A method for manufacturing a high-frequency signal transmission circuit includes the steps of forming a groove to surround a first region on a semiconductor substrate, filling the groove with a stopper material, forming a high-frequency transmission line on the semiconductor substrate so that the transmission line extends over the first region, and etching the first region of the semiconductor substrate using the stopper material as an etching stopper to form a recess in the first region.

Abstract: A method of manufacturing a sensor node module includes forming a protruding structure on a carrier. A sensor die is applied onto the protruding structure with an active sensing surface of the sensor die facing the carrier. The sensor die is encapsulated with mold material, wherein the protruding structure prevents the mold material from covering the active sensing surface. The carrier and the protruding structure are removed from the sensor die.

Abstract: A method of manufacturing an MEMS device includes: forming a covering structure having an MEMS structure and a hollow portion, which is located on a periphery of the MEMS structure and is opened to an outside, on a substrate; and performing surface etching for the MEMS structure in a gas phase by supplying an etching gas to the periphery of the MEMS structure from the outside.

Abstract: Techniques for uniformity tuning in an ion implanter system are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for ion beam uniformity tuning. The method may comprise generating an ion beam in an ion implanter system. The method may also comprise measuring a first ion beam current density profile along an ion beam path. The method may further comprise measuring a second ion beam current density profile along the ion beam path. In addition, the method may comprise determining a third ion beam current density profile along the ion beam path based at least in part on the first ion beam current density profile and the second ion beam current density profile.

Abstract: A method and apparatus for thermally processing a substrate is provided. A substrate is disposed within a processing chamber configured for thermal processing by directing electromagnetic energy toward a surface of the substrate. An energy blocker is provided to block at least a portion of the energy directed toward the substrate. The blocker prevents damage to the substrate from thermal stresses as the incident energy approaches an edge of the substrate.

Abstract: A method for processing a semiconductor wafer in a plasma reactor comprises sensing transient voltages or currents on a conductor coupled to the wafer and providing a first comparator for comparing the transient voltages or currents with a threshold level stored in the comparator. The method further includes transmitting from the comparator an arc flag signal whenever a transient voltage or current is sensed that exceeds the threshold level, and deactivating the power generator in response to the arc flag signal.

Abstract: A method of monitoring and testing electro-migration and time dependent dielectric breakdown includes forming an addressable wiring test array, which includes a plurality or horizontally disposed metal wiring and a plurality of segmented, vertically disposed probing wiring, performing a single row continuity/resistance check to determine which row of said metal wiring is open, performing a full serpentine continuity/resistance check, and determining a position of short defects.

Abstract: A plasma reactor system for processing a wafer in which respective comparators are coupled to the respective RF transient sensors which are coupled in turn to respective RF power application points. The comparators have respective comparison thresholds. The system further includes a controller programmed to updating the respective thresholds of the comparators with respective updated thresholds for different ones of the steps of the process recipe.

Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: A method is given for aligning an optical package comprising a laser, a wavelength conversion device, at least one adjustable optical component and at least one actuator. The adjustable optical component may be moved to a command position by applying a pulse width modulated signal to the actuator. The command position represents an optimized alignment of the laser and wavelength conversion device. The actual position of the adjustable may be measured by measuring an output of a position measuring circuit, which may measure the voltage amplitude of an oscillation in a resonator tank circuit during an “off” period of the pulse-width modulated signal. The resonator tank circuit may comprise a capacitive element electrically coupled to the electrically conductive coil. The pulse-width modulated signal may then be adjusted to compensate for any difference in the actual position and the command position of the adjustable optical component. Additional embodiments are disclosed and claimed.

Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Abstract: Wafer level arc detection is provided in a plasma reactor using an RF transient sensor sensing voltage at an electrostatic chucking electrode, the RF sensor being coupled to a threshold comparator, and a system controller responsive to the threshold comparator.

Abstract: A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.

Abstract: Wafer level arc detection is provided in a plasma reactor using an RF transient sensor coupled to a threshold comparator, and a system controller responsive to the threshold comparator.

Abstract: Universal plasma unconfinement detection systems configured to detect the plasma unconfinement condition in the plasma processing chamber and methods therefor. The detection systems and methods are designed to reliably and accurately detect the existence of the plasma unconfinement condition in a process-independent and recipe-independent manner.

Abstract: The present invention discloses a semiconductor device. The semiconductor device includes an integrated circuit and a connecting component. The integrated circuit includes a first pad; a second pad; a first current guiding circuit, coupled to the first pad and a first reference voltage, for selectively guiding a first specific electrical signal received from the first pad to the first reference voltage; and a second current guiding circuit, coupled to the second pad and a second reference voltage, for selectively guiding a second specific electrical signal received from the second pad to the second reference voltage; and the connecting component is external to the integrated circuit for coupling the first pad and the second pad.

Abstract: A method is provided for manufacturing an integrated electronic component arranged on a substrate wafer. According to the method, at least one metallization step is performed, and a value of an electrical parameter of the integrated electronic component is determined after the at least one metallization step. A subsequent metallization step is performed after determining the value of the electrical parameter. The subsequent metallization step is performed using an adjustment mask chosen from n predefined masks based on a desired value of the electrical parameter, so as to obtain the desired value of the electrical parameter of the integrated electronic component after manufacturing. In one preferred embodiment, a series of electrical tests is performed on the wafer using test equipment, and the value of the electrical parameter is determined using the same test equipment as is used to perform the series of electrical tests.

Abstract: Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (210, 215). Electrical bias (920) and/or thermal power (925) is applied on each side of a wafer (100) having back and front electrical contacts for semiconductor devices borne by the wafer. A pliable conductive layer (910) is described for supplying pins on the device side of a wafer with electrical contact and/or also for providing protection to the wafer from mechanical pressure being applied to its surfaces. Use of a cooling system (950) is also described for enabling the application of a uniform temperature to a wafer undergoing burn-in.

Abstract: A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-? directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film.

Abstract: Method and system for detecting endpoint for a plasma etch process are provided. In accordance with one embodiment, the method provides a semiconductor substrate having a film to be processed thereon. The film is processed in a plasma environment during a time period to provide for device structures. Information associated with the plasma process is collected. The information is characterized by a first signal intensity. Information on a change in the first signal intensity is extracted. The change in the first signal intensity has a second signal intensity. The change in signal intensity at the second signal intensity is associated to an endpoint of processing the film in the plasma environment. The second signal intensity may be about 0.25% and less of the first signal intensity.

Abstract: A doping process, including applying pressure to at least one first phase of a semiconductor containing an electrically inactive dopant and removing the pressure to cause at least one phase transformation of the semiconductor to at least one second phase, wherein the at least one phase transformation activates the dopant so that the at least one second phase includes at least one doped phase of the semiconductor in which the dopant is electrically active.

Abstract: A microelectromechanical device and method of fabricating the same, including a layer of patterned and deposited metal or mechanical-quality, doped polysilicon inserted between the appropriate device element layers, which provides a conductive layer to prevent the microelectromechanical device's output from drifting. The conductive layer may encapsulate of the device's sensing or active elements, or may selectively cover only certain of the device's elements. Further, coupling the metal or mechanical-quality, doped polysilicon to the same voltage source as the device's substrate contact may place the conductive layer at the voltage of the substrate, which may function as a Faraday shield, attracting undesired, migrating ions from interfering with the output of the device.

Abstract: Zero point shift based on thermal siphon effect occurring actually when a substrate is processed is detected accurately and corrected suitably. The semiconductor fabrication system comprises a gas supply passage (210) for supplying gas into a heat treatment unit (110), an MFC (240) for comparing an output voltage from a detecting unit for detecting the gas flow rate of the gas supply passage with a set voltage corresponding to a preset flow rate and controlling the gas flow rate of the gas supply passage to the set flow rate, and a control unit (300).

Abstract: A method for identifying potentially defective integrated circuit chips and excluding them from future testing as wafers move through a manufacturing line The method includes data-collecting steps, tagging the chips on wafers identified as potentially bad chips based on information collected as the wafer moves down the fabrication line, evaluating test cost savings by eliminating any further tests on the tagged chips preferably using a test cost database. Considering all the future tests to be preformed, the tagged chips are skipped if it is determined that the test cost saving is significant. Tagging bad chips is based on various criteria and models which are dynamically adjusted by performing the wafer final test on samples of the tagged chips and feeding-back the final test results. The dynamic adaptive adjustment method preferably includes a feedback loop or iterative process to evaluate financial tradeoffs when assessing the profit of salvaging chips against the additional test costs.

Abstract: A silicon substrate processing method for reducing the thickness of an area of a silicon substrate on which a metal layer is formed to implement a semiconductor integrated circuit is disclosed. The method includes: (A) a process which evenly reduces the thickness of the backside of a silicon substrate to an extent where mechanical strength is maintained and the metal layer on the silicon substrate remains intact; (B) a process which detects defects from the backside of the silicon substrate after the process (A); (C) a process which further reduces the thickness of a defect-containing area of the silicon substrate by processing the backside of the silicon substrate; and (D) a process which measures the thickness of the area of the silicon substrate which is reduced in the process (C).

Abstract: A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities.

Abstract: A method of measuring ion dose in a plasma immersion ion implantation reactor during ion implantation of a selected species into a workpiece includes placing the workpiece on a pedestal in the reactor and feeding into the reactor a process gas comprising a species to be implanted into the workpiece, and then coupling RF plasma source power to a plasma in the reactor. It further includes coupling RF bias power to the workpiece by an RF bias power generator that is coupled to the workpiece through a bias feedpoint of the reactor and measuring RF current at the feedpoint to generate a current-related value, and then integrating the current-related over time to produce an ion implantation dose-related value.

Abstract: A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of the finFETs, is disclosed. Threshold measurement circuits on the signal gates enable a threshold adjustment voltage from the adjustable voltage source to reduce the threshold mismatch between the finFETs. Adding a second DAC to the second finFET allows a simpler DAC design. Threshold correction may be performed during the operational life of the IC. Implementations in a differential input stage of an amplifier and in a current mirror circuit are described.